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-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp14
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 25256d901ce..dd7207b70f0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33125,6 +33125,20 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
(OpLHS == CondLHS || OpRHS == CondLHS))
return SplitOpsAndApply(DAG, Subtarget, DL, VT, { OpLHS, OpRHS },
ADDUSBuilder);
+
+ if (isa<BuildVectorSDNode>(OpRHS) && isa<BuildVectorSDNode>(CondRHS) &&
+ CondLHS == OpLHS) {
+ // If the RHS is a constant we have to reverse the const
+ // canonicalization.
+ // x > ~C ? x+C : ~0 --> addus x, C
+ auto MatchADDUS = [](ConstantSDNode *Op, ConstantSDNode *Cond) {
+ return Cond->getAPIntValue() == ~Op->getAPIntValue();
+ };
+ if (CC == ISD::SETULE &&
+ ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchADDUS))
+ return SplitOpsAndApply(DAG, Subtarget, DL, VT, { OpLHS, OpRHS },
+ ADDUSBuilder);
+ }
}
}
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