diff options
Diffstat (limited to 'llvm/lib/Target')
7 files changed, 20 insertions, 42 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td index 72efbb6c284..ec9dbffde7f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.td +++ b/llvm/lib/Target/WebAssembly/WebAssembly.td @@ -25,13 +25,6 @@ include "llvm/Target/Target.td" def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true", "Enable 128-bit SIMD">; - -def FeatureUnimplementedSIMD128 : - SubtargetFeature<"unimplemented-simd128", - "HasUnimplementedSIMD128", "true", - "Enable 128-bit SIMD not yet implemented in engines", - [FeatureSIMD128]>; - def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", "Enable Atomics">; def FeatureNontrappingFPToInt : diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 527908d039c..a452a005df7 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -44,6 +44,8 @@ using namespace PatternMatch; #define DEBUG_TYPE "wasm-fastisel" +extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs; + namespace { class WebAssemblyFastISel final : public FastISel { @@ -143,7 +145,7 @@ private: break; case MVT::v2i64: case MVT::v2f64: - if (Subtarget->hasUnimplementedSIMD128()) + if (Subtarget->hasSIMD128() && EnableUnimplementedWasmSIMDInstrs) return VT; break; default: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp index 0a7464cedc9..29678f37ae2 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -25,6 +25,8 @@ using namespace llvm; #define DEBUG_TYPE "wasm-isel" +extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs; + //===--------------------------------------------------------------------===// /// WebAssembly-specific code to select WebAssembly machine instructions for /// SelectionDAG operations. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index d0c8aacac7c..d267358db30 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -37,6 +37,12 @@ using namespace llvm; #define DEBUG_TYPE "wasm-lower" +// Emit proposed instructions that may not have been implemented in engines +cl::opt<bool> EnableUnimplementedWasmSIMDInstrs( + "wasm-enable-unimplemented-simd", + cl::desc("Emit potentially-unimplemented WebAssembly SIMD instructions"), + cl::init(false)); + WebAssemblyTargetLowering::WebAssemblyTargetLowering( const TargetMachine &TM, const WebAssemblySubtarget &STI) : TargetLowering(TM), Subtarget(&STI) { @@ -64,7 +70,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); - if (Subtarget->hasUnimplementedSIMD128()) { + if (EnableUnimplementedWasmSIMDInstrs) { addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass); } @@ -129,7 +135,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) { setOperationAction(Op, T, Expand); } - if (Subtarget->hasUnimplementedSIMD128()) { + if (EnableUnimplementedWasmSIMDInstrs) { setOperationAction(Op, MVT::v2i64, Expand); } } @@ -143,7 +149,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) { setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); } - if (Subtarget->hasUnimplementedSIMD128()) { + if (EnableUnimplementedWasmSIMDInstrs) { setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); } @@ -154,7 +160,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) setOperationAction(Op, T, Custom); - if (Subtarget->hasUnimplementedSIMD128()) + if (EnableUnimplementedWasmSIMDInstrs) for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) setOperationAction(Op, MVT::v2i64, Custom); } @@ -164,7 +170,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) { for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) setOperationAction(Op, T, Expand); - if (Subtarget->hasUnimplementedSIMD128()) + if (EnableUnimplementedWasmSIMDInstrs) for (auto T : {MVT::v2i64, MVT::v2f64}) setOperationAction(Op, T, Expand); } @@ -173,10 +179,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( // sign-extend from. setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); if (!Subtarget->hasSignExt()) { - // Sign extends are legal only when extending a vector extract - auto Action = Subtarget->hasSIMD128() ? Custom : Expand; for (auto T : {MVT::i8, MVT::i16, MVT::i32}) - setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); + setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); } for (auto T : MVT::integer_vector_valuetypes()) setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); @@ -221,7 +225,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( } // Expand additional SIMD ops that V8 hasn't implemented yet - if (Subtarget->hasSIMD128() && !Subtarget->hasUnimplementedSIMD128()) { + if (Subtarget->hasSIMD128() && !EnableUnimplementedWasmSIMDInstrs) { setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); setOperationAction(ISD::FDIV, MVT::v4f32, Expand); } @@ -232,7 +236,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); } - if (Subtarget->hasUnimplementedSIMD128()) { + if (EnableUnimplementedWasmSIMDInstrs) { for (auto T : {MVT::v2i64, MVT::v2f64}) { setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); @@ -896,8 +900,6 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op, return LowerAccessVectorElement(Op, DAG); case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); - case ISD::SIGN_EXTEND_INREG: - return LowerSIGN_EXTEND_INREG(Op, DAG); case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); case ISD::SHL: @@ -1100,22 +1102,6 @@ WebAssemblyTargetLowering::LowerINTRINSIC_VOID(SDValue Op, } SDValue -WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, - SelectionDAG &DAG) const { - // If sign extension operations are disabled, allow sext_inreg only if operand - // is a vector extract. SIMD does not depend on sign extension operations, but - // allowing sext_inreg in this context lets us have simple patterns to select - // extract_lane_s instructions. Expanding sext_inreg everywhere would be - // simpler in this file, but would necessitate large and brittle patterns to - // undo the expansion and select extract_lane_s instructions. - assert(!Subtarget->hasSignExt() && Subtarget->hasSIMD128()); - if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT) - return Op; - // Otherwise expand - return SDValue(); -} - -SDValue WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h index 59f4230ed88..80076818de7 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -99,7 +99,6 @@ private: SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const; SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td index 2f9e719431b..d172537bb34 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -20,9 +20,7 @@ def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">; def HasAddr64 : Predicate<"Subtarget->hasAddr64()">; def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">, AssemblerPredicate<"FeatureSIMD128", "simd128">; -def HasUnimplementedSIMD : - Predicate<"Subtarget->hasUnimplementedSIMD128()">, - AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">; +def HasUnimplementedSIMD : Predicate<"EnableUnimplementedWasmSIMDInstrs">; def HasAtomics : Predicate<"Subtarget->hasAtomics()">, AssemblerPredicate<"FeatureAtomics", "atomics">; def HasNontrappingFPToInt : diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h index 270d5b08241..b170dbff3b3 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h @@ -30,7 +30,6 @@ namespace llvm { class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo { bool HasSIMD128; - bool HasUnimplementedSIMD128; bool HasAtomics; bool HasNontrappingFPToInt; bool HasSignExt; @@ -79,7 +78,6 @@ public: // Predicates used by WebAssemblyInstrInfo.td. bool hasAddr64() const { return TargetTriple.isArch64Bit(); } bool hasSIMD128() const { return HasSIMD128; } - bool hasUnimplementedSIMD128() const { return HasUnimplementedSIMD128; } bool hasAtomics() const { return HasAtomics; } bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; } bool hasSignExt() const { return HasSignExt; } |
