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-rw-r--r--llvm/lib/Target/Sparc/SparcInternals.h14
-rw-r--r--llvm/lib/Target/Sparc/SparcRegClassInfo.h18
-rw-r--r--llvm/lib/Target/Sparc/SparcRegInfo.cpp2
-rw-r--r--llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp8
-rw-r--r--llvm/lib/Target/TargetSchedInfo.cpp24
-rw-r--r--llvm/lib/Target/X86/X86TargetMachine.h4
6 files changed, 35 insertions, 35 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h
index 0840522929e..e5eaa0f2227 100644
--- a/llvm/lib/Target/Sparc/SparcInternals.h
+++ b/llvm/lib/Target/Sparc/SparcInternals.h
@@ -9,10 +9,10 @@
#define SPARC_INTERNALS_H
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetCacheInfo.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/TargetOptInfo.h"
#include "llvm/Type.h"
#include <sys/types.h>
@@ -211,11 +211,11 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
//----------------------------------------------------------------------------
// class UltraSparcRegInfo
//
-// This class implements the virtual class MachineRegInfo for Sparc.
+// This class implements the virtual class TargetRegInfo for Sparc.
//
//----------------------------------------------------------------------------
-class UltraSparcRegInfo : public MachineRegInfo {
+class UltraSparcRegInfo : public TargetRegInfo {
// The actual register classes in the Sparc
//
enum RegClassIDs {
@@ -511,7 +511,7 @@ public:
//---------------------------------------------------------------------------
-class UltraSparcSchedInfo: public MachineSchedInfo {
+class UltraSparcSchedInfo: public TargetSchedInfo {
public:
UltraSparcSchedInfo(const TargetMachine &tgt);
protected:
@@ -734,8 +734,8 @@ public:
UltraSparc();
virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
- virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
- virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
+ virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
+ virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.h b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
index 467c3acf5f4..a8a39eb86a7 100644
--- a/llvm/lib/Target/Sparc/SparcRegClassInfo.h
+++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.h
@@ -7,7 +7,7 @@
#ifndef SPARC_REG_CLASS_INFO_H
#define SPARC_REG_CLASS_INFO_H
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
#include "llvm/CodeGen/IGNode.h"
//-----------------------------------------------------------------------------
@@ -15,9 +15,9 @@
//-----------------------------------------------------------------------------
-struct SparcIntRegClass : public MachineRegClassInfo {
+struct SparcIntRegClass : public TargetRegClassInfo {
SparcIntRegClass(unsigned ID)
- : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
+ : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
@@ -73,12 +73,12 @@ struct SparcIntRegClass : public MachineRegClassInfo {
// Float Register Class
//-----------------------------------------------------------------------------
-class SparcFloatRegClass : public MachineRegClassInfo {
+class SparcFloatRegClass : public TargetRegClassInfo {
int findFloatColor(const LiveRange *LR, unsigned Start,
unsigned End, std::vector<bool> &IsColorUsedArr) const;
public:
SparcFloatRegClass(unsigned ID)
- : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
+ : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
@@ -119,9 +119,9 @@ public:
// allocated for two names.
//-----------------------------------------------------------------------------
-struct SparcIntCCRegClass : public MachineRegClassInfo {
+struct SparcIntCCRegClass : public TargetRegClassInfo {
SparcIntCCRegClass(unsigned ID)
- : MachineRegClassInfo(ID, 1, 2) { }
+ : TargetRegClassInfo(ID, 1, 2) { }
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
if (IsColorUsedArr[0])
@@ -149,9 +149,9 @@ struct SparcIntCCRegClass : public MachineRegClassInfo {
// Only 4 Float CC registers are available
//-----------------------------------------------------------------------------
-struct SparcFloatCCRegClass : public MachineRegClassInfo {
+struct SparcFloatCCRegClass : public TargetRegClassInfo {
SparcFloatCCRegClass(unsigned ID)
- : MachineRegClassInfo(ID, 4, 4) { }
+ : TargetRegClassInfo(ID, 4, 4) { }
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
for(unsigned c = 0; c != 4; ++c)
diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
index 3caac417cae..e7889d2d509 100644
--- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
@@ -25,7 +25,7 @@ using std::cerr;
using std::vector;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
- : MachineRegInfo(tgt), NumOfIntArgRegs(6),
+ : TargetRegInfo(tgt), NumOfIntArgRegs(6),
NumOfFloatArgRegs(32), InvalidRegNum(1000) {
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
diff --git a/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp b/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp
index 35a0526c92f..92dc5830e5f 100644
--- a/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp
+++ b/llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp
@@ -700,12 +700,12 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
// Purpose:
// Scheduling information for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
-// class MachineSchedInfo.
+// class TargetSchedInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
- : MachineSchedInfo(tgt,
+ : TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
SparcRUsageDesc,
SparcInstrUsageDeltas,
@@ -733,8 +733,8 @@ UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
void
UltraSparcSchedInfo::initializeResources()
{
- // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
- MachineSchedInfo::initializeResources();
+ // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
+ TargetSchedInfo::initializeResources();
// Machine-dependent fixups go here. None for now.
}
diff --git a/llvm/lib/Target/TargetSchedInfo.cpp b/llvm/lib/Target/TargetSchedInfo.cpp
index 185f01ec9e8..d64652398ae 100644
--- a/llvm/lib/Target/TargetSchedInfo.cpp
+++ b/llvm/lib/Target/TargetSchedInfo.cpp
@@ -5,7 +5,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
#include "llvm/Target/TargetMachine.h"
resourceId_t MachineResource::nextId = 0;
@@ -69,17 +69,17 @@ ComputeMinGap(const InstrRUsage &fromRU,
//---------------------------------------------------------------------------
-// class MachineSchedInfo
+// class TargetSchedInfo
// Interface to machine description for instruction scheduling
//---------------------------------------------------------------------------
-MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt,
- int NumSchedClasses,
- const InstrClassRUsage* ClassRUsages,
- const InstrRUsageDelta* UsageDeltas,
- const InstrIssueDelta* IssueDeltas,
- unsigned int NumUsageDeltas,
- unsigned int NumIssueDeltas)
+TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt,
+ int NumSchedClasses,
+ const InstrClassRUsage* ClassRUsages,
+ const InstrRUsageDelta* UsageDeltas,
+ const InstrIssueDelta* IssueDeltas,
+ unsigned NumUsageDeltas,
+ unsigned NumIssueDeltas)
: target(tgt),
numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
@@ -88,7 +88,7 @@ MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt,
{}
void
-MachineSchedInfo::initializeResources()
+TargetSchedInfo::initializeResources()
{
assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
&& "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
@@ -111,7 +111,7 @@ MachineSchedInfo::initializeResources()
void
-MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
+TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
instrRUForClasses)
{
int numOpCodes = mii->getNumRealOpCodes();
@@ -141,7 +141,7 @@ MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
void
-MachineSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
+TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
instrRUForClasses)
{
int numOpCodes = mii->getNumRealOpCodes();
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index 9bf9a3779ea..35a3b6a4285 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -23,8 +23,8 @@ public:
return &InstrInfo.getRegisterInfo();
}
- virtual const MachineSchedInfo &getSchedInfo() const { abort(); }
- virtual const MachineRegInfo &getRegInfo() const { abort(); }
+ virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
+ virtual const TargetRegInfo &getRegInfo() const { abort(); }
virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
virtual const TargetOptInfo &getOptInfo() const { abort(); }
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