diff options
Diffstat (limited to 'llvm/lib/Target')
37 files changed, 652 insertions, 549 deletions
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp index 8e424f5d17b..f2fcdf60d50 100644 --- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp +++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp @@ -18,13 +18,13 @@ #include "MCTargetDesc/WebAssemblyTargetStreamer.h" #include "WebAssembly.h" #include "llvm/MC/MCContext.h" -#include "llvm/MC/MCParser/MCTargetAsmParser.h" -#include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCParser/MCTargetAsmParser.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCStreamer.h" #include "llvm/Support/Endian.h" #include "llvm/Support/TargetRegistry.h" @@ -65,18 +65,18 @@ struct WebAssemblyOperand : public MCParsedAsmOperand { }; WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, TokOp T) - : Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {} + : Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {} WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I) - : Kind(K), StartLoc(Start), EndLoc(End), Int(I) {} + : Kind(K), StartLoc(Start), EndLoc(End), Int(I) {} WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, FltOp F) - : Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {} + : Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {} WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, SymOp S) - : Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {} + : Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {} bool isToken() const override { return Kind == Token; } - bool isImm() const override { return Kind == Integer || - Kind == Float || - Kind == Symbol; } + bool isImm() const override { + return Kind == Integer || Kind == Float || Kind == Symbol; + } bool isMem() const override { return false; } bool isReg() const override { return false; } @@ -145,8 +145,8 @@ public: #include "WebAssemblyGenAsmMatcher.inc" // TODO: This is required to be implemented, but appears unused. - bool ParseRegister(unsigned &/*RegNo*/, SMLoc &/*StartLoc*/, - SMLoc &/*EndLoc*/) override { + bool ParseRegister(unsigned & /*RegNo*/, SMLoc & /*StartLoc*/, + SMLoc & /*EndLoc*/) override { llvm_unreachable("ParseRegister is not implemented."); } @@ -156,7 +156,8 @@ public: bool IsNext(AsmToken::TokenKind Kind) { auto ok = Lexer.is(Kind); - if (ok) Parser.Lex(); + if (ok) + Parser.Lex(); return ok; } @@ -190,15 +191,15 @@ public: void ParseSingleInteger(bool IsNegative, OperandVector &Operands) { auto &Int = Lexer.getTok(); int64_t Val = Int.getIntVal(); - if (IsNegative) Val = -Val; + if (IsNegative) + Val = -Val; Operands.push_back(make_unique<WebAssemblyOperand>( - WebAssemblyOperand::Integer, Int.getLoc(), - Int.getEndLoc(), WebAssemblyOperand::IntOp{Val})); + WebAssemblyOperand::Integer, Int.getLoc(), Int.getEndLoc(), + WebAssemblyOperand::IntOp{Val})); Parser.Lex(); } - bool ParseOperandStartingWithInteger(bool IsNegative, - OperandVector &Operands, + bool ParseOperandStartingWithInteger(bool IsNegative, OperandVector &Operands, StringRef InstName) { ParseSingleInteger(IsNegative, Operands); // FIXME: there is probably a cleaner way to do this. @@ -217,25 +218,24 @@ public: // We can't just call WebAssembly::GetDefaultP2Align since we don't have // an opcode until after the assembly matcher. Operands.push_back(make_unique<WebAssemblyOperand>( - WebAssemblyOperand::Integer, Offset.getLoc(), - Offset.getEndLoc(), WebAssemblyOperand::IntOp{0})); + WebAssemblyOperand::Integer, Offset.getLoc(), Offset.getEndLoc(), + WebAssemblyOperand::IntOp{0})); } } return false; } - bool ParseInstruction(ParseInstructionInfo &/*Info*/, StringRef Name, + bool ParseInstruction(ParseInstructionInfo & /*Info*/, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override { - Operands.push_back( - make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token, NameLoc, - SMLoc::getFromPointer( - NameLoc.getPointer() + Name.size()), - WebAssemblyOperand::TokOp{ - StringRef(NameLoc.getPointer(), - Name.size())})); + Operands.push_back(make_unique<WebAssemblyOperand>( + WebAssemblyOperand::Token, NameLoc, + SMLoc::getFromPointer(NameLoc.getPointer() + Name.size()), + WebAssemblyOperand::TokOp{ + StringRef(NameLoc.getPointer(), Name.size())})); auto NamePair = Name.split('.'); // If no '.', there is no type prefix. - if (NamePair.second.empty()) std::swap(NamePair.first, NamePair.second); + if (NamePair.second.empty()) + std::swap(NamePair.first, NamePair.second); while (Lexer.isNot(AsmToken::EndOfStatement)) { auto &Tok = Lexer.getTok(); switch (Tok.getKind()) { @@ -246,8 +246,8 @@ public: if (Parser.parsePrimaryExpr(Val, End)) return Error("Cannot parse symbol: ", Lexer.getTok()); Operands.push_back(make_unique<WebAssemblyOperand>( - WebAssemblyOperand::Symbol, Id.getLoc(), - Id.getEndLoc(), WebAssemblyOperand::SymOp{Val})); + WebAssemblyOperand::Symbol, Id.getLoc(), Id.getEndLoc(), + WebAssemblyOperand::SymOp{Val})); break; } case AsmToken::Minus: @@ -266,8 +266,8 @@ public: if (Tok.getString().getAsDouble(Val, false)) return Error("Cannot parse real: ", Tok); Operands.push_back(make_unique<WebAssemblyOperand>( - WebAssemblyOperand::Float, Tok.getLoc(), - Tok.getEndLoc(), WebAssemblyOperand::FltOp{Val})); + WebAssemblyOperand::Float, Tok.getLoc(), Tok.getEndLoc(), + WebAssemblyOperand::FltOp{Val})); Parser.Lex(); break; } @@ -275,7 +275,8 @@ public: return Error("Unexpected token in operand: ", Tok); } if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Expect(AsmToken::Comma, ",")) return true; + if (Expect(AsmToken::Comma, ",")) + return true; } } Parser.Lex(); @@ -285,34 +286,30 @@ public: // the wasm module is generated). if (NamePair.second == "block" || NamePair.second == "loop") { Operands.push_back(make_unique<WebAssemblyOperand>( - WebAssemblyOperand::Integer, NameLoc, - NameLoc, WebAssemblyOperand::IntOp{-1})); + WebAssemblyOperand::Integer, NameLoc, NameLoc, + WebAssemblyOperand::IntOp{-1})); } return false; } - void onLabelParsed(MCSymbol *Symbol) override { - LastLabel = Symbol; - } + void onLabelParsed(MCSymbol *Symbol) override { LastLabel = Symbol; } bool ParseDirective(AsmToken DirectiveID) override { assert(DirectiveID.getKind() == AsmToken::Identifier); auto &Out = getStreamer(); - auto &TOut = reinterpret_cast<WebAssemblyTargetStreamer &>( - *Out.getTargetStreamer()); + auto &TOut = + reinterpret_cast<WebAssemblyTargetStreamer &>(*Out.getTargetStreamer()); // TODO: we're just parsing the subset of directives we're interested in, // and ignoring ones we don't recognise. We should ideally verify // all directives here. if (DirectiveID.getString() == ".type") { // This could be the start of a function, check if followed by // "label,@function" - if (!(IsNext(AsmToken::Identifier) && - IsNext(AsmToken::Comma) && - IsNext(AsmToken::At) && - Lexer.is(AsmToken::Identifier))) + if (!(IsNext(AsmToken::Identifier) && IsNext(AsmToken::Comma) && + IsNext(AsmToken::At) && Lexer.is(AsmToken::Identifier))) return Error("Expected label,@type declaration, got: ", Lexer.getTok()); Parser.Lex(); - //Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction); + // Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction); } else if (DirectiveID.getString() == ".param" || DirectiveID.getString() == ".local") { // Track the number of locals, needed for correct virtual register @@ -322,28 +319,31 @@ public: std::vector<MVT> Locals; while (Lexer.is(AsmToken::Identifier)) { auto RegType = ParseRegType(Lexer.getTok().getString()); - if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE) return true; + if (RegType == MVT::INVALID_SIMPLE_VALUE_TYPE) + return true; if (DirectiveID.getString() == ".param") { Params.push_back(RegType); } else { Locals.push_back(RegType); } Parser.Lex(); - if (!IsNext(AsmToken::Comma)) break; + if (!IsNext(AsmToken::Comma)) + break; } assert(LastLabel); TOut.emitParam(LastLabel, Params); TOut.emitLocal(Locals); } else { // For now, ignore anydirective we don't recognize: - while (Lexer.isNot(AsmToken::EndOfStatement)) Parser.Lex(); + while (Lexer.isNot(AsmToken::EndOfStatement)) + Parser.Lex(); } return Expect(AsmToken::EndOfStatement, "EOL"); } - bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &/*Opcode*/, - OperandVector &Operands, - MCStreamer &Out, uint64_t &ErrorInfo, + bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned & /*Opcode*/, + OperandVector &Operands, MCStreamer &Out, + uint64_t &ErrorInfo, bool MatchingInlineAsm) override { MCInst Inst; unsigned MatchResult = @@ -354,8 +354,8 @@ public: return false; } case Match_MissingFeature: - return Parser.Error(IDLoc, - "instruction requires a WASM feature not currently enabled"); + return Parser.Error( + IDLoc, "instruction requires a WASM feature not currently enabled"); case Match_MnemonicFail: return Parser.Error(IDLoc, "invalid instruction"); case Match_NearMisses: diff --git a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp index b6a4bdd2957..ad0a0454c3f 100644 --- a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp @@ -57,10 +57,9 @@ void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, // FIXME: For CALL_INDIRECT_VOID, don't print a leading comma, because // we have an extra flags operand which is not currently printed, for // compatiblity reasons. - if (i != 0 && - ((MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID && - MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID_S) || - i != Desc.getNumOperands())) + if (i != 0 && ((MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID && + MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID_S) || + i != Desc.getNumOperands())) OS << ", "; printOperand(MI, i, OS); } @@ -88,12 +87,14 @@ void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, case WebAssembly::END_LOOP_S: // Have to guard against an empty stack, in case of mismatched pairs // in assembly parsing. - if (!ControlFlowStack.empty()) ControlFlowStack.pop_back(); + if (!ControlFlowStack.empty()) + ControlFlowStack.pop_back(); break; case WebAssembly::END_BLOCK: case WebAssembly::END_BLOCK_S: - if (!ControlFlowStack.empty()) printAnnotation( - OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':'); + if (!ControlFlowStack.empty()) + printAnnotation( + OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':'); break; } @@ -118,17 +119,15 @@ void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, static std::string toString(const APFloat &FP) { // Print NaNs with custom payloads specially. - if (FP.isNaN() && - !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) && + if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) && !FP.bitwiseIsEqual( APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) { APInt AI = FP.bitcastToAPInt(); - return - std::string(AI.isNegative() ? "-" : "") + "nan:0x" + - utohexstr(AI.getZExtValue() & - (AI.getBitWidth() == 32 ? INT64_C(0x007fffff) : - INT64_C(0x000fffffffffffff)), - /*LowerCase=*/true); + return std::string(AI.isNegative() ? "-" : "") + "nan:0x" + + utohexstr(AI.getZExtValue() & + (AI.getBitWidth() == 32 ? INT64_C(0x007fffff) + : INT64_C(0x000fffffffffffff)), + /*LowerCase=*/true); } // Use C99's hexadecimal floating-point representation. @@ -199,25 +198,40 @@ void WebAssemblyInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, } } -void WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand( - const MCInst *MI, unsigned OpNo, raw_ostream &O) { +void WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand(const MCInst *MI, + unsigned OpNo, + raw_ostream &O) { int64_t Imm = MI->getOperand(OpNo).getImm(); if (Imm == WebAssembly::GetDefaultP2Align(MI->getOpcode())) return; O << ":p2align=" << Imm; } -void WebAssemblyInstPrinter::printWebAssemblySignatureOperand( - const MCInst *MI, unsigned OpNo, raw_ostream &O) { +void WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI, + unsigned OpNo, + raw_ostream &O) { int64_t Imm = MI->getOperand(OpNo).getImm(); switch (WebAssembly::ExprType(Imm)) { - case WebAssembly::ExprType::Void: break; - case WebAssembly::ExprType::I32: O << "i32"; break; - case WebAssembly::ExprType::I64: O << "i64"; break; - case WebAssembly::ExprType::F32: O << "f32"; break; - case WebAssembly::ExprType::F64: O << "f64"; break; - case WebAssembly::ExprType::V128: O << "v128"; break; - case WebAssembly::ExprType::ExceptRef: O << "except_ref"; break; + case WebAssembly::ExprType::Void: + break; + case WebAssembly::ExprType::I32: + O << "i32"; + break; + case WebAssembly::ExprType::I64: + O << "i64"; + break; + case WebAssembly::ExprType::F32: + O << "f32"; + break; + case WebAssembly::ExprType::F64: + O << "f64"; + break; + case WebAssembly::ExprType::V128: + O << "v128"; + break; + case WebAssembly::ExprType::ExceptRef: + O << "except_ref"; + break; } } diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp index 244c2189b45..0726dd48117 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp @@ -73,13 +73,13 @@ public: const MCFixupKindInfo & WebAssemblyAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { const static MCFixupKindInfo Infos[WebAssembly::NumTargetFixupKinds] = { - // This table *must* be in the order that the fixup_* kinds are defined in - // WebAssemblyFixupKinds.h. - // - // Name Offset (bits) Size (bits) Flags - { "fixup_code_sleb128_i32", 0, 5*8, 0 }, - { "fixup_code_sleb128_i64", 0, 10*8, 0 }, - { "fixup_code_uleb128_i32", 0, 5*8, 0 }, + // This table *must* be in the order that the fixup_* kinds are defined in + // WebAssemblyFixupKinds.h. + // + // Name Offset (bits) Size (bits) Flags + {"fixup_code_sleb128_i32", 0, 5 * 8, 0}, + {"fixup_code_sleb128_i64", 0, 10 * 8, 0}, + {"fixup_code_uleb128_i32", 0, 5 * 8, 0}, }; if (Kind < FirstTargetFixupKind) diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h index 23d0de15ea9..c2fac5f93a2 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h @@ -15,9 +15,9 @@ namespace llvm { namespace WebAssembly { enum Fixups { - fixup_code_sleb128_i32 = FirstTargetFixupKind, // 32-bit signed - fixup_code_sleb128_i64, // 64-bit signed - fixup_code_uleb128_i32, // 32-bit unsigned + fixup_code_sleb128_i32 = FirstTargetFixupKind, // 32-bit signed + fixup_code_sleb128_i64, // 64-bit signed + fixup_code_uleb128_i32, // 32-bit unsigned // Marker LastTargetFixupKind, diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp index 3f24f93fe92..fa399371f2c 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp @@ -67,8 +67,7 @@ void WebAssemblyMCCodeEmitter::encodeInstruction( OS << uint8_t(Binary); } else { assert(Binary <= UINT16_MAX && "Several-byte opcodes not supported yet"); - OS << uint8_t(Binary >> 8) - << uint8_t(Binary); + OS << uint8_t(Binary >> 8) << uint8_t(Binary); } // For br_table instructions, encode the size of the table. In the MCInst, @@ -162,9 +161,8 @@ void WebAssemblyMCCodeEmitter::encodeInstruction( } else { llvm_unreachable("unexpected symbolic operand kind"); } - Fixups.push_back(MCFixup::create( - OS.tell() - Start, MO.getExpr(), - FixupKind, MI.getLoc())); + Fixups.push_back(MCFixup::create(OS.tell() - Start, MO.getExpr(), + FixupKind, MI.getLoc())); ++MCNumFixups; encodeULEB128(0, OS, PaddedSize); } else { diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp index baf8a0c96c0..55478353ecc 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -125,11 +125,17 @@ extern "C" void LLVMInitializeWebAssemblyTargetMC() { wasm::ValType WebAssembly::toValType(const MVT &Ty) { switch (Ty.SimpleTy) { - case MVT::i32: return wasm::ValType::I32; - case MVT::i64: return wasm::ValType::I64; - case MVT::f32: return wasm::ValType::F32; - case MVT::f64: return wasm::ValType::F64; - case MVT::ExceptRef: return wasm::ValType::EXCEPT_REF; - default: llvm_unreachable("unexpected type"); + case MVT::i32: + return wasm::ValType::I32; + case MVT::i64: + return wasm::ValType::I64; + case MVT::f32: + return wasm::ValType::F32; + case MVT::f64: + return wasm::ValType::F64; + case MVT::ExceptRef: + return wasm::ValType::EXCEPT_REF; + default: + llvm_unreachable("unexpected type"); } } diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h index 8477bdc3618..730bb8d6c79 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h @@ -96,8 +96,8 @@ enum TOF { // Flags to indicate the type of the symbol being referenced MO_SYMBOL_FUNCTION = 0x1, - MO_SYMBOL_GLOBAL = 0x2, - MO_SYMBOL_MASK = 0x3, + MO_SYMBOL_GLOBAL = 0x2, + MO_SYMBOL_MASK = 0x3, }; } // end namespace WebAssemblyII diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp index 5272e188e1d..961ef8146a9 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp @@ -85,7 +85,8 @@ void WebAssemblyTargetAsmStreamer::emitLocal(ArrayRef<MVT> Types) { void WebAssemblyTargetAsmStreamer::emitEndFunc() { OS << "\t.endfunc\n"; } void WebAssemblyTargetAsmStreamer::emitIndirectFunctionType( - MCSymbol *Symbol, SmallVectorImpl<MVT> &Params, SmallVectorImpl<MVT> &Results) { + MCSymbol *Symbol, SmallVectorImpl<MVT> &Params, + SmallVectorImpl<MVT> &Results) { OS << "\t.functype\t" << Symbol->getName(); if (Results.empty()) OS << ", void"; diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h index cafcb04ccd1..124161c5579 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h @@ -65,8 +65,7 @@ public: void emitResult(MCSymbol *Symbol, ArrayRef<MVT> Types) override; void emitLocal(ArrayRef<MVT> Types) override; void emitEndFunc() override; - void emitIndirectFunctionType(MCSymbol *Symbol, - SmallVectorImpl<MVT> &Params, + void emitIndirectFunctionType(MCSymbol *Symbol, SmallVectorImpl<MVT> &Params, SmallVectorImpl<MVT> &Results) override; void emitIndIdx(const MCExpr *Value) override; void emitGlobalImport(StringRef name) override; @@ -82,8 +81,7 @@ public: void emitResult(MCSymbol *Symbol, ArrayRef<MVT> Types) override; void emitLocal(ArrayRef<MVT> Types) override; void emitEndFunc() override; - void emitIndirectFunctionType(MCSymbol *Symbol, - SmallVectorImpl<MVT> &Params, + void emitIndirectFunctionType(MCSymbol *Symbol, SmallVectorImpl<MVT> &Params, SmallVectorImpl<MVT> &Results) override; void emitIndIdx(const MCExpr *Value) override; void emitGlobalImport(StringRef name) override; diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyWasmObjectWriter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyWasmObjectWriter.cpp index dc876ab585b..d9ed146ede7 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyWasmObjectWriter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyWasmObjectWriter.cpp @@ -86,9 +86,8 @@ static bool IsGlobalType(const MCValue &Target) { return RefA && RefA->getKind() == MCSymbolRefExpr::VK_WebAssembly_GLOBAL; } -unsigned -WebAssemblyWasmObjectWriter::getRelocType(const MCValue &Target, - const MCFixup &Fixup) const { +unsigned WebAssemblyWasmObjectWriter::getRelocType(const MCValue &Target, + const MCFixup &Fixup) const { // WebAssembly functions are not allocated in the data address space. To // resolve a pointer to a function, we must use a special relocation type. bool IsFunction = IsFunctionExpr(Fixup.getValue()); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp index 4af9cd150bf..a4d276c7936 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAddMissingPrototypes.cpp @@ -24,10 +24,10 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Module.h" #include "llvm/IR/Operator.h" -#include "llvm/Transforms/Utils/ModuleUtils.h" -#include "llvm/Transforms/Utils/Local.h" #include "llvm/Pass.h" #include "llvm/Support/Debug.h" +#include "llvm/Transforms/Utils/Local.h" +#include "llvm/Transforms/Utils/ModuleUtils.h" using namespace llvm; #define DEBUG_TYPE "wasm-add-missing-prototypes" @@ -62,14 +62,15 @@ ModulePass *llvm::createWebAssemblyAddMissingPrototypes() { bool WebAssemblyAddMissingPrototypes::runOnModule(Module &M) { LLVM_DEBUG(dbgs() << "runnning AddMissingPrototypes\n"); - std::vector<std::pair<Function*, Function*>> Replacements; + std::vector<std::pair<Function *, Function *>> Replacements; // Find all the prototype-less function declarations for (Function &F : M) { if (!F.isDeclaration() || !F.hasFnAttribute("no-prototype")) continue; - LLVM_DEBUG(dbgs() << "Found no-prototype function: " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Found no-prototype function: " << F.getName() + << "\n"); // When clang emits prototype-less C functions it uses (...), i.e. varargs // function that take no arguments (have no sentinel). When we see a @@ -83,11 +84,10 @@ bool WebAssemblyAddMissingPrototypes::runOnModule(Module &M) { "Functions with 'no-prototype' attribute should not have params: " + F.getName()); - // Create a function prototype based on the first call site (first bitcast) // that we find. FunctionType *NewType = nullptr; - Function* NewF = nullptr; + Function *NewF = nullptr; for (Use &U : F.uses()) { LLVM_DEBUG(dbgs() << "prototype-less use: " << F.getName() << "\n"); if (BitCastOperator *BC = dyn_cast<BitCastOperator>(U.getUser())) { @@ -134,8 +134,8 @@ bool WebAssemblyAddMissingPrototypes::runOnModule(Module &M) { // Finally replace the old function declarations with the new ones for (auto &Pair : Replacements) { - Function* Old = Pair.first; - Function* New = Pair.second; + Function *Old = Pair.first; + Function *New = Pair.second; Old->eraseFromParent(); M.getFunctionList().push_back(New); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index c6aa0a77fff..20b41e1ffab 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -90,8 +90,8 @@ void WebAssemblyAsmPrinter::EmitEndOfAsmFile(Module &M) { if (TM.getTargetTriple().isOSBinFormatWasm() && F.hasFnAttribute("wasm-import-module")) { MCSymbolWasm *WasmSym = cast<MCSymbolWasm>(Sym); - StringRef Name = F.getFnAttribute("wasm-import-module") - .getValueAsString(); + StringRef Name = + F.getFnAttribute("wasm-import-module").getValueAsString(); getTargetStreamer()->emitImportModule(WasmSym, Name); } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h index 23817b4e512..97b1ae578b5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h @@ -29,8 +29,8 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyAsmPrinter final : public AsmPrinter { public: explicit WebAssemblyAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) - : AsmPrinter(TM, std::move(Streamer)), - Subtarget(nullptr), MRI(nullptr), MFI(nullptr) {} + : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), MRI(nullptr), + MFI(nullptr) {} StringRef getPassName() const override { return "WebAssembly Assembly Printer"; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp index c8e7fe4caef..e62b8b60d0d 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp @@ -97,8 +97,8 @@ public: char WebAssemblyCFGStackify::ID = 0; INITIALIZE_PASS(WebAssemblyCFGStackify, DEBUG_TYPE, - "Insert BLOCK and LOOP markers for WebAssembly scopes", - false, false) + "Insert BLOCK and LOOP markers for WebAssembly scopes", false, + false) FunctionPass *llvm::createWebAssemblyCFGStackify() { return new WebAssemblyCFGStackify(); @@ -633,10 +633,18 @@ void WebAssemblyCFGStackify::fixEndsAtEndOfFunction(MachineFunction &MF) { WebAssembly::ExprType retType; switch (MFI.getResults().front().SimpleTy) { - case MVT::i32: retType = WebAssembly::ExprType::I32; break; - case MVT::i64: retType = WebAssembly::ExprType::I64; break; - case MVT::f32: retType = WebAssembly::ExprType::F32; break; - case MVT::f64: retType = WebAssembly::ExprType::F64; break; + case MVT::i32: + retType = WebAssembly::ExprType::I32; + break; + case MVT::i64: + retType = WebAssembly::ExprType::I64; + break; + case MVT::f32: + retType = WebAssembly::ExprType::F32; + break; + case MVT::f64: + retType = WebAssembly::ExprType::F64; + break; case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: @@ -645,8 +653,11 @@ void WebAssemblyCFGStackify::fixEndsAtEndOfFunction(MachineFunction &MF) { case MVT::v2f64: retType = WebAssembly::ExprType::V128; break; - case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break; - default: llvm_unreachable("unexpected return type"); + case MVT::ExceptRef: + retType = WebAssembly::ExprType::ExceptRef; + break; + default: + llvm_unreachable("unexpected return type"); } for (MachineBasicBlock &MBB : reverse(MF)) { @@ -669,9 +680,8 @@ void WebAssemblyCFGStackify::fixEndsAtEndOfFunction(MachineFunction &MF) { // WebAssembly functions end with an end instruction, as if the function body // were a block. -static void AppendEndToFunction( - MachineFunction &MF, - const WebAssemblyInstrInfo &TII) { +static void AppendEndToFunction(MachineFunction &MF, + const WebAssemblyInstrInfo &TII) { BuildMI(MF.back(), MF.back().end(), MF.back().findPrevDebugLoc(MF.back().end()), TII.get(WebAssembly::END_FUNCTION)); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp index 85b8bd6759d..326e838052d 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp @@ -64,18 +64,30 @@ FunctionPass *llvm::createWebAssemblyCallIndirectFixup() { static unsigned GetNonPseudoCallIndirectOpcode(const MachineInstr &MI) { switch (MI.getOpcode()) { using namespace WebAssembly; - case PCALL_INDIRECT_VOID: return CALL_INDIRECT_VOID; - case PCALL_INDIRECT_I32: return CALL_INDIRECT_I32; - case PCALL_INDIRECT_I64: return CALL_INDIRECT_I64; - case PCALL_INDIRECT_F32: return CALL_INDIRECT_F32; - case PCALL_INDIRECT_F64: return CALL_INDIRECT_F64; - case PCALL_INDIRECT_v16i8: return CALL_INDIRECT_v16i8; - case PCALL_INDIRECT_v8i16: return CALL_INDIRECT_v8i16; - case PCALL_INDIRECT_v4i32: return CALL_INDIRECT_v4i32; - case PCALL_INDIRECT_v2i64: return CALL_INDIRECT_v2i64; - case PCALL_INDIRECT_v4f32: return CALL_INDIRECT_v4f32; - case PCALL_INDIRECT_v2f64: return CALL_INDIRECT_v2f64; - default: return INSTRUCTION_LIST_END; + case PCALL_INDIRECT_VOID: + return CALL_INDIRECT_VOID; + case PCALL_INDIRECT_I32: + return CALL_INDIRECT_I32; + case PCALL_INDIRECT_I64: + return CALL_INDIRECT_I64; + case PCALL_INDIRECT_F32: + return CALL_INDIRECT_F32; + case PCALL_INDIRECT_F64: + return CALL_INDIRECT_F64; + case PCALL_INDIRECT_v16i8: + return CALL_INDIRECT_v16i8; + case PCALL_INDIRECT_v8i16: + return CALL_INDIRECT_v8i16; + case PCALL_INDIRECT_v4i32: + return CALL_INDIRECT_v4i32; + case PCALL_INDIRECT_v2i64: + return CALL_INDIRECT_v2i64; + case PCALL_INDIRECT_v4f32: + return CALL_INDIRECT_v4f32; + case PCALL_INDIRECT_v2f64: + return CALL_INDIRECT_v2f64; + default: + return INSTRUCTION_LIST_END; } } @@ -112,10 +124,8 @@ bool WebAssemblyCallIndirectFixup::runOnMachineFunction(MachineFunction &MF) { Ops.push_back(MachineOperand::CreateImm(0)); for (const MachineOperand &MO : - make_range(MI.operands_begin() + - MI.getDesc().getNumDefs() + 1, - MI.operands_begin() + - MI.getNumExplicitOperands())) + make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1, + MI.operands_begin() + MI.getNumExplicitOperands())) Ops.push_back(MO); Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs())); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp index 84683d48a90..dca7902b8fb 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp @@ -13,8 +13,8 @@ //===----------------------------------------------------------------------===// #include "WebAssemblyExceptionInfo.h" -#include "WebAssemblyUtilities.h" #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" +#include "WebAssemblyUtilities.h" #include "llvm/ADT/PostOrderIterator.h" #include "llvm/CodeGen/MachineDominanceFrontier.h" #include "llvm/CodeGen/MachineDominators.h" diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 20482c85446..8dc535445d6 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -114,8 +114,8 @@ private: // Utility helper routines MVT::SimpleValueType getSimpleType(Type *Ty) { EVT VT = TLI.getValueType(DL, Ty, /*HandleUnknown=*/true); - return VT.isSimple() ? VT.getSimpleVT().SimpleTy : - MVT::INVALID_SIMPLE_VALUE_TYPE; + return VT.isSimple() ? VT.getSimpleVT().SimpleTy + : MVT::INVALID_SIMPLE_VALUE_TYPE; } MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { switch (VT) { @@ -155,11 +155,9 @@ private: MVT::SimpleValueType From); unsigned signExtendToI32(unsigned Reg, const Value *V, MVT::SimpleValueType From); - unsigned zeroExtend(unsigned Reg, const Value *V, - MVT::SimpleValueType From, + unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From, MVT::SimpleValueType To); - unsigned signExtend(unsigned Reg, const Value *V, - MVT::SimpleValueType From, + unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From, MVT::SimpleValueType To); unsigned getRegForUnsignedValue(const Value *V); unsigned getRegForSignedValue(const Value *V); @@ -376,14 +374,12 @@ void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) { if (Addr.isRegBase()) { unsigned Reg = Addr.getReg(); if (Reg == 0) { - Reg = createResultReg(Subtarget->hasAddr64() ? - &WebAssembly::I64RegClass : - &WebAssembly::I32RegClass); - unsigned Opc = Subtarget->hasAddr64() ? - WebAssembly::CONST_I64 : - WebAssembly::CONST_I32; + Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass + : &WebAssembly::I32RegClass); + unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 + : WebAssembly::CONST_I32; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) - .addImm(0); + .addImm(0); Addr.setReg(Reg); } } @@ -459,13 +455,13 @@ unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V, unsigned Imm = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::CONST_I32), Imm) - .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits())); + .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits())); unsigned Result = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::AND_I32), Result) - .addReg(Reg) - .addReg(Imm); + .addReg(Reg) + .addReg(Imm); return Result; } @@ -489,19 +485,19 @@ unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V, unsigned Imm = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::CONST_I32), Imm) - .addImm(32 - MVT(From).getSizeInBits()); + .addImm(32 - MVT(From).getSizeInBits()); unsigned Left = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::SHL_I32), Left) - .addReg(Reg) - .addReg(Imm); + .addReg(Reg) + .addReg(Imm); unsigned Right = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::SHR_S_I32), Right) - .addReg(Left) - .addReg(Imm); + .addReg(Left) + .addReg(Imm); return Right; } @@ -564,8 +560,7 @@ unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) { unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V, bool IsSigned) { - return IsSigned ? getRegForSignedValue(V) : - getRegForUnsignedValue(V); + return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V); } unsigned WebAssemblyFastISel::notValue(unsigned Reg) { @@ -574,15 +569,15 @@ unsigned WebAssemblyFastISel::notValue(unsigned Reg) { unsigned NotReg = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::EQZ_I32), NotReg) - .addReg(Reg); + .addReg(Reg); return NotReg; } unsigned WebAssemblyFastISel::copyValue(unsigned Reg) { unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(WebAssembly::COPY), ResultReg) - .addReg(Reg); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY), + ResultReg) + .addReg(Reg); return ResultReg; } @@ -591,12 +586,11 @@ unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) { FuncInfo.StaticAllocaMap.find(AI); if (SI != FuncInfo.StaticAllocaMap.end()) { - unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? - &WebAssembly::I64RegClass : - &WebAssembly::I32RegClass); - unsigned Opc = Subtarget->hasAddr64() ? - WebAssembly::COPY_I64 : - WebAssembly::COPY_I32; + unsigned ResultReg = + createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass + : &WebAssembly::I32RegClass); + unsigned Opc = + Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) .addFrameIndex(SI->second); return ResultReg; @@ -607,14 +601,13 @@ unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) { unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) { if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) { - unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? - &WebAssembly::I64RegClass : - &WebAssembly::I32RegClass); - unsigned Opc = Subtarget->hasAddr64() ? - WebAssembly::CONST_I64 : - WebAssembly::CONST_I32; + unsigned ResultReg = + createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass + : &WebAssembly::I32RegClass); + unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 + : WebAssembly::CONST_I32; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) - .addGlobalAddress(GV); + .addGlobalAddress(GV); return ResultReg; } @@ -701,7 +694,7 @@ bool WebAssemblyFastISel::fastLowerArguments() { } unsigned ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) - .addImm(i); + .addImm(i); updateValueMap(&Arg, ResultReg); ++i; @@ -720,7 +713,8 @@ bool WebAssemblyFastISel::fastLowerArguments() { } if (!F->getReturnType()->isVoidTy()) { - MVT::SimpleValueType RetTy = getLegalType(getSimpleType(F->getReturnType())); + MVT::SimpleValueType RetTy = + getLegalType(getSimpleType(F->getReturnType())); if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) { MFI->clearParamsAndResults(); return false; @@ -778,33 +772,33 @@ bool WebAssemblyFastISel::selectCall(const Instruction *I) { ResultReg = createResultReg(&WebAssembly::F64RegClass); break; case MVT::v16i8: - Opc = - IsDirect ? WebAssembly::CALL_v16i8 : WebAssembly::PCALL_INDIRECT_v16i8; + Opc = IsDirect ? WebAssembly::CALL_v16i8 + : WebAssembly::PCALL_INDIRECT_v16i8; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; case MVT::v8i16: - Opc = - IsDirect ? WebAssembly::CALL_v8i16 : WebAssembly::PCALL_INDIRECT_v8i16; + Opc = IsDirect ? WebAssembly::CALL_v8i16 + : WebAssembly::PCALL_INDIRECT_v8i16; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; case MVT::v4i32: - Opc = - IsDirect ? WebAssembly::CALL_v4i32 : WebAssembly::PCALL_INDIRECT_v4i32; + Opc = IsDirect ? WebAssembly::CALL_v4i32 + : WebAssembly::PCALL_INDIRECT_v4i32; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; case MVT::v2i64: - Opc = - IsDirect ? WebAssembly::CALL_v2i64 : WebAssembly::PCALL_INDIRECT_v2i64; + Opc = IsDirect ? WebAssembly::CALL_v2i64 + : WebAssembly::PCALL_INDIRECT_v2i64; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; case MVT::v4f32: - Opc = - IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32; + Opc = IsDirect ? WebAssembly::CALL_v4f32 + : WebAssembly::PCALL_INDIRECT_v4f32; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; case MVT::v2f64: - Opc = - IsDirect ? WebAssembly::CALL_v2f64 : WebAssembly::PCALL_INDIRECT_v2f64; + Opc = IsDirect ? WebAssembly::CALL_v2f64 + : WebAssembly::PCALL_INDIRECT_v2f64; ResultReg = createResultReg(&WebAssembly::V128RegClass); break; case MVT::ExceptRef: @@ -873,11 +867,11 @@ bool WebAssemblyFastISel::selectSelect(const Instruction *I) { const SelectInst *Select = cast<SelectInst>(I); bool Not; - unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); + unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); if (CondReg == 0) return false; - unsigned TrueReg = getRegForValue(Select->getTrueValue()); + unsigned TrueReg = getRegForValue(Select->getTrueValue()); if (TrueReg == 0) return false; @@ -920,9 +914,9 @@ bool WebAssemblyFastISel::selectSelect(const Instruction *I) { unsigned ResultReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) - .addReg(TrueReg) - .addReg(FalseReg) - .addReg(CondReg); + .addReg(TrueReg) + .addReg(FalseReg) + .addReg(CondReg); updateValueMap(Select, ResultReg); return true; @@ -1022,7 +1016,8 @@ bool WebAssemblyFastISel::selectICmp(const Instruction *I) { Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64; isSigned = true; break; - default: return false; + default: + return false; } unsigned LHS = getRegForPromotedValue(ICmp->getOperand(0), isSigned); @@ -1230,7 +1225,8 @@ bool WebAssemblyFastISel::selectStore(const Instruction *I) { case MVT::f64: Opc = WebAssembly::STORE_F64; break; - default: return false; + default: + return false; } materializeLoadStoreOperands(Addr); @@ -1295,8 +1291,10 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) { unsigned Opc; switch (getSimpleType(RV->getType())) { - case MVT::i1: case MVT::i8: - case MVT::i16: case MVT::i32: + case MVT::i1: + case MVT::i8: + case MVT::i16: + case MVT::i32: Opc = WebAssembly::RETURN_I32; break; case MVT::i64: @@ -1329,7 +1327,8 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) { case MVT::ExceptRef: Opc = WebAssembly::RETURN_EXCEPT_REF; break; - default: return false; + default: + return false; } unsigned Reg; @@ -1359,19 +1358,32 @@ bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) { if (selectCall(I)) return true; break; - case Instruction::Select: return selectSelect(I); - case Instruction::Trunc: return selectTrunc(I); - case Instruction::ZExt: return selectZExt(I); - case Instruction::SExt: return selectSExt(I); - case Instruction::ICmp: return selectICmp(I); - case Instruction::FCmp: return selectFCmp(I); - case Instruction::BitCast: return selectBitCast(I); - case Instruction::Load: return selectLoad(I); - case Instruction::Store: return selectStore(I); - case Instruction::Br: return selectBr(I); - case Instruction::Ret: return selectRet(I); - case Instruction::Unreachable: return selectUnreachable(I); - default: break; + case Instruction::Select: + return selectSelect(I); + case Instruction::Trunc: + return selectTrunc(I); + case Instruction::ZExt: + return selectZExt(I); + case Instruction::SExt: + return selectSExt(I); + case Instruction::ICmp: + return selectICmp(I); + case Instruction::FCmp: + return selectFCmp(I); + case Instruction::BitCast: + return selectBitCast(I); + case Instruction::Load: + return selectLoad(I); + case Instruction::Store: + return selectStore(I); + case Instruction::Br: + return selectBr(I); + case Instruction::Ret: + return selectRet(I); + case Instruction::Unreachable: + return selectUnreachable(I); + default: + break; } // Fall back to target-independent instruction selection. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp index 4050bd9e7b6..179dcc50540 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp @@ -36,10 +36,10 @@ using namespace llvm; #define DEBUG_TYPE "wasm-fix-function-bitcasts" -static cl::opt<bool> TemporaryWorkarounds( - "wasm-temporary-workarounds", - cl::desc("Apply certain temporary workarounds"), - cl::init(true), cl::Hidden); +static cl::opt<bool> + TemporaryWorkarounds("wasm-temporary-workarounds", + cl::desc("Apply certain temporary workarounds"), + cl::init(true), cl::Hidden); namespace { class FixFunctionBitcasts final : public ModulePass { @@ -108,7 +108,7 @@ static void FindUses(Value *V, Function &F, // instead). // // If there is a type mismatch that we know would result in an invalid wasm -// module then generate wrapper that contains unreachable (i.e. abort at +// module then generate wrapper that contains unreachable (i.e. abort at // runtime). Such programs are deep into undefined behaviour territory, // but we choose to fail at runtime rather than generate and invalid module // or fail at compiler time. The reason we delay the error is that we want @@ -117,7 +117,7 @@ static void FindUses(Value *V, Function &F, // CMake detects the existence of a function in a toolchain). // // For bitcasts that involve struct types we don't know at this stage if they -// would be equivalent at the wasm level and so we can't know if we need to +// would be equivalent at the wasm level and so we can't know if we need to // generate a wrapper. static Function *CreateWrapper(Function *F, FunctionType *Ty) { Module *M = F->getParent(); @@ -212,7 +212,8 @@ static Function *CreateWrapper(Function *F, FunctionType *Ty) { if (TypeMismatch) { // Create a new wrapper that simply contains `unreachable`. Wrapper->eraseFromParent(); - Wrapper = Function::Create(Ty, Function::PrivateLinkage, F->getName() + "_bitcast_invalid", M); + Wrapper = Function::Create(Ty, Function::PrivateLinkage, + F->getName() + "_bitcast_invalid", M); BasicBlock *BB = BasicBlock::Create(M->getContext(), "body", Wrapper); new UnreachableInst(M->getContext(), BB); Wrapper->setName(F->getName() + "_bitcast_invalid"); @@ -243,19 +244,15 @@ bool FixFunctionBitcasts::runOnModule(Module &M) { if (!TemporaryWorkarounds && !F.isDeclaration() && F.getName() == "main") { Main = &F; LLVMContext &C = M.getContext(); - Type *MainArgTys[] = { - PointerType::get(Type::getInt8PtrTy(C), 0), - Type::getInt32Ty(C) - }; + Type *MainArgTys[] = {PointerType::get(Type::getInt8PtrTy(C), 0), + Type::getInt32Ty(C)}; FunctionType *MainTy = FunctionType::get(Type::getInt32Ty(C), MainArgTys, /*isVarArg=*/false); if (F.getFunctionType() != MainTy) { - Value *Args[] = { - UndefValue::get(MainArgTys[0]), - UndefValue::get(MainArgTys[1]) - }; - Value *Casted = ConstantExpr::getBitCast(Main, - PointerType::get(MainTy, 0)); + Value *Args[] = {UndefValue::get(MainArgTys[0]), + UndefValue::get(MainArgTys[1])}; + Value *Casted = + ConstantExpr::getBitCast(Main, PointerType::get(MainTy, 0)); CallMain = CallInst::Create(Casted, Args, "call_main"); Use *UseMain = &CallMain->getOperandUse(2); Uses.push_back(std::make_pair(UseMain, &F)); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp index b132b31ef04..9db34304213 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp @@ -43,8 +43,7 @@ using namespace llvm; /// require stricter alignment than the stack pointer itself. Because we need /// to shift the stack pointer by some unknown amount to force the alignment, /// we need to record the value of the stack pointer on entry to the function. -bool WebAssemblyFrameLowering::hasBP( - const MachineFunction &MF) const { +bool WebAssemblyFrameLowering::hasBP(const MachineFunction &MF) const { const auto *RegInfo = MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo(); return RegInfo->needsStackRealignment(MF); @@ -158,7 +157,8 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF, assert(MFI.getCalleeSavedInfo().empty() && "WebAssembly should not have callee-saved registers"); - if (!needsSP(MF)) return; + if (!needsSP(MF)) + return; uint64_t StackSize = MFI.getStackSize(); const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); @@ -202,7 +202,7 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF, unsigned BitmaskReg = MRI.createVirtualRegister(PtrRC); unsigned Alignment = MFI.getMaxAlignment(); assert((1u << countTrailingZeros(Alignment)) == Alignment && - "Alignment must be a power of 2"); + "Alignment must be a power of 2"); BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), BitmaskReg) .addImm((int)~(Alignment - 1)); BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::AND_I32), @@ -214,8 +214,7 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF, // Unlike most conventional targets (where FP points to the saved FP), // FP points to the bottom of the fixed-size locals, so we can use positive // offsets in load/store instructions. - BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), - WebAssembly::FP32) + BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), WebAssembly::FP32) .addReg(WebAssembly::SP32); } if (StackSize && needsSPWriteback(MF)) { @@ -226,7 +225,8 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF, void WebAssemblyFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { uint64_t StackSize = MF.getFrameInfo().getStackSize(); - if (!needsSP(MF) || !needsSPWriteback(MF)) return; + if (!needsSP(MF) || !needsSPWriteback(MF)) + return; const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); auto &MRI = MF.getRegInfo(); auto InsertPt = MBB.getFirstTerminator(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h index 03a6b7c3ad1..c6fa8261b03 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h @@ -22,7 +22,7 @@ namespace llvm { class MachineFrameInfo; class WebAssemblyFrameLowering final : public TargetFrameLowering { - public: +public: /// Size of the red zone for the user stack (leaf functions can use this much /// space below the stack pointer without writing it back to __stack_pointer /// global). @@ -35,9 +35,9 @@ class WebAssemblyFrameLowering final : public TargetFrameLowering { /*TransientStackAlignment=*/16, /*StackRealignable=*/true) {} - MachineBasicBlock::iterator eliminateCallFramePseudoInstr( - MachineFunction &MF, MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const override; + MachineBasicBlock::iterator + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; /// These methods insert prolog and epilog code into the function. void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; @@ -61,6 +61,6 @@ private: bool needsSPWriteback(const MachineFunction &MF) const; }; -} // end namespace llvm +} // end namespace llvm #endif diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index b3cd27b1b8f..b3775ce4ff6 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -95,8 +95,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) setCondCodeAction(CC, T, Expand); // Expand floating-point library function operators. - for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, - ISD::FMA}) + for (auto Op : + {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) setOperationAction(Op, T, Expand); // Note supported floating-point library function operators that otherwise // default to expand. @@ -116,10 +116,9 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( for (auto T : {MVT::i32, MVT::i64}) { // Expand unavailable integer operations. for (auto Op : - {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, - ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, - ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, - ISD::SUBE}) { + {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, + ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, + ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { setOperationAction(Op, T, Expand); } } @@ -201,7 +200,8 @@ bool WebAssemblyTargetLowering::isOffsetFoldingLegal( MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/, EVT VT) const { unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1); - if (BitWidth > 1 && BitWidth < 8) BitWidth = 8; + if (BitWidth > 1 && BitWidth < 8) + BitWidth = 8; if (BitWidth > 64) { // The shift will be lowered to a libcall, and compiler-rt libcalls expect @@ -220,17 +220,11 @@ MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/, // Lower an fp-to-int conversion operator from the LLVM opcode, which has an // undefined result on invalid/overflow, to the WebAssembly opcode, which // traps on invalid/overflow. -static MachineBasicBlock * -LowerFPToInt( - MachineInstr &MI, - DebugLoc DL, - MachineBasicBlock *BB, - const TargetInstrInfo &TII, - bool IsUnsigned, - bool Int64, - bool Float64, - unsigned LoweredOpcode -) { +static MachineBasicBlock *LowerFPToInt(MachineInstr &MI, DebugLoc DL, + MachineBasicBlock *BB, + const TargetInstrInfo &TII, + bool IsUnsigned, bool Int64, + bool Float64, unsigned LoweredOpcode) { MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); unsigned OutReg = MI.getOperand(0).getReg(); @@ -262,8 +256,7 @@ LowerFPToInt( // Transfer the remainder of BB and its successor edges to DoneMBB. DoneMBB->splice(DoneMBB->begin(), BB, - std::next(MachineBasicBlock::iterator(MI)), - BB->end()); + std::next(MachineBasicBlock::iterator(MI)), BB->end()); DoneMBB->transferSuccessorsAndUpdatePHIs(BB); BB->addSuccessor(TrueMBB); @@ -285,45 +278,33 @@ LowerFPToInt( if (IsUnsigned) { Tmp0 = InReg; } else { - BuildMI(BB, DL, TII.get(Abs), Tmp0) - .addReg(InReg); + BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); } BuildMI(BB, DL, TII.get(FConst), Tmp1) .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal))); - BuildMI(BB, DL, TII.get(LT), CmpReg) - .addReg(Tmp0) - .addReg(Tmp1); + BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); // For unsigned numbers, we have to do a separate comparison with zero. if (IsUnsigned) { Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); - unsigned SecondCmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); + unsigned SecondCmpReg = + MRI.createVirtualRegister(&WebAssembly::I32RegClass); unsigned AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); BuildMI(BB, DL, TII.get(FConst), Tmp1) .addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, 0.0))); - BuildMI(BB, DL, TII.get(GE), SecondCmpReg) - .addReg(Tmp0) - .addReg(Tmp1); - BuildMI(BB, DL, TII.get(And), AndReg) - .addReg(CmpReg) - .addReg(SecondCmpReg); + BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); + BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); CmpReg = AndReg; } - BuildMI(BB, DL, TII.get(Eqz), EqzReg) - .addReg(CmpReg); + BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg); // Create the CFG diamond to select between doing the conversion or using // the substitute value. - BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)) - .addMBB(TrueMBB) - .addReg(EqzReg); - BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg) - .addReg(InReg); - BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR)) - .addMBB(DoneMBB); - BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg) - .addImm(Substitute); + BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg); + BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); + BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR)).addMBB(DoneMBB); + BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg) .addReg(FalseReg) .addMBB(FalseMBB) @@ -333,16 +314,14 @@ LowerFPToInt( return DoneMBB; } -MachineBasicBlock * -WebAssemblyTargetLowering::EmitInstrWithCustomInserter( - MachineInstr &MI, - MachineBasicBlock *BB -) const { +MachineBasicBlock *WebAssemblyTargetLowering::EmitInstrWithCustomInserter( + MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); DebugLoc DL = MI.getDebugLoc(); switch (MI.getOpcode()) { - default: llvm_unreachable("Unexpected instr type to insert"); + default: + llvm_unreachable("Unexpected instr type to insert"); case WebAssembly::FP_TO_SINT_I32_F32: return LowerFPToInt(MI, DL, BB, TII, false, false, false, WebAssembly::I32_TRUNC_S_F32); @@ -367,17 +346,17 @@ WebAssemblyTargetLowering::EmitInstrWithCustomInserter( case WebAssembly::FP_TO_UINT_I64_F64: return LowerFPToInt(MI, DL, BB, TII, true, true, true, WebAssembly::I64_TRUNC_U_F64); - llvm_unreachable("Unexpected instruction to emit with custom inserter"); + llvm_unreachable("Unexpected instruction to emit with custom inserter"); } } -const char *WebAssemblyTargetLowering::getTargetNodeName( - unsigned Opcode) const { +const char * +WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) { - case WebAssemblyISD::FIRST_NUMBER: - break; -#define HANDLE_NODETYPE(NODE) \ - case WebAssemblyISD::NODE: \ + case WebAssemblyISD::FIRST_NUMBER: + break; +#define HANDLE_NODETYPE(NODE) \ + case WebAssemblyISD::NODE: \ return "WebAssemblyISD::" #NODE; #include "WebAssemblyISD.def" #undef HANDLE_NODETYPE @@ -392,21 +371,21 @@ WebAssemblyTargetLowering::getRegForInlineAsmConstraint( // WebAssembly register class. if (Constraint.size() == 1) { switch (Constraint[0]) { - case 'r': - assert(VT != MVT::iPTR && "Pointer MVT not expected here"); - if (Subtarget->hasSIMD128() && VT.isVector()) { - if (VT.getSizeInBits() == 128) - return std::make_pair(0U, &WebAssembly::V128RegClass); - } - if (VT.isInteger() && !VT.isVector()) { - if (VT.getSizeInBits() <= 32) - return std::make_pair(0U, &WebAssembly::I32RegClass); - if (VT.getSizeInBits() <= 64) - return std::make_pair(0U, &WebAssembly::I64RegClass); - } - break; - default: - break; + case 'r': + assert(VT != MVT::iPTR && "Pointer MVT not expected here"); + if (Subtarget->hasSIMD128() && VT.isVector()) { + if (VT.getSizeInBits() == 128) + return std::make_pair(0U, &WebAssembly::V128RegClass); + } + if (VT.isInteger() && !VT.isVector()) { + if (VT.getSizeInBits() <= 32) + return std::make_pair(0U, &WebAssembly::I32RegClass); + if (VT.getSizeInBits() <= 64) + return std::make_pair(0U, &WebAssembly::I64RegClass); + } + break; + default: + break; } } @@ -425,16 +404,17 @@ bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const { bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, - Type *Ty, - unsigned AS, + Type *Ty, unsigned AS, Instruction *I) const { // WebAssembly offsets are added as unsigned without wrapping. The // isLegalAddressingMode gives us no way to determine if wrapping could be // happening, so we approximate this by accepting only non-negative offsets. - if (AM.BaseOffs < 0) return false; + if (AM.BaseOffs < 0) + return false; // WebAssembly has no scale register operands. - if (AM.Scale != 0) return false; + if (AM.Scale != 0) + return false; // Everything else is legal. return true; @@ -448,7 +428,8 @@ bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses( // for the kinds of things that LLVM uses this for (merging adjacent stores // of constants, etc.), WebAssembly implementations will either want the // unaligned access or they'll split anyway. - if (Fast) *Fast = true; + if (Fast) + *Fast = true; return true; } @@ -535,8 +516,9 @@ static bool CallingConvSupported(CallingConv::ID CallConv) { CallConv == CallingConv::CXX_FAST_TLS; } -SDValue WebAssemblyTargetLowering::LowerCall( - CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const { +SDValue +WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI, + SmallVectorImpl<SDValue> &InVals) const { SelectionDAG &DAG = CLI.DAG; SDLoc DL = CLI.DL; SDValue Chain = CLI.Chain; @@ -638,9 +620,9 @@ SDValue WebAssemblyTargetLowering::LowerCall( FINode = DAG.getFrameIndex(FI, getPointerTy(Layout)); SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode, DAG.getConstant(Offset, DL, PtrVT)); - Chains.push_back(DAG.getStore( - Chain, DL, Arg, Add, - MachinePointerInfo::getFixedStack(MF, FI, Offset), 0)); + Chains.push_back( + DAG.getStore(Chain, DL, Arg, Add, + MachinePointerInfo::getFixedStack(MF, FI, Offset), 0)); } if (!Chains.empty()) Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); @@ -658,7 +640,8 @@ SDValue WebAssemblyTargetLowering::LowerCall( Ops.append(OutVals.begin(), IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end()); // Add a pointer to the vararg buffer. - if (IsVarArg) Ops.push_back(FINode); + if (IsVarArg) + Ops.push_back(FINode); SmallVector<EVT, 8> InTys; for (const auto &In : Ins) { @@ -752,11 +735,10 @@ SDValue WebAssemblyTargetLowering::LowerFormalArguments( fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments"); // Ignore In.getOrigAlign() because all our arguments are passed in // registers. - InVals.push_back( - In.Used - ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT, - DAG.getTargetConstant(InVals.size(), DL, MVT::i32)) - : DAG.getUNDEF(In.VT)); + InVals.push_back(In.Used ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT, + DAG.getTargetConstant(InVals.size(), + DL, MVT::i32)) + : DAG.getUNDEF(In.VT)); // Record the number and types of arguments. MFI->addParam(In.VT); @@ -794,34 +776,34 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); switch (Op.getOpcode()) { - default: - llvm_unreachable("unimplemented operation lowering"); - return SDValue(); - case ISD::FrameIndex: - return LowerFrameIndex(Op, DAG); - case ISD::GlobalAddress: - return LowerGlobalAddress(Op, DAG); - case ISD::ExternalSymbol: - return LowerExternalSymbol(Op, DAG); - case ISD::JumpTable: - return LowerJumpTable(Op, DAG); - case ISD::BR_JT: - return LowerBR_JT(Op, DAG); - case ISD::VASTART: - return LowerVASTART(Op, DAG); - case ISD::BlockAddress: - case ISD::BRIND: - fail(DL, DAG, "WebAssembly hasn't implemented computed gotos"); - return SDValue(); - case ISD::RETURNADDR: // Probably nothing meaningful can be returned here. - fail(DL, DAG, "WebAssembly hasn't implemented __builtin_return_address"); - return SDValue(); - case ISD::FRAMEADDR: - return LowerFRAMEADDR(Op, DAG); - case ISD::CopyToReg: - return LowerCopyToReg(Op, DAG); - case ISD::INTRINSIC_WO_CHAIN: - return LowerINTRINSIC_WO_CHAIN(Op, DAG); + default: + llvm_unreachable("unimplemented operation lowering"); + return SDValue(); + case ISD::FrameIndex: + return LowerFrameIndex(Op, DAG); + case ISD::GlobalAddress: + return LowerGlobalAddress(Op, DAG); + case ISD::ExternalSymbol: + return LowerExternalSymbol(Op, DAG); + case ISD::JumpTable: + return LowerJumpTable(Op, DAG); + case ISD::BR_JT: + return LowerBR_JT(Op, DAG); + case ISD::VASTART: + return LowerVASTART(Op, DAG); + case ISD::BlockAddress: + case ISD::BRIND: + fail(DL, DAG, "WebAssembly hasn't implemented computed gotos"); + return SDValue(); + case ISD::RETURNADDR: // Probably nothing meaningful can be returned here. + fail(DL, DAG, "WebAssembly hasn't implemented __builtin_return_address"); + return SDValue(); + case ISD::FRAMEADDR: + return LowerFRAMEADDR(Op, DAG); + case ISD::CopyToReg: + return LowerCopyToReg(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: + return LowerINTRINSIC_WO_CHAIN(Op, DAG); } } @@ -838,16 +820,15 @@ SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op, SDLoc DL(Op); unsigned Reg = cast<RegisterSDNode>(Op.getOperand(1))->getReg(); EVT VT = Src.getValueType(); - SDValue Copy( - DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_I32 - : WebAssembly::COPY_I64, - DL, VT, Src), - 0); + SDValue Copy(DAG.getMachineNode(VT == MVT::i32 ? WebAssembly::COPY_I32 + : WebAssembly::COPY_I64, + DL, VT, Src), + 0); return Op.getNode()->getNumValues() == 1 ? DAG.getCopyToReg(Chain, DL, Reg, Copy) - : DAG.getCopyToReg(Chain, DL, Reg, Copy, Op.getNumOperands() == 4 - ? Op.getOperand(3) - : SDValue()); + : DAG.getCopyToReg(Chain, DL, Reg, Copy, + Op.getNumOperands() == 4 ? Op.getOperand(3) + : SDValue()); } return SDValue(); } @@ -887,8 +868,9 @@ SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op, DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset())); } -SDValue WebAssemblyTargetLowering::LowerExternalSymbol( - SDValue Op, SelectionDAG &DAG) const { +SDValue +WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op, + SelectionDAG &DAG) const { SDLoc DL(Op); const auto *ES = cast<ExternalSymbolSDNode>(Op); EVT VT = Op.getValueType(); @@ -899,9 +881,10 @@ SDValue WebAssemblyTargetLowering::LowerExternalSymbol( // we don't know anything about the symbol other than its name, because all // external symbols used in target-independent SelectionDAG code are for // functions. - return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT, - DAG.getTargetExternalSymbol(ES->getSymbol(), VT, - WebAssemblyII::MO_SYMBOL_FUNCTION)); + return DAG.getNode( + WebAssemblyISD::Wrapper, DL, VT, + DAG.getTargetExternalSymbol(ES->getSymbol(), VT, + WebAssemblyII::MO_SYMBOL_FUNCTION)); } SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op, @@ -930,7 +913,8 @@ SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op, const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs; // Add an operand for each case. - for (auto MBB : MBBs) Ops.push_back(DAG.getBasicBlock(MBB)); + for (auto MBB : MBBs) + Ops.push_back(DAG.getBasicBlock(MBB)); // TODO: For now, we just pick something arbitrary for a default case for now. // We really want to sniff out the guard and put in the real default case (and diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h index 8b78b0e92a4..7955876716e 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -29,17 +29,17 @@ enum NodeType : unsigned { #undef HANDLE_NODETYPE }; -} // end namespace WebAssemblyISD +} // end namespace WebAssemblyISD class WebAssemblySubtarget; class WebAssemblyTargetMachine; class WebAssemblyTargetLowering final : public TargetLowering { - public: +public: WebAssemblyTargetLowering(const TargetMachine &TM, const WebAssemblySubtarget &STI); - private: +private: /// Keep a pointer to the WebAssemblySubtarget around so that we can make the /// right decision when generating code for different targets. const WebAssemblySubtarget *Subtarget; @@ -53,9 +53,9 @@ class WebAssemblyTargetLowering final : public TargetLowering { EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; const char *getTargetNodeName(unsigned Opcode) const override; - std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint( - const TargetRegisterInfo *TRI, StringRef Constraint, - MVT VT) const override; + std::pair<unsigned, const TargetRegisterClass *> + getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + StringRef Constraint, MVT VT) const override; bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCtlz() const override; bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, @@ -103,8 +103,8 @@ class WebAssemblyTargetLowering final : public TargetLowering { namespace WebAssembly { FastISel *createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo); -} // end namespace WebAssembly +} // end namespace WebAssembly -} // end namespace llvm +} // end namespace llvm #endif diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index cd49bd1682a..a1e0516a53b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -77,10 +77,8 @@ void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, KillSrc ? RegState::Kill : 0); } -MachineInstr * -WebAssemblyInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, - unsigned OpIdx1, - unsigned OpIdx2) const { +MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl( + MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const { // If the operands are stackified, we can't reorder them. WebAssemblyFunctionInfo &MFI = *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>(); @@ -165,12 +163,9 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, return Count; } -unsigned WebAssemblyInstrInfo::insertBranch(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - ArrayRef<MachineOperand> Cond, - const DebugLoc &DL, - int *BytesAdded) const { +unsigned WebAssemblyInstrInfo::insertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { assert(!BytesAdded && "code size not handled"); if (Cond.empty()) { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp index 5fb97e38939..c9a3527d3fb 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp @@ -78,30 +78,102 @@ bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) { MachineInstr *Def = MRI.getVRegDef(Cond); switch (Def->getOpcode()) { using namespace WebAssembly; - case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break; - case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break; - case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break; - case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break; - case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break; - case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break; - case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break; - case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break; - case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break; - case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted = true; break; - case EQ_I64: Def->setDesc(TII.get(NE_I64)); Inverted = true; break; - case NE_I64: Def->setDesc(TII.get(EQ_I64)); Inverted = true; break; - case GT_S_I64: Def->setDesc(TII.get(LE_S_I64)); Inverted = true; break; - case GE_S_I64: Def->setDesc(TII.get(LT_S_I64)); Inverted = true; break; - case LT_S_I64: Def->setDesc(TII.get(GE_S_I64)); Inverted = true; break; - case LE_S_I64: Def->setDesc(TII.get(GT_S_I64)); Inverted = true; break; - case GT_U_I64: Def->setDesc(TII.get(LE_U_I64)); Inverted = true; break; - case GE_U_I64: Def->setDesc(TII.get(LT_U_I64)); Inverted = true; break; - case LT_U_I64: Def->setDesc(TII.get(GE_U_I64)); Inverted = true; break; - case LE_U_I64: Def->setDesc(TII.get(GT_U_I64)); Inverted = true; break; - case EQ_F32: Def->setDesc(TII.get(NE_F32)); Inverted = true; break; - case NE_F32: Def->setDesc(TII.get(EQ_F32)); Inverted = true; break; - case EQ_F64: Def->setDesc(TII.get(NE_F64)); Inverted = true; break; - case NE_F64: Def->setDesc(TII.get(EQ_F64)); Inverted = true; break; + case EQ_I32: + Def->setDesc(TII.get(NE_I32)); + Inverted = true; + break; + case NE_I32: + Def->setDesc(TII.get(EQ_I32)); + Inverted = true; + break; + case GT_S_I32: + Def->setDesc(TII.get(LE_S_I32)); + Inverted = true; + break; + case GE_S_I32: + Def->setDesc(TII.get(LT_S_I32)); + Inverted = true; + break; + case LT_S_I32: + Def->setDesc(TII.get(GE_S_I32)); + Inverted = true; + break; + case LE_S_I32: + Def->setDesc(TII.get(GT_S_I32)); + Inverted = true; + break; + case GT_U_I32: + Def->setDesc(TII.get(LE_U_I32)); + Inverted = true; + break; + case GE_U_I32: + Def->setDesc(TII.get(LT_U_I32)); + Inverted = true; + break; + case LT_U_I32: + Def->setDesc(TII.get(GE_U_I32)); + Inverted = true; + break; + case LE_U_I32: + Def->setDesc(TII.get(GT_U_I32)); + Inverted = true; + break; + case EQ_I64: + Def->setDesc(TII.get(NE_I64)); + Inverted = true; + break; + case NE_I64: + Def->setDesc(TII.get(EQ_I64)); + Inverted = true; + break; + case GT_S_I64: + Def->setDesc(TII.get(LE_S_I64)); + Inverted = true; + break; + case GE_S_I64: + Def->setDesc(TII.get(LT_S_I64)); + Inverted = true; + break; + case LT_S_I64: + Def->setDesc(TII.get(GE_S_I64)); + Inverted = true; + break; + case LE_S_I64: + Def->setDesc(TII.get(GT_S_I64)); + Inverted = true; + break; + case GT_U_I64: + Def->setDesc(TII.get(LE_U_I64)); + Inverted = true; + break; + case GE_U_I64: + Def->setDesc(TII.get(LT_U_I64)); + Inverted = true; + break; + case LT_U_I64: + Def->setDesc(TII.get(GE_U_I64)); + Inverted = true; + break; + case LE_U_I64: + Def->setDesc(TII.get(GT_U_I64)); + Inverted = true; + break; + case EQ_F32: + Def->setDesc(TII.get(NE_F32)); + Inverted = true; + break; + case NE_F32: + Def->setDesc(TII.get(EQ_F32)); + Inverted = true; + break; + case EQ_F64: + Def->setDesc(TII.get(NE_F64)); + Inverted = true; + break; + case NE_F64: + Def->setDesc(TII.get(EQ_F64)); + Inverted = true; + break; case EQZ_I32: { // Invert an eqz by replacing it with its operand. Cond = Def->getOperand(1).getReg(); @@ -109,7 +181,8 @@ bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) { Inverted = true; break; } - default: break; + default: + break; } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp index ee708d637b2..3988189ba7c 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerGlobalDtors.cpp @@ -18,15 +18,15 @@ //===----------------------------------------------------------------------===// #include "WebAssembly.h" +#include "llvm/ADT/MapVector.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/Module.h" -#include "llvm/Transforms/Utils/ModuleUtils.h" #include "llvm/Pass.h" -#include "llvm/ADT/MapVector.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Transforms/Utils/ModuleUtils.h" using namespace llvm; #define DEBUG_TYPE "wasm-lower-global-dtors" @@ -77,18 +77,20 @@ bool LowerGlobalDtors::runOnModule(Module &M) { // Collect the contents of @llvm.global_dtors, collated by priority and // associated symbol. - std::map<uint16_t, MapVector<Constant *, std::vector<Constant *> > > DtorFuncs; + std::map<uint16_t, MapVector<Constant *, std::vector<Constant *>>> DtorFuncs; for (Value *O : InitList->operands()) { ConstantStruct *CS = dyn_cast<ConstantStruct>(O); - if (!CS) continue; // Malformed. + if (!CS) + continue; // Malformed. ConstantInt *Priority = dyn_cast<ConstantInt>(CS->getOperand(0)); - if (!Priority) continue; // Malformed. + if (!Priority) + continue; // Malformed. uint16_t PriorityValue = Priority->getLimitedValue(UINT16_MAX); Constant *DtorFunc = CS->getOperand(1); if (DtorFunc->isNullValue()) - break; // Found a null terminator, skip the rest. + break; // Found a null terminator, skip the rest. Constant *Associated = CS->getOperand(2); Associated = cast<Constant>(Associated->stripPointerCastsNoFollowAliases()); @@ -101,31 +103,23 @@ bool LowerGlobalDtors::runOnModule(Module &M) { // extern "C" int __cxa_atexit(void (*f)(void *), void *p, void *d); LLVMContext &C = M.getContext(); PointerType *VoidStar = Type::getInt8PtrTy(C); - Type *AtExitFuncArgs[] = { VoidStar }; - FunctionType *AtExitFuncTy = FunctionType::get( - Type::getVoidTy(C), - AtExitFuncArgs, - /*isVarArg=*/false); - - Type *AtExitArgs[] = { - PointerType::get(AtExitFuncTy, 0), - VoidStar, - VoidStar - }; - FunctionType *AtExitTy = FunctionType::get( - Type::getInt32Ty(C), - AtExitArgs, - /*isVarArg=*/false); + Type *AtExitFuncArgs[] = {VoidStar}; + FunctionType *AtExitFuncTy = + FunctionType::get(Type::getVoidTy(C), AtExitFuncArgs, + /*isVarArg=*/false); + + Type *AtExitArgs[] = {PointerType::get(AtExitFuncTy, 0), VoidStar, VoidStar}; + FunctionType *AtExitTy = FunctionType::get(Type::getInt32Ty(C), AtExitArgs, + /*isVarArg=*/false); Constant *AtExit = M.getOrInsertFunction("__cxa_atexit", AtExitTy); // Declare __dso_local. Constant *DsoHandle = M.getNamedValue("__dso_handle"); if (!DsoHandle) { Type *DsoHandleTy = Type::getInt8Ty(C); - GlobalVariable *Handle = - new GlobalVariable(M, DsoHandleTy, /*isConstant=*/true, - GlobalVariable::ExternalWeakLinkage, - nullptr, "__dso_handle"); + GlobalVariable *Handle = new GlobalVariable( + M, DsoHandleTy, /*isConstant=*/true, + GlobalVariable::ExternalWeakLinkage, nullptr, "__dso_handle"); Handle->setVisibility(GlobalVariable::HiddenVisibility); DsoHandle = Handle; } @@ -139,13 +133,13 @@ bool LowerGlobalDtors::runOnModule(Module &M) { Constant *Associated = AssociatedAndMore.first; Function *CallDtors = Function::Create( - AtExitFuncTy, Function::PrivateLinkage, - "call_dtors" + - (Priority != UINT16_MAX ? - (Twine(".") + Twine(Priority)) : Twine()) + - (!Associated->isNullValue() ? - (Twine(".") + Associated->getName()) : Twine()), - &M); + AtExitFuncTy, Function::PrivateLinkage, + "call_dtors" + + (Priority != UINT16_MAX ? (Twine(".") + Twine(Priority)) + : Twine()) + + (!Associated->isNullValue() ? (Twine(".") + Associated->getName()) + : Twine()), + &M); BasicBlock *BB = BasicBlock::Create(C, "body", CallDtors); for (auto Dtor : AssociatedAndMore.second) @@ -155,29 +149,29 @@ bool LowerGlobalDtors::runOnModule(Module &M) { FunctionType *VoidVoid = FunctionType::get(Type::getVoidTy(C), /*isVarArg=*/false); Function *RegisterCallDtors = Function::Create( - VoidVoid, Function::PrivateLinkage, - "register_call_dtors" + - (Priority != UINT16_MAX ? - (Twine(".") + Twine(Priority)) : Twine()) + - (!Associated->isNullValue() ? - (Twine(".") + Associated->getName()) : Twine()), - &M); + VoidVoid, Function::PrivateLinkage, + "register_call_dtors" + + (Priority != UINT16_MAX ? (Twine(".") + Twine(Priority)) + : Twine()) + + (!Associated->isNullValue() ? (Twine(".") + Associated->getName()) + : Twine()), + &M); BasicBlock *EntryBB = BasicBlock::Create(C, "entry", RegisterCallDtors); BasicBlock *FailBB = BasicBlock::Create(C, "fail", RegisterCallDtors); BasicBlock *RetBB = BasicBlock::Create(C, "return", RegisterCallDtors); Value *Null = ConstantPointerNull::get(VoidStar); - Value *Args[] = { CallDtors, Null, DsoHandle }; + Value *Args[] = {CallDtors, Null, DsoHandle}; Value *Res = CallInst::Create(AtExit, Args, "call", EntryBB); Value *Cmp = new ICmpInst(*EntryBB, ICmpInst::ICMP_NE, Res, Constant::getNullValue(Res->getType())); BranchInst::Create(FailBB, RetBB, Cmp, EntryBB); // If `__cxa_atexit` hits out-of-memory, trap, so that we don't misbehave. - // This should be very rare, because if the process is running out of memory - // before main has even started, something is wrong. - CallInst::Create(Intrinsic::getDeclaration(&M, Intrinsic::trap), - "", FailBB); + // This should be very rare, because if the process is running out of + // memory before main has even started, something is wrong. + CallInst::Create(Intrinsic::getDeclaration(&M, Intrinsic::trap), "", + FailBB); new UnreachableInst(C, FailBB); ReturnInst::Create(C, RetBB); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp index 2ac32d5a356..db4fb5c75b5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp @@ -32,11 +32,11 @@ using namespace llvm; // This disables the removal of registers when lowering into MC, as required // by some current tests. -static cl::opt<bool> WasmKeepRegisters( - "wasm-keep-registers", cl::Hidden, - cl::desc("WebAssembly: output stack registers in" - " instruction output for test purposes only."), - cl::init(false)); +static cl::opt<bool> + WasmKeepRegisters("wasm-keep-registers", cl::Hidden, + cl::desc("WebAssembly: output stack registers in" + " instruction output for test purposes only."), + cl::init(false)); static unsigned regInstructionToStackInstruction(unsigned OpCode); static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI); @@ -54,10 +54,9 @@ WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const { SmallVector<wasm::ValType, 4> Returns; SmallVector<wasm::ValType, 4> Params; - wasm::ValType iPTR = - MF.getSubtarget<WebAssemblySubtarget>().hasAddr64() ? - wasm::ValType::I64 : - wasm::ValType::I32; + wasm::ValType iPTR = MF.getSubtarget<WebAssemblySubtarget>().hasAddr64() + ? wasm::ValType::I64 + : wasm::ValType::I32; SmallVector<MVT, 4> ResultMVTs; ComputeLegalValueVTs(CurrentFunc, TM, FuncTy->getReturnType(), ResultMVTs); @@ -122,9 +121,9 @@ MCOperand WebAssemblyMCInstLower::LowerSymbolOperand(MCSymbol *Sym, bool IsFunc, bool IsGlob) const { MCSymbolRefExpr::VariantKind VK = - IsFunc ? MCSymbolRefExpr::VK_WebAssembly_FUNCTION : - IsGlob ? MCSymbolRefExpr::VK_WebAssembly_GLOBAL - : MCSymbolRefExpr::VK_None; + IsFunc ? MCSymbolRefExpr::VK_WebAssembly_FUNCTION + : IsGlob ? MCSymbolRefExpr::VK_WebAssembly_GLOBAL + : MCSymbolRefExpr::VK_None; const MCExpr *Expr = MCSymbolRefExpr::create(Sym, VK, Ctx); @@ -238,7 +237,8 @@ void WebAssemblyMCInstLower::Lower(const MachineInstr *MI, // variable or a function. assert((MO.getTargetFlags() & ~WebAssemblyII::MO_SYMBOL_MASK) == 0 && "WebAssembly uses only symbol flags on ExternalSymbols"); - MCOp = LowerSymbolOperand(GetExternalSymbolSymbol(MO), /*Offset=*/0, + MCOp = LowerSymbolOperand( + GetExternalSymbolSymbol(MO), /*Offset=*/0, (MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_FUNCTION) != 0, (MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_GLOBAL) != 0); break; @@ -295,7 +295,7 @@ static unsigned regInstructionToStackInstruction(unsigned OpCode) { switch (OpCode) { default: llvm_unreachable( - "unknown WebAssembly instruction in WebAssemblyMCInstLower pass"); + "unknown WebAssembly instruction in WebAssemblyMCInstLower pass"); #include "WebAssemblyGenStackifier.inc" } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h index 3a9d52b1c8c..54a55796415 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h @@ -33,8 +33,8 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyMCInstLower { MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const; MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; - MCOperand LowerSymbolOperand(MCSymbol *Sym, int64_t Offset, - bool IsFunc, bool IsGlob) const; + MCOperand LowerSymbolOperand(MCSymbol *Sym, int64_t Offset, bool IsFunc, + bool IsGlob) const; public: WebAssemblyMCInstLower(MCContext &ctx, WebAssemblyAsmPrinter &printer) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h index a60b10fc530..5a2602f87ee 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h @@ -50,7 +50,7 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo { // overaligned values on the user stack. unsigned BasePtrVreg = -1U; - public: +public: explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {} ~WebAssemblyFunctionInfo() override; @@ -60,7 +60,10 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo { void addResult(MVT VT) { Results.push_back(VT); } const std::vector<MVT> &getResults() const { return Results; } - void clearParamsAndResults() { Params.clear(); Results.clear(); } + void clearParamsAndResults() { + Params.clear(); + Results.clear(); + } void setNumLocals(size_t NumLocals) { Locals.resize(NumLocals, MVT::i32); } void setLocal(size_t i, MVT VT) { Locals[i] = VT; } @@ -115,8 +118,8 @@ class WebAssemblyFunctionInfo final : public MachineFunctionInfo { } }; -void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM, - Type *Ty, SmallVectorImpl<MVT> &ValueVTs); +void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM, Type *Ty, + SmallVectorImpl<MVT> &ValueVTs); void ComputeSignatureVTs(const Function &F, const TargetMachine &TM, SmallVectorImpl<MVT> &Params, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp index 04ac22a589e..3d0a15244ee 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp @@ -65,7 +65,8 @@ FunctionPass *llvm::createWebAssemblyOptimizeLiveIntervals() { return new WebAssemblyOptimizeLiveIntervals(); } -bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(MachineFunction &MF) { +bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction( + MachineFunction &MF) { LLVM_DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n" "********** Function: " << MF.getName() << '\n'); @@ -76,11 +77,10 @@ bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(MachineFunction &MF) // We don't preserve SSA form. MRI.leaveSSA(); - assert(MRI.tracksLiveness() && - "OptimizeLiveIntervals expects liveness"); + assert(MRI.tracksLiveness() && "OptimizeLiveIntervals expects liveness"); // Split multiple-VN LiveIntervals into multiple LiveIntervals. - SmallVector<LiveInterval*, 4> SplitLIs; + SmallVector<LiveInterval *, 4> SplitLIs; for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (MRI.reg_nodbg_empty(Reg)) @@ -94,7 +94,7 @@ bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(MachineFunction &MF) // instructions to satisfy LiveIntervals' requirement that all uses be // dominated by defs. Now that LiveIntervals has computed which of these // defs are actually needed and which are dead, remove the dead ones. - for (auto MII = MF.begin()->begin(), MIE = MF.begin()->end(); MII != MIE; ) { + for (auto MII = MF.begin()->begin(), MIE = MF.begin()->end(); MII != MIE;) { MachineInstr *MI = &*MII++; if (MI->isImplicitDef() && MI->getOperand(0).isDead()) { LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg()); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp index e44e7057e23..0be0ba65783 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp @@ -70,7 +70,8 @@ static bool HasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) { return false; } -bool WebAssemblyPrepareForLiveIntervals::runOnMachineFunction(MachineFunction &MF) { +bool WebAssemblyPrepareForLiveIntervals::runOnMachineFunction( + MachineFunction &MF) { LLVM_DEBUG({ dbgs() << "********** Prepare For LiveIntervals **********\n" << "********** Function: " << MF.getName() << '\n'; @@ -112,7 +113,7 @@ bool WebAssemblyPrepareForLiveIntervals::runOnMachineFunction(MachineFunction &M // Move ARGUMENT_* instructions to the top of the entry block, so that their // liveness reflects the fact that these really are live-in values. - for (auto MII = Entry.begin(), MIE = Entry.end(); MII != MIE; ) { + for (auto MII = Entry.begin(), MIE = Entry.end(); MII != MIE;) { MachineInstr &MI = *MII++; if (WebAssembly::isArgument(MI)) { MI.removeFromParent(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 254cd041b11..e6d02a5a0e8 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -100,8 +100,7 @@ static void ConvertImplicitDefToConstZero(MachineInstr *MI, MachineFunction &MF) { assert(MI->getOpcode() == TargetOpcode::IMPLICIT_DEF); - const auto *RegClass = - MRI.getRegClass(MI->getOperand(0).getReg()); + const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); if (RegClass == &WebAssembly::I32RegClass) { MI->setDesc(TII->get(WebAssembly::CONST_I32)); MI->addOperand(MachineOperand::CreateImm(0)); @@ -187,14 +186,22 @@ static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read, } } else if (MI.hasOrderedMemoryRef()) { switch (MI.getOpcode()) { - case WebAssembly::DIV_S_I32: case WebAssembly::DIV_S_I64: - case WebAssembly::REM_S_I32: case WebAssembly::REM_S_I64: - case WebAssembly::DIV_U_I32: case WebAssembly::DIV_U_I64: - case WebAssembly::REM_U_I32: case WebAssembly::REM_U_I64: - case WebAssembly::I32_TRUNC_S_F32: case WebAssembly::I64_TRUNC_S_F32: - case WebAssembly::I32_TRUNC_S_F64: case WebAssembly::I64_TRUNC_S_F64: - case WebAssembly::I32_TRUNC_U_F32: case WebAssembly::I64_TRUNC_U_F32: - case WebAssembly::I32_TRUNC_U_F64: case WebAssembly::I64_TRUNC_U_F64: + case WebAssembly::DIV_S_I32: + case WebAssembly::DIV_S_I64: + case WebAssembly::REM_S_I32: + case WebAssembly::REM_S_I64: + case WebAssembly::DIV_U_I32: + case WebAssembly::DIV_U_I64: + case WebAssembly::REM_U_I32: + case WebAssembly::REM_U_I64: + case WebAssembly::I32_TRUNC_S_F32: + case WebAssembly::I64_TRUNC_S_F32: + case WebAssembly::I32_TRUNC_S_F64: + case WebAssembly::I64_TRUNC_S_F64: + case WebAssembly::I32_TRUNC_U_F32: + case WebAssembly::I64_TRUNC_U_F32: + case WebAssembly::I32_TRUNC_U_F64: + case WebAssembly::I64_TRUNC_U_F64: // These instruction have hasUnmodeledSideEffects() returning true // because they trap on overflow and invalid so they can't be arbitrarily // moved, however hasOrderedMemoryRef() interprets this plus their lack @@ -214,14 +221,22 @@ static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read, // Check for side effects. if (MI.hasUnmodeledSideEffects()) { switch (MI.getOpcode()) { - case WebAssembly::DIV_S_I32: case WebAssembly::DIV_S_I64: - case WebAssembly::REM_S_I32: case WebAssembly::REM_S_I64: - case WebAssembly::DIV_U_I32: case WebAssembly::DIV_U_I64: - case WebAssembly::REM_U_I32: case WebAssembly::REM_U_I64: - case WebAssembly::I32_TRUNC_S_F32: case WebAssembly::I64_TRUNC_S_F32: - case WebAssembly::I32_TRUNC_S_F64: case WebAssembly::I64_TRUNC_S_F64: - case WebAssembly::I32_TRUNC_U_F32: case WebAssembly::I64_TRUNC_U_F32: - case WebAssembly::I32_TRUNC_U_F64: case WebAssembly::I64_TRUNC_U_F64: + case WebAssembly::DIV_S_I32: + case WebAssembly::DIV_S_I64: + case WebAssembly::REM_S_I32: + case WebAssembly::REM_S_I64: + case WebAssembly::DIV_U_I32: + case WebAssembly::DIV_U_I64: + case WebAssembly::REM_U_I32: + case WebAssembly::REM_U_I64: + case WebAssembly::I32_TRUNC_S_F32: + case WebAssembly::I64_TRUNC_S_F32: + case WebAssembly::I32_TRUNC_S_F64: + case WebAssembly::I64_TRUNC_S_F64: + case WebAssembly::I32_TRUNC_U_F32: + case WebAssembly::I64_TRUNC_U_F32: + case WebAssembly::I32_TRUNC_U_F64: + case WebAssembly::I64_TRUNC_U_F64: // These instructions have hasUnmodeledSideEffects() returning true // because they trap on overflow and invalid so they can't be arbitrarily // moved, however in the specific case of register stackifying, it is safe @@ -251,8 +266,7 @@ static bool ShouldRematerialize(const MachineInstr &Def, AliasAnalysis &AA, // LiveIntervals to handle complex cases. static MachineInstr *GetVRegDef(unsigned Reg, const MachineInstr *Insert, const MachineRegisterInfo &MRI, - const LiveIntervals &LIS) -{ + const LiveIntervals &LIS) { // Most registers are in SSA form here so we try a quick MRI query first. if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) return Def; @@ -268,17 +282,16 @@ static MachineInstr *GetVRegDef(unsigned Reg, const MachineInstr *Insert, // Test whether Reg, as defined at Def, has exactly one use. This is a // generalization of MachineRegisterInfo::hasOneUse that uses LiveIntervals // to handle complex cases. -static bool HasOneUse(unsigned Reg, MachineInstr *Def, - MachineRegisterInfo &MRI, MachineDominatorTree &MDT, - LiveIntervals &LIS) { +static bool HasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, + MachineDominatorTree &MDT, LiveIntervals &LIS) { // Most registers are in SSA form here so we try a quick MRI query first. if (MRI.hasOneUse(Reg)) return true; bool HasOne = false; const LiveInterval &LI = LIS.getInterval(Reg); - const VNInfo *DefVNI = LI.getVNInfoAt( - LIS.getInstructionIndex(*Def).getRegSlot()); + const VNInfo *DefVNI = + LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot()); assert(DefVNI); for (auto &I : MRI.use_nodbg_operands(Reg)) { const auto &Result = LI.Query(LIS.getInstructionIndex(*I.getParent())); @@ -447,16 +460,15 @@ static unsigned GetTeeOpcode(const TargetRegisterClass *RC) { // Shrink LI to its uses, cleaning up LI. static void ShrinkToUses(LiveInterval &LI, LiveIntervals &LIS) { if (LIS.shrinkToUses(&LI)) { - SmallVector<LiveInterval*, 4> SplitLIs; + SmallVector<LiveInterval *, 4> SplitLIs; LIS.splitSeparateComponents(LI, SplitLIs); } } /// A single-use def in the same block with no intervening memory or register /// dependencies; move the def down and nest it with the current instruction. -static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op, - MachineInstr *Def, - MachineBasicBlock &MBB, +static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand &Op, + MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI) { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp index b6481ac2d4a..1f0870865b0 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp @@ -22,9 +22,9 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/IR/Function.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp index f432b367d15..e5a3e47a3bc 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp @@ -54,8 +54,8 @@ private: char WebAssemblyReplacePhysRegs::ID = 0; INITIALIZE_PASS(WebAssemblyReplacePhysRegs, DEBUG_TYPE, - "Replace physical registers with virtual registers", - false, false) + "Replace physical registers with virtual registers", false, + false) FunctionPass *llvm::createWebAssemblyReplacePhysRegs() { return new WebAssemblyReplacePhysRegs(); @@ -86,7 +86,7 @@ bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) { // Replace explicit uses of the physical register with a virtual register. const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); unsigned VReg = WebAssembly::NoRegister; - for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E; ) { + for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E;) { MachineOperand &MO = *I++; if (!MO.isImplicit()) { if (VReg == WebAssembly::NoRegister) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp index fe8a5e4c06f..5d31fb241ce 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp @@ -88,7 +88,6 @@ enum RuntimeLibcallSignature { unsupported }; - struct RuntimeLibcallSignatureTable { std::vector<RuntimeLibcallSignature> Table; @@ -486,8 +485,6 @@ struct StaticLibcallNameMap { } // end anonymous namespace - - void llvm::GetSignature(const WebAssemblySubtarget &Subtarget, RTLIB::Libcall LC, SmallVectorImpl<wasm::ValType> &Rets, SmallVectorImpl<wasm::ValType> &Params) { @@ -497,7 +494,7 @@ void llvm::GetSignature(const WebAssemblySubtarget &Subtarget, wasm::ValType iPTR = Subtarget.hasAddr64() ? wasm::ValType::I64 : wasm::ValType::I32; - auto& Table = RuntimeLibcallSignatures->Table; + auto &Table = RuntimeLibcallSignatures->Table; switch (Table[LC]) { case func: break; @@ -837,7 +834,7 @@ static ManagedStatic<StaticLibcallNameMap> LibcallNameMap; void llvm::GetSignature(const WebAssemblySubtarget &Subtarget, const char *Name, SmallVectorImpl<wasm::ValType> &Rets, SmallVectorImpl<wasm::ValType> &Params) { - auto& Map = LibcallNameMap->Map; + auto &Map = LibcallNameMap->Map; auto val = Map.find(Name); assert(val != Map.end() && "unexpected runtime library name"); return GetSignature(Subtarget, val->second, Rets, Params); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp index d8fe1a4630e..aaa0bbcbc57 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp @@ -60,8 +60,7 @@ static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) { assert(MI.hasOneMemOperand() && "Load and store instructions have exactly one mem operand"); assert((*MI.memoperands_begin())->getSize() == - (UINT64_C(1) - << WebAssembly::GetDefaultP2Align(MI.getOpcode())) && + (UINT64_C(1) << WebAssembly::GetDefaultP2Align(MI.getOpcode())) && "Default p2align value should be natural"); assert(MI.getDesc().OpInfo[OperandNo].OperandType == WebAssembly::OPERAND_P2ALIGN && @@ -69,8 +68,8 @@ static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) { uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment()); // WebAssembly does not currently support supernatural alignment. - P2Align = std::min( - P2Align, uint64_t(WebAssembly::GetDefaultP2Align(MI.getOpcode()))); + P2Align = std::min(P2Align, + uint64_t(WebAssembly::GetDefaultP2Align(MI.getOpcode()))); MI.getOperand(OperandNo).setImm(P2Align); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp index 893e8484c4c..de104d42be4 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp @@ -91,7 +91,8 @@ static bool ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI, SmallVector<SlotIndex, 4> Indices; - for (auto I = MRI.use_nodbg_begin(FromReg), E = MRI.use_nodbg_end(); I != E;) { + for (auto I = MRI.use_nodbg_begin(FromReg), E = MRI.use_nodbg_end(); + I != E;) { MachineOperand &O = *I++; MachineInstr *Where = O.getParent(); @@ -132,9 +133,9 @@ static bool ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI, // If we replaced all dominated uses, FromReg is now killed at MI. if (!FromLI->liveAt(FromIdx.getDeadSlot())) - MI.addRegisterKilled(FromReg, - MBB.getParent()->getSubtarget<WebAssemblySubtarget>() - .getRegisterInfo()); + MI.addRegisterKilled(FromReg, MBB.getParent() + ->getSubtarget<WebAssemblySubtarget>() + .getRegisterInfo()); } return Changed; @@ -142,8 +143,7 @@ static bool ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI, static bool optimizeCall(MachineBasicBlock &MBB, MachineInstr &MI, const MachineRegisterInfo &MRI, - MachineDominatorTree &MDT, - LiveIntervals &LIS, + MachineDominatorTree &MDT, LiveIntervals &LIS, const WebAssemblyTargetLowering &TLI, const TargetLibraryInfo &LibInfo) { MachineOperand &Op1 = MI.getOperand(1); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 1cc688599a9..954c8a6b50b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -150,7 +150,7 @@ class StripThreadLocal final : public ModulePass { // pass just converts all GlobalVariables to NotThreadLocal static char ID; - public: +public: StripThreadLocal() : ModulePass(ID) {} bool runOnModule(Module &M) override { for (auto &GV : M.globals()) |
