diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrFormats.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 22 |
2 files changed, 12 insertions, 12 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td index ea5e58d07e0..5523ec142ba 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td +++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td @@ -242,7 +242,7 @@ let Uses = [EXEC] in { class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : InstSI <outs, ins, asm, pattern> { - + let VINTRP = 1; // VINTRP instructions read parameter values from LDS, but these parameter // values are stored outside of the LDS memory that is allocated to the // shader for general purpose use. diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 9f728110faa..0d6166ac2af 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -51,10 +51,10 @@ let Uses = [M0, EXEC] in { multiclass V_INTERP_P1_F32_m : VINTRP_m < 0x00000000, (outs VGPR_32:$vdst), - (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), - "v_interp_p1_f32 $vdst, $i, $attr_chan, $attr", - [(set f32:$vdst, (AMDGPUinterp_p1 f32:$i, (i32 imm:$attr_chan), - (i32 imm:$attr)))] + (ins VGPR_32:$vsrc, i32imm:$attrchan, i32imm:$attr), + "v_interp_p1_f32 $vdst, $vsrc, $attrchan, $attr", + [(set f32:$vdst, (AMDGPUinterp_p1 f32:$vsrc, (i32 imm:$attrchan), + (i32 imm:$attr)))] >; let OtherPredicates = [has32BankLDS] in { @@ -74,19 +74,19 @@ let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in { defm V_INTERP_P2_F32 : VINTRP_m < 0x00000001, (outs VGPR_32:$vdst), - (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), - "v_interp_p2_f32 $vdst, $j, $attr_chan, $attr", - [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$j, (i32 imm:$attr_chan), - (i32 imm:$attr)))]>; + (ins VGPR_32:$src0, VGPR_32:$vsrc, i32imm:$attrchan, i32imm:$attr), + "v_interp_p2_f32 $vdst, $vsrc, $attrchan, $attr", + [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$vsrc, (i32 imm:$attrchan), + (i32 imm:$attr)))]>; } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst" defm V_INTERP_MOV_F32 : VINTRP_m < 0x00000002, (outs VGPR_32:$vdst), - (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), - "v_interp_mov_f32 $vdst, $src0, $attr_chan, $attr", - [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan), + (ins InterpSlot:$vsrc, i32imm:$attrchan, i32imm:$attr), + "v_interp_mov_f32 $vdst, $vsrc, $attrchan, $attr", + [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 imm:$attrchan), (i32 imm:$attr)))]>; } // End Uses = [M0, EXEC] |
