diff options
Diffstat (limited to 'llvm/lib/Target')
4 files changed, 7 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 23bffb9bc01..22d99bfb371 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -101,10 +101,7 @@ StringRef Hexagon_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) { return ArchV; } -unsigned HexagonGetLastSlot() { - return HexagonItinerariesV4FU::SLOT3; -} - +unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV4FU::SLOT3; } namespace { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index 82758a92004..6bb69be6142 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -65,10 +65,11 @@ MCAsmBackend *createHexagonAsmBackend(const Target &T, MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU); -} // End llvm namespace unsigned HexagonGetLastSlot(); +} // End llvm namespace + // Define symbolic names for Hexagon registers. This defines a mapping from // register name to register number. // diff --git a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp index accb84a8094..ebd414baf1d 100644 --- a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp +++ b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp @@ -42,6 +42,7 @@ static cl::opt<bool> cl::desc("Enable generating the ISEL instruction."), cl::init(true), cl::Hidden); +namespace { class PPCExpandISEL : public MachineFunctionPass { DebugLoc dl; MachineFunction *MF; @@ -143,6 +144,7 @@ public: return true; } }; +} // end anonymous namespace void PPCExpandISEL::initialize(MachineFunction &MFParam) { MF = &MFParam; diff --git a/llvm/lib/Target/X86/X86InterleavedAccess.cpp b/llvm/lib/Target/X86/X86InterleavedAccess.cpp index d9edf4676fa..806d6cc888f 100644 --- a/llvm/lib/Target/X86/X86InterleavedAccess.cpp +++ b/llvm/lib/Target/X86/X86InterleavedAccess.cpp @@ -19,6 +19,7 @@ using namespace llvm; +namespace { /// \brief This class holds necessary information to represent an interleaved /// access group and supports utilities to lower the group into /// X86-specific instructions/intrinsics. @@ -27,7 +28,6 @@ using namespace llvm; /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr /// %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6> /// %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7> - class X86InterleavedAccessGroup { /// \brief Reference to the wide-load instruction of an interleaved access /// group. @@ -95,6 +95,7 @@ public: /// instructions/intrinsics. bool lowerIntoOptimizedSequence(); }; +} // end anonymous namespace bool X86InterleavedAccessGroup::isSupported() const { VectorType *ShuffleVecTy = Shuffles[0]->getType(); |
