diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 11 |
2 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 1a5aed47b32..5500a434c36 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -985,6 +985,8 @@ static bool hasShortDelaySlot(unsigned Opcode) { switch (Opcode) { case Mips::JALS_MM: case Mips::JALRS_MM: + case Mips::BGEZALS_MM: + case Mips::BLTZALS_MM: return true; default: return false; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index dbbf1602919..41654ac1def 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -115,6 +115,11 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in { class JumpLinkRegMM<string opstr, RegisterOperand RO>: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), [], IIBranch, FrmR>; + + class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd, + RegisterOperand RO> : + InstSE<(outs), (ins RO:$rs, opnd:$offset), + !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; } def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; @@ -298,6 +303,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>, BGEZAL_FM_MM<0x01>; + /// Branch Instructions - Short Delay Slot + def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm, + GPR32Opnd>, BGEZAL_FM_MM<0x13>; + def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, + GPR32Opnd>, BGEZAL_FM_MM<0x11>; + /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; |
