diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index b3eb460d3c3..7de6791f2e4 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -50,8 +50,8 @@ def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; -// Integer division issued on port 0, but uses the non-pipelined divider. -def HWDivider : ProcResource<1> { let Buffered = 0; } +// Integer division issued on port 0. +def HWDivider : ProcResource<1>; // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 // cycles after the memory operand. diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 66d78e4fc42..74d5f1b6eba 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -46,8 +46,8 @@ def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; -// Integer division issued on port 0, but uses the non-pipelined divider. -def SBDivider : ProcResource<1> { let Buffered = 0; } +// Integer division issued on port 0. +def SBDivider : ProcResource<1>; // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 // cycles after the memory operand. |
