diff options
Diffstat (limited to 'llvm/lib/Target')
184 files changed, 2719 insertions, 2642 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp index 7de5d0ef66b..30232afaf02 100644 --- a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp +++ b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp @@ -116,7 +116,7 @@ INITIALIZE_PASS(AArch64A53Fix835769, "aarch64-fix-cortex-a53-835769-pass", bool AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) { - DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n"); + LLVM_DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n"); bool Changed = false; TII = F.getSubtarget().getInstrInfo(); @@ -190,7 +190,8 @@ static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI, bool AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n"); + LLVM_DEBUG(dbgs() << "Running on MBB: " << MBB + << " - scanning instructions...\n"); // First, scan the basic block, looking for a sequence of 2 instructions // that match the conditions under which the erratum may trigger. @@ -206,17 +207,17 @@ AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) { for (auto &MI : MBB) { MachineInstr *CurrInstr = &MI; - DEBUG(dbgs() << " Examining: " << MI); + LLVM_DEBUG(dbgs() << " Examining: " << MI); if (PrevInstr) { - DEBUG(dbgs() << " PrevInstr: " << *PrevInstr - << " CurrInstr: " << *CurrInstr - << " isFirstInstructionInSequence(PrevInstr): " - << isFirstInstructionInSequence(PrevInstr) << "\n" - << " isSecondInstructionInSequence(CurrInstr): " - << isSecondInstructionInSequence(CurrInstr) << "\n"); + LLVM_DEBUG(dbgs() << " PrevInstr: " << *PrevInstr + << " CurrInstr: " << *CurrInstr + << " isFirstInstructionInSequence(PrevInstr): " + << isFirstInstructionInSequence(PrevInstr) << "\n" + << " isSecondInstructionInSequence(CurrInstr): " + << isSecondInstructionInSequence(CurrInstr) << "\n"); if (isFirstInstructionInSequence(PrevInstr) && isSecondInstructionInSequence(CurrInstr)) { - DEBUG(dbgs() << " ** pattern found at Idx " << Idx << "!\n"); + LLVM_DEBUG(dbgs() << " ** pattern found at Idx " << Idx << "!\n"); Sequences.push_back(CurrInstr); } } @@ -225,8 +226,8 @@ AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) { ++Idx; } - DEBUG(dbgs() << "Scan complete, " << Sequences.size() - << " occurrences of pattern found.\n"); + LLVM_DEBUG(dbgs() << "Scan complete, " << Sequences.size() + << " occurrences of pattern found.\n"); // Then update the basic block, inserting nops between the detected sequences. for (auto &MI : Sequences) { diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index 330237fc10b..a95476b9118 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -315,7 +315,7 @@ bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) { return false; bool Changed = false; - DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n"); + LLVM_DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n"); MRI = &F.getRegInfo(); TRI = F.getRegInfo().getTargetRegisterInfo(); @@ -330,7 +330,8 @@ bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) { bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n"); + LLVM_DEBUG(dbgs() << "Running on MBB: " << MBB + << " - scanning instructions...\n"); // First, scan the basic block producing a set of chains. @@ -343,7 +344,8 @@ bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) { for (auto &MI : MBB) scanInstruction(&MI, Idx++, ActiveChains, AllChains); - DEBUG(dbgs() << "Scan complete, "<< AllChains.size() << " chains created.\n"); + LLVM_DEBUG(dbgs() << "Scan complete, " << AllChains.size() + << " chains created.\n"); // Group the chains into disjoint sets based on their liveness range. This is // a poor-man's version of graph coloring. Ideally we'd create an interference @@ -360,7 +362,7 @@ bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) { for (auto &J : AllChains) if (I != J && I->rangeOverlapsWith(*J)) EC.unionSets(I.get(), J.get()); - DEBUG(dbgs() << "Created " << EC.getNumClasses() << " disjoint sets.\n"); + LLVM_DEBUG(dbgs() << "Created " << EC.getNumClasses() << " disjoint sets.\n"); // Now we assume that every member of an equivalence class interferes // with every other member of that class, and with no members of other classes. @@ -440,7 +442,7 @@ bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB, int &Parity) { bool Changed = false; - DEBUG(dbgs() << "colorChainSet(): #sets=" << GV.size() << "\n"); + LLVM_DEBUG(dbgs() << "colorChainSet(): #sets=" << GV.size() << "\n"); // Sort by descending size order so that we allocate the most important // sets first. @@ -470,16 +472,18 @@ bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV, // But if we really don't care, use the chain's preferred color. C = G->getPreferredColor(); - DEBUG(dbgs() << " - Parity=" << Parity << ", Color=" - << ColorNames[(int)C] << "\n"); + LLVM_DEBUG(dbgs() << " - Parity=" << Parity + << ", Color=" << ColorNames[(int)C] << "\n"); // If we'll need a fixup FMOV, don't bother. Testing has shown that this // happens infrequently and when it does it has at least a 50% chance of // slowing code down instead of speeding it up. if (G->requiresFixup() && C != G->getPreferredColor()) { C = G->getPreferredColor(); - DEBUG(dbgs() << " - " << G->str() << " - not worthwhile changing; " - "color remains " << ColorNames[(int)C] << "\n"); + LLVM_DEBUG(dbgs() << " - " << G->str() + << " - not worthwhile changing; " + "color remains " + << ColorNames[(int)C] << "\n"); } Changed |= colorChain(G, C, MBB); @@ -528,17 +532,17 @@ int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C, MachineBasicBlock &MBB) { bool Changed = false; - DEBUG(dbgs() << " - colorChain(" << G->str() << ", " - << ColorNames[(int)C] << ")\n"); + LLVM_DEBUG(dbgs() << " - colorChain(" << G->str() << ", " + << ColorNames[(int)C] << ")\n"); // Try and obtain a free register of the right class. Without a register // to play with we cannot continue. int Reg = scavengeRegister(G, C, MBB); if (Reg == -1) { - DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n"); + LLVM_DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n"); return false; } - DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); std::map<unsigned, unsigned> Substs; for (MachineInstr &I : *G) { @@ -586,11 +590,11 @@ bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C, assert(Substs.size() == 0 && "No substitutions should be left active!"); if (G->getKill()) { - DEBUG(dbgs() << " - Kill instruction seen.\n"); + LLVM_DEBUG(dbgs() << " - Kill instruction seen.\n"); } else { // We didn't have a kill instruction, but we didn't seem to need to change // the destination register anyway. - DEBUG(dbgs() << " - Destination register not changed.\n"); + LLVM_DEBUG(dbgs() << " - Destination register not changed.\n"); } return Changed; } @@ -611,8 +615,8 @@ void AArch64A57FPLoadBalancing::scanInstruction( // unit. unsigned DestReg = MI->getOperand(0).getReg(); - DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI) - << " at " << *MI); + LLVM_DEBUG(dbgs() << "New chain started for register " + << printReg(DestReg, TRI) << " at " << *MI); auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); ActiveChains[DestReg] = G.get(); @@ -631,8 +635,8 @@ void AArch64A57FPLoadBalancing::scanInstruction( maybeKillChain(MI->getOperand(0), Idx, ActiveChains); if (ActiveChains.find(AccumReg) != ActiveChains.end()) { - DEBUG(dbgs() << "Chain found for accumulator register " - << printReg(AccumReg, TRI) << " in MI " << *MI); + LLVM_DEBUG(dbgs() << "Chain found for accumulator register " + << printReg(AccumReg, TRI) << " in MI " << *MI); // For simplicity we only chain together sequences of MULs/MLAs where the // accumulator register is killed on each instruction. This means we don't @@ -641,7 +645,7 @@ void AArch64A57FPLoadBalancing::scanInstruction( // FIXME: We could extend to handle the non-kill cases for more coverage. if (MI->getOperand(3).isKill()) { // Add to chain. - DEBUG(dbgs() << "Instruction was successfully added to chain.\n"); + LLVM_DEBUG(dbgs() << "Instruction was successfully added to chain.\n"); ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); // Handle cases where the destination is not the same as the accumulator. if (DestReg != AccumReg) { @@ -651,13 +655,14 @@ void AArch64A57FPLoadBalancing::scanInstruction( return; } - DEBUG(dbgs() << "Cannot add to chain because accumulator operand wasn't " - << "marked <kill>!\n"); + LLVM_DEBUG( + dbgs() << "Cannot add to chain because accumulator operand wasn't " + << "marked <kill>!\n"); maybeKillChain(MI->getOperand(3), Idx, ActiveChains); } - DEBUG(dbgs() << "Creating new chain for dest register " - << printReg(DestReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Creating new chain for dest register " + << printReg(DestReg, TRI) << "\n"); auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); ActiveChains[DestReg] = G.get(); AllChains.push_back(std::move(G)); @@ -685,8 +690,8 @@ maybeKillChain(MachineOperand &MO, unsigned Idx, // If this is a KILL of a current chain, record it. if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) { - DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) + << "\n"); ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied()); } ActiveChains.erase(MO.getReg()); @@ -696,8 +701,8 @@ maybeKillChain(MachineOperand &MO, unsigned Idx, for (auto I = ActiveChains.begin(), E = ActiveChains.end(); I != E;) { if (MO.clobbersPhysReg(I->first)) { - DEBUG(dbgs() << "Kill (regmask) seen for chain " - << printReg(I->first, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Kill (regmask) seen for chain " + << printReg(I->first, TRI) << "\n"); I->second->setKill(MI, Idx, /*Immutable=*/true); ActiveChains.erase(I++); } else diff --git a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp index 338daecb49e..22b0c1e3b47 100644 --- a/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp @@ -277,7 +277,7 @@ static MachineInstr *insertCopy(const TargetInstrInfo *TII, MachineInstr &MI, MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::COPY), Dst) .addReg(Src, getKillRegState(IsKill)); - DEBUG(dbgs() << " adding copy: " << *MIB); + LLVM_DEBUG(dbgs() << " adding copy: " << *MIB); ++NumCopiesInserted; return MIB; } @@ -286,7 +286,7 @@ static MachineInstr *insertCopy(const TargetInstrInfo *TII, MachineInstr &MI, // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs // to be the correct register class, minimizing cross-class copies. void AArch64AdvSIMDScalar::transformInstruction(MachineInstr &MI) { - DEBUG(dbgs() << "Scalar transform: " << MI); + LLVM_DEBUG(dbgs() << "Scalar transform: " << MI); MachineBasicBlock *MBB = MI.getParent(); unsigned OldOpc = MI.getOpcode(); @@ -391,7 +391,7 @@ bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) { // runOnMachineFunction - Pass entry point from PassManager. bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) { bool Changed = false; - DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n"); + LLVM_DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n"); if (skipFunction(mf.getFunction())) return false; diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp index 0a9167edcdb..720323f81d2 100644 --- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp @@ -380,8 +380,8 @@ static bool handleMiddleInst(const MachineInstr &MI, LOHInfo &DefInfo, static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI, LOHInfo &Info) { if (Info.LastADRP != nullptr) { - DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n" << '\t' << MI << '\t' - << *Info.LastADRP); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n" + << '\t' << MI << '\t' << *Info.LastADRP); AFI.addLOHDirective(MCLOH_AdrpAdrp, {&MI, Info.LastADRP}); ++NumADRPSimpleCandidate; } @@ -390,48 +390,52 @@ static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI, if (Info.IsCandidate) { switch (Info.Type) { case MCLOH_AdrpAdd: - DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n" << '\t' << MI << '\t' - << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n" + << '\t' << MI << '\t' << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpAdd, {&MI, Info.MI0}); ++NumADRSimpleCandidate; break; case MCLOH_AdrpLdr: if (supportLoadFromLiteral(*Info.MI0)) { - DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n" << '\t' << MI << '\t' - << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n" + << '\t' << MI << '\t' << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpLdr, {&MI, Info.MI0}); ++NumADRPToLDR; } break; case MCLOH_AdrpAddLdr: - DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" + << '\t' << MI << '\t' << *Info.MI1 << '\t' + << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0}); ++NumADDToLDR; break; case MCLOH_AdrpAddStr: if (Info.MI1 != nullptr) { - DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" + << '\t' << MI << '\t' << *Info.MI1 << '\t' + << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpAddStr, {&MI, Info.MI1, Info.MI0}); ++NumADDToSTR; } break; case MCLOH_AdrpLdrGotLdr: - DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n" + << '\t' << MI << '\t' << *Info.MI1 << '\t' + << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpLdrGotLdr, {&MI, Info.MI1, Info.MI0}); ++NumLDRToLDR; break; case MCLOH_AdrpLdrGotStr: - DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n" << '\t' << MI << '\t' - << *Info.MI1 << '\t' << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n" + << '\t' << MI << '\t' << *Info.MI1 << '\t' + << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpLdrGotStr, {&MI, Info.MI1, Info.MI0}); ++NumLDRToSTR; break; case MCLOH_AdrpLdrGot: - DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n" << '\t' << MI << '\t' - << *Info.MI0); + LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n" + << '\t' << MI << '\t' << *Info.MI0); AFI.addLOHDirective(MCLOH_AdrpLdrGot, {&MI, Info.MI0}); break; case MCLOH_AdrpAdrp: @@ -485,8 +489,8 @@ bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(dbgs() << "********** AArch64 Collect LOH **********\n" - << "Looking in function " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** AArch64 Collect LOH **********\n" + << "Looking in function " << MF.getName() << '\n'); LOHInfo LOHInfos[N_GPR_REGS]; AArch64FunctionInfo &AFI = *MF.getInfo<AArch64FunctionInfo>(); diff --git a/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp b/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp index 30cefbad884..5ae787409ae 100644 --- a/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp +++ b/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp @@ -201,10 +201,10 @@ bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI, I->readsRegister(AArch64::NZCV, TRI)) return false; } - DEBUG(dbgs() << " Replacing instructions:\n "); - DEBUG(DefMI.print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(MI.print(dbgs())); + LLVM_DEBUG(dbgs() << " Replacing instructions:\n "); + LLVM_DEBUG(DefMI.print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(MI.print(dbgs())); NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); NewBr = convertToCondBr(MI); @@ -260,10 +260,10 @@ bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI, I->readsRegister(AArch64::NZCV, TRI)) return false; } - DEBUG(dbgs() << " Replacing instructions:\n "); - DEBUG(DefMI.print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(MI.print(dbgs())); + LLVM_DEBUG(dbgs() << " Replacing instructions:\n "); + LLVM_DEBUG(DefMI.print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(MI.print(dbgs())); NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); NewBr = convertToCondBr(MI); @@ -275,10 +275,10 @@ bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI, (void)NewCmp; (void)NewBr; assert(NewCmp && NewBr && "Expected new instructions."); - DEBUG(dbgs() << " with instruction:\n "); - DEBUG(NewCmp->print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(NewBr->print(dbgs())); + LLVM_DEBUG(dbgs() << " with instruction:\n "); + LLVM_DEBUG(NewCmp->print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(NewBr->print(dbgs())); // If this was a flag setting version of the instruction, we use the original // instruction by just clearing the dead marked on the implicit-def of NCZV. @@ -293,8 +293,9 @@ bool AArch64CondBrTuning::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(dbgs() << "********** AArch64 Conditional Branch Tuning **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG( + dbgs() << "********** AArch64 Conditional Branch Tuning **********\n" + << "********** Function: " << MF.getName() << '\n'); TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); TRI = MF.getSubtarget().getRegisterInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp index d14bde33d94..5064762b9f7 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp @@ -173,13 +173,14 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare( case AArch64::ADDSXri: { unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm()); if (!I->getOperand(2).isImm()) { - DEBUG(dbgs() << "Immediate of cmp is symbolic, " << *I << '\n'); + LLVM_DEBUG(dbgs() << "Immediate of cmp is symbolic, " << *I << '\n'); return nullptr; } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) { - DEBUG(dbgs() << "Immediate of cmp may be out of range, " << *I << '\n'); + LLVM_DEBUG(dbgs() << "Immediate of cmp may be out of range, " << *I + << '\n'); return nullptr; } else if (!MRI->use_empty(I->getOperand(0).getReg())) { - DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n'); + LLVM_DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n'); return nullptr; } return &*I; @@ -207,7 +208,8 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare( return nullptr; } } - DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n'); + LLVM_DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) + << '\n'); return nullptr; } @@ -325,8 +327,8 @@ bool AArch64ConditionOptimizer::adjustTo(MachineInstr *CmpMI, } bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n" + << "********** Function: " << MF.getName() << '\n'); if (skipFunction(MF.getFunction())) return false; @@ -384,15 +386,15 @@ bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) { const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm(); const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm(); - DEBUG(dbgs() << "Head branch:\n"); - DEBUG(dbgs() << "\tcondition: " - << AArch64CC::getCondCodeName(HeadCmp) << '\n'); - DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n'); + LLVM_DEBUG(dbgs() << "Head branch:\n"); + LLVM_DEBUG(dbgs() << "\tcondition: " << AArch64CC::getCondCodeName(HeadCmp) + << '\n'); + LLVM_DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n'); - DEBUG(dbgs() << "True branch:\n"); - DEBUG(dbgs() << "\tcondition: " - << AArch64CC::getCondCodeName(TrueCmp) << '\n'); - DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n'); + LLVM_DEBUG(dbgs() << "True branch:\n"); + LLVM_DEBUG(dbgs() << "\tcondition: " << AArch64CC::getCondCodeName(TrueCmp) + << '\n'); + LLVM_DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n'); if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::LT) || (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::GT)) && diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 9ff2472dbec..8176b6fb269 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -311,7 +311,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { return &*I; } ++NumCmpTermRejs; - DEBUG(dbgs() << "Flags not used by terminator: " << *I); + LLVM_DEBUG(dbgs() << "Flags not used by terminator: " << *I); return nullptr; } @@ -329,7 +329,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { // Check that the immediate operand is within range, ccmp wants a uimm5. // Rd = SUBSri Rn, imm, shift if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) { - DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I); + LLVM_DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I); ++NumImmRangeRejs; return nullptr; } @@ -340,7 +340,8 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { case AArch64::ADDSXrr: if (isDeadDef(I->getOperand(0).getReg())) return &*I; - DEBUG(dbgs() << "Can't convert compare with live destination: " << *I); + LLVM_DEBUG(dbgs() << "Can't convert compare with live destination: " + << *I); ++NumLiveDstRejs; return nullptr; case AArch64::FCMPSrr: @@ -358,18 +359,19 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { // The ccmp doesn't produce exactly the same flags as the original // compare, so reject the transform if there are uses of the flags // besides the terminators. - DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I); + LLVM_DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I); ++NumMultNZCVUses; return nullptr; } if (PRI.Defined || PRI.Clobbered) { - DEBUG(dbgs() << "Not convertible compare: " << *I); + LLVM_DEBUG(dbgs() << "Not convertible compare: " << *I); ++NumUnknNZCVDefs; return nullptr; } } - DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n'); + LLVM_DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) + << '\n'); return nullptr; } @@ -383,7 +385,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to // get right. if (!MBB->livein_empty()) { - DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n"); return false; } @@ -396,14 +398,14 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, continue; if (++InstrCount > BlockInstrLimit && !Stress) { - DEBUG(dbgs() << printMBBReference(*MBB) << " has more than " - << BlockInstrLimit << " instructions.\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than " + << BlockInstrLimit << " instructions.\n"); return false; } // There shouldn't normally be any phis in a single-predecessor block. if (I.isPHI()) { - DEBUG(dbgs() << "Can't hoist: " << I); + LLVM_DEBUG(dbgs() << "Can't hoist: " << I); return false; } @@ -411,20 +413,20 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, // speculate GOT or constant pool loads that are guaranteed not to trap, // but we don't support that for now. if (I.mayLoad()) { - DEBUG(dbgs() << "Won't speculate load: " << I); + LLVM_DEBUG(dbgs() << "Won't speculate load: " << I); return false; } // We never speculate stores, so an AA pointer isn't necessary. bool DontMoveAcrossStore = true; if (!I.isSafeToMove(nullptr, DontMoveAcrossStore)) { - DEBUG(dbgs() << "Can't speculate: " << I); + LLVM_DEBUG(dbgs() << "Can't speculate: " << I); return false; } // Only CmpMI is allowed to clobber the flags. if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) { - DEBUG(dbgs() << "Clobbers flags: " << I); + LLVM_DEBUG(dbgs() << "Clobbers flags: " << I); return false; } } @@ -458,9 +460,9 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { return false; // The CFG topology checks out. - DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> " - << printMBBReference(*CmpBB) << " -> " - << printMBBReference(*Tail) << '\n'); + LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> " + << printMBBReference(*CmpBB) << " -> " + << printMBBReference(*Tail) << '\n'); ++NumConsidered; // Tail is allowed to have many predecessors, but we can't handle PHIs yet. @@ -470,13 +472,13 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { // always be safe to sink the ccmp down to immediately before the CmpBB // terminators. if (!trivialTailPHIs()) { - DEBUG(dbgs() << "Can't handle phis in Tail.\n"); + LLVM_DEBUG(dbgs() << "Can't handle phis in Tail.\n"); ++NumPhiRejs; return false; } if (!Tail->livein_empty()) { - DEBUG(dbgs() << "Can't handle live-in physregs in Tail.\n"); + LLVM_DEBUG(dbgs() << "Can't handle live-in physregs in Tail.\n"); ++NumPhysRejs; return false; } @@ -484,13 +486,13 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { // CmpBB should never have PHIs since Head is its only predecessor. // FIXME: Clean them up if it happens. if (!CmpBB->empty() && CmpBB->front().isPHI()) { - DEBUG(dbgs() << "Can't handle phis in CmpBB.\n"); + LLVM_DEBUG(dbgs() << "Can't handle phis in CmpBB.\n"); ++NumPhi2Rejs; return false; } if (!CmpBB->livein_empty()) { - DEBUG(dbgs() << "Can't handle live-in physregs in CmpBB.\n"); + LLVM_DEBUG(dbgs() << "Can't handle live-in physregs in CmpBB.\n"); ++NumPhysRejs; return false; } @@ -499,7 +501,7 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { HeadCond.clear(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; if (TII->analyzeBranch(*Head, TBB, FBB, HeadCond)) { - DEBUG(dbgs() << "Head branch not analyzable.\n"); + LLVM_DEBUG(dbgs() << "Head branch not analyzable.\n"); ++NumHeadBranchRejs; return false; } @@ -507,13 +509,14 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { // This is weird, probably some sort of degenerate CFG, or an edge to a // landing pad. if (!TBB || HeadCond.empty()) { - DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n"); + LLVM_DEBUG( + dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n"); ++NumHeadBranchRejs; return false; } if (!parseCond(HeadCond, HeadCmpBBCC)) { - DEBUG(dbgs() << "Unsupported branch type on Head\n"); + LLVM_DEBUG(dbgs() << "Unsupported branch type on Head\n"); ++NumHeadBranchRejs; return false; } @@ -527,19 +530,20 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { CmpBBCond.clear(); TBB = FBB = nullptr; if (TII->analyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) { - DEBUG(dbgs() << "CmpBB branch not analyzable.\n"); + LLVM_DEBUG(dbgs() << "CmpBB branch not analyzable.\n"); ++NumCmpBranchRejs; return false; } if (!TBB || CmpBBCond.empty()) { - DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n"); + LLVM_DEBUG( + dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n"); ++NumCmpBranchRejs; return false; } if (!parseCond(CmpBBCond, CmpBBTailCC)) { - DEBUG(dbgs() << "Unsupported branch type on CmpBB\n"); + LLVM_DEBUG(dbgs() << "Unsupported branch type on CmpBB\n"); ++NumCmpBranchRejs; return false; } @@ -547,9 +551,10 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { if (TBB != Tail) CmpBBTailCC = AArch64CC::getInvertedCondCode(CmpBBTailCC); - DEBUG(dbgs() << "Head->CmpBB on " << AArch64CC::getCondCodeName(HeadCmpBBCC) - << ", CmpBB->Tail on " << AArch64CC::getCondCodeName(CmpBBTailCC) - << '\n'); + LLVM_DEBUG(dbgs() << "Head->CmpBB on " + << AArch64CC::getCondCodeName(HeadCmpBBCC) + << ", CmpBB->Tail on " + << AArch64CC::getCondCodeName(CmpBBTailCC) << '\n'); CmpMI = findConvertibleCompare(CmpBB); if (!CmpMI) @@ -563,9 +568,9 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { } void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) { - DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into " - << printMBBReference(*Head) << ":\n" - << *CmpBB); + LLVM_DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into " + << printMBBReference(*Head) << ":\n" + << *CmpBB); // All CmpBB instructions are moved into Head, and CmpBB is deleted. // Update the CFG first. @@ -710,7 +715,7 @@ void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) { RemovedBlocks.push_back(CmpBB); CmpBB->eraseFromParent(); - DEBUG(dbgs() << "Result:\n" << *Head); + LLVM_DEBUG(dbgs() << "Result:\n" << *Head); ++NumConverted; } @@ -860,13 +865,13 @@ bool AArch64ConditionalCompares::shouldConvert() { // If code size is the main concern if (MinSize) { int CodeSizeDelta = CmpConv.expectedCodeSizeDelta(); - DEBUG(dbgs() << "Code size delta: " << CodeSizeDelta << '\n'); + LLVM_DEBUG(dbgs() << "Code size delta: " << CodeSizeDelta << '\n'); // If we are minimizing the code size, do the conversion whatever // the cost is. if (CodeSizeDelta < 0) return true; if (CodeSizeDelta > 0) { - DEBUG(dbgs() << "Code size is increasing, give up on this one.\n"); + LLVM_DEBUG(dbgs() << "Code size is increasing, give up on this one.\n"); return false; } // CodeSizeDelta == 0, continue with the regular heuristics @@ -885,24 +890,24 @@ bool AArch64ConditionalCompares::shouldConvert() { Trace.getInstrCycles(*CmpConv.Head->getFirstTerminator()).Depth; unsigned CmpBBDepth = Trace.getInstrCycles(*CmpConv.CmpBB->getFirstTerminator()).Depth; - DEBUG(dbgs() << "Head depth: " << HeadDepth - << "\nCmpBB depth: " << CmpBBDepth << '\n'); + LLVM_DEBUG(dbgs() << "Head depth: " << HeadDepth + << "\nCmpBB depth: " << CmpBBDepth << '\n'); if (CmpBBDepth > HeadDepth + DelayLimit) { - DEBUG(dbgs() << "Branch delay would be larger than " << DelayLimit - << " cycles.\n"); + LLVM_DEBUG(dbgs() << "Branch delay would be larger than " << DelayLimit + << " cycles.\n"); return false; } // Check the resource depth at the bottom of CmpBB - these instructions will // be speculated. unsigned ResDepth = Trace.getResourceDepth(true); - DEBUG(dbgs() << "Resources: " << ResDepth << '\n'); + LLVM_DEBUG(dbgs() << "Resources: " << ResDepth << '\n'); // Heuristic: The speculatively executed instructions must all be able to // merge into the Head block. The Head critical path should dominate the // resource cost of the speculated instructions. if (ResDepth > HeadDepth) { - DEBUG(dbgs() << "Too many instructions to speculate.\n"); + LLVM_DEBUG(dbgs() << "Too many instructions to speculate.\n"); return false; } return true; @@ -922,8 +927,8 @@ bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) { } bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n" - << "********** Function: " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n" + << "********** Function: " << MF.getName() << '\n'); if (skipFunction(MF.getFunction())) return false; diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 8e7e740da6f..2ba10d25e93 100644 --- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -136,18 +136,21 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock( // We need to skip this instruction because while it appears to have a // dead def it uses a frame index which might expand into a multi // instruction sequence during EPI. - DEBUG(dbgs() << " Ignoring, operand is frame index\n"); + LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n"); continue; } if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) { // It is not allowed to write to the same register (not even the zero // register) twice in a single instruction. - DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n"); + LLVM_DEBUG( + dbgs() + << " Ignoring, XZR or WZR already used by the instruction\n"); continue; } if (shouldSkip(MI, MF)) { - DEBUG(dbgs() << " Ignoring, Atomic instruction with acquire semantics using WZR/XZR\n"); + LLVM_DEBUG(dbgs() << " Ignoring, Atomic instruction with acquire " + "semantics using WZR/XZR\n"); continue; } @@ -163,30 +166,30 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock( (!MO.isDead() && !MRI->use_nodbg_empty(Reg))) continue; assert(!MO.isImplicit() && "Unexpected implicit def!"); - DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; - MI.print(dbgs())); + LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; + MI.print(dbgs())); // Be careful not to change the register if it's a tied operand. if (MI.isRegTiedToUseOperand(I)) { - DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); + LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); continue; } const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); unsigned NewReg; if (RC == nullptr) { - DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); + LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); continue; } else if (RC->contains(AArch64::WZR)) NewReg = AArch64::WZR; else if (RC->contains(AArch64::XZR)) NewReg = AArch64::XZR; else { - DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); + LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); continue; } - DEBUG(dbgs() << " Replacing with zero register. New:\n "); + LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n "); MO.setReg(NewReg); MO.setIsDead(); - DEBUG(MI.print(dbgs())); + LLVM_DEBUG(MI.print(dbgs())); ++NumDeadDefsReplaced; Changed = true; // Only replace one dead register, see check for zero register above. @@ -204,7 +207,7 @@ bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { TRI = MF.getSubtarget().getRegisterInfo(); TII = MF.getSubtarget().getInstrInfo(); MRI = &MF.getRegInfo(); - DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); + LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); Changed = false; for (auto &MBB : MF) processMachineBasicBlock(MBB); diff --git a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp index 4be44ecb52d..bc9a5ca97fe 100644 --- a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp +++ b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp @@ -169,7 +169,7 @@ bool FalkorMarkStridedAccesses::runOnLoop(Loop &L) { LoadI->setMetadata(FALKOR_STRIDED_ACCESS_MD, MDNode::get(LoadI->getContext(), {})); ++NumStridedLoadsMarked; - DEBUG(dbgs() << "Load: " << I << " marked as strided\n"); + LLVM_DEBUG(dbgs() << "Load: " << I << " marked as strided\n"); MadeChange = true; } } @@ -731,10 +731,10 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { continue; bool Fixed = false; - DEBUG(dbgs() << "Attempting to fix tag collision: " << MI); + LLVM_DEBUG(dbgs() << "Attempting to fix tag collision: " << MI); if (!DebugCounter::shouldExecute(FixCounter)) { - DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI); + LLVM_DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI); continue; } @@ -759,8 +759,8 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { if (TagMap.count(NewTag)) continue; - DEBUG(dbgs() << "Changing base reg to: " << printReg(ScratchReg, TRI) - << '\n'); + LLVM_DEBUG(dbgs() << "Changing base reg to: " + << printReg(ScratchReg, TRI) << '\n'); // Rewrite: // Xd = LOAD Xb, off @@ -778,8 +778,8 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) { // If the load does a pre/post increment, then insert a MOV after as // well to update the real base register. if (LdI.IsPrePost) { - DEBUG(dbgs() << "Doing post MOV of incremented reg: " - << printReg(ScratchReg, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Doing post MOV of incremented reg: " + << printReg(ScratchReg, TRI) << '\n'); MI.getOperand(0).setReg( ScratchReg); // Change tied operand pre/post update dest. BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL, diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 2523cfdfb53..6dc5d19862a 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1287,13 +1287,11 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui; else StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui; - DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); - if (RPI.isPaired()) - dbgs() << ", " << printReg(Reg2, TRI); - dbgs() << ") -> fi#(" << RPI.FrameIdx; - if (RPI.isPaired()) - dbgs() << ", " << RPI.FrameIdx+1; - dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); + if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); + dbgs() << ") -> fi#(" << RPI.FrameIdx; + if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1; + dbgs() << ")\n"); MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc)); if (!MRI.isReserved(Reg1)) @@ -1350,13 +1348,11 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui; else LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui; - DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI); - if (RPI.isPaired()) - dbgs() << ", " << printReg(Reg2, TRI); - dbgs() << ") -> fi#(" << RPI.FrameIdx; - if (RPI.isPaired()) - dbgs() << ", " << RPI.FrameIdx+1; - dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI); + if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); + dbgs() << ") -> fi#(" << RPI.FrameIdx; + if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx + 1; + dbgs() << ")\n"); MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc)); if (RPI.isPaired()) { @@ -1465,10 +1461,11 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, } } - DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:"; - for (unsigned Reg : SavedRegs.set_bits()) - dbgs() << ' ' << printReg(Reg, RegInfo); - dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:"; + for (unsigned Reg + : SavedRegs.set_bits()) dbgs() + << ' ' << printReg(Reg, RegInfo); + dbgs() << "\n";); // If any callee-saved registers are used, the frame cannot be eliminated. unsigned NumRegsSpilled = SavedRegs.count(); @@ -1477,7 +1474,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, // The CSR spill slots have not been allocated yet, so estimateStackSize // won't include them. unsigned CFSize = MFI.estimateStackSize(MF) + 8 * NumRegsSpilled; - DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n"); + LLVM_DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n"); unsigned EstimatedStackSizeLimit = estimateRSStackSizeLimit(MF); bool BigStack = (CFSize > EstimatedStackSizeLimit); if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) @@ -1491,8 +1488,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, // here. if (BigStack) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { - DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) - << " to get a scratch register.\n"); + LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) + << " to get a scratch register.\n"); SavedRegs.set(UnspilledCSGPR); // MachO's compact unwind format relies on all registers being stored in // pairs, so if we need to spill one extra for BigStack, then we need to @@ -1512,8 +1509,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, unsigned Align = TRI->getSpillAlignment(RC); int FI = MFI.CreateStackObject(Size, Align, false); RS->addScavengingFrameIndex(FI); - DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI - << " as the emergency spill slot.\n"); + LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI + << " as the emergency spill slot.\n"); } } diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 3124204fc59..fd040313179 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -1553,8 +1553,9 @@ static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N, // Bail out on large immediates. This happens when no proper // combining/constant folding was performed. if (!BiggerPattern && (SrlImm <= 0 || SrlImm >= VT.getSizeInBits())) { - DEBUG((dbgs() << N - << ": Found large shift immediate, this should not happen\n")); + LLVM_DEBUG( + (dbgs() << N + << ": Found large shift immediate, this should not happen\n")); return false; } @@ -1696,8 +1697,9 @@ static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0, // Missing combines/constant folding may have left us with strange // constants. if (ShlImm >= VT.getSizeInBits()) { - DEBUG((dbgs() << N - << ": Found large shift immediate, this should not happen\n")); + LLVM_DEBUG( + (dbgs() << N + << ": Found large shift immediate, this should not happen\n")); return false; } @@ -2657,7 +2659,7 @@ bool AArch64DAGToDAGISel::SelectCMP_SWAP(SDNode *N) { void AArch64DAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); Node->setNodeId(-1); return; } @@ -2754,9 +2756,9 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { } SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT, Node->getOperand(0)); - DEBUG(dbgs() << "ISEL: Custom selection!\n=> "); - DEBUG(Extract->dumpr(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "ISEL: Custom selection!\n=> "); + LLVM_DEBUG(Extract->dumpr(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); ReplaceNode(Node, Extract.getNode()); return; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 8dc13c6fb24..51063ee7fb4 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1442,7 +1442,8 @@ static void changeVectorFPCCToAArch64CC(ISD::CondCode CC, static bool isLegalArithImmed(uint64_t C) { // Matches AArch64DAGToDAGISel::SelectArithImmed(). bool IsLegal = (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0); - DEBUG(dbgs() << "Is imm " << C << " legal: " << (IsLegal ? "yes\n" : "no\n")); + LLVM_DEBUG(dbgs() << "Is imm " << C + << " legal: " << (IsLegal ? "yes\n" : "no\n")); return IsLegal; } @@ -2644,8 +2645,8 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { - DEBUG(dbgs() << "Custom lowering: "); - DEBUG(Op.dump()); + LLVM_DEBUG(dbgs() << "Custom lowering: "); + LLVM_DEBUG(Op.dump()); switch (Op.getOpcode()) { default: @@ -3774,7 +3775,7 @@ SDValue AArch64TargetLowering::getTargetNode(BlockAddressSDNode* N, EVT Ty, template <class NodeTy> SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const { - DEBUG(dbgs() << "AArch64TargetLowering::getGOT\n"); + LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getGOT\n"); SDLoc DL(N); EVT Ty = getPointerTy(DAG.getDataLayout()); SDValue GotAddr = getTargetNode(N, Ty, DAG, AArch64II::MO_GOT | Flags); @@ -3787,7 +3788,7 @@ SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG, template <class NodeTy> SDValue AArch64TargetLowering::getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const { - DEBUG(dbgs() << "AArch64TargetLowering::getAddrLarge\n"); + LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrLarge\n"); SDLoc DL(N); EVT Ty = getPointerTy(DAG.getDataLayout()); const unsigned char MO_NC = AArch64II::MO_NC; @@ -3803,7 +3804,7 @@ SDValue AArch64TargetLowering::getAddrLarge(NodeTy *N, SelectionDAG &DAG, template <class NodeTy> SDValue AArch64TargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags) const { - DEBUG(dbgs() << "AArch64TargetLowering::getAddr\n"); + LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddr\n"); SDLoc DL(N); EVT Ty = getPointerTy(DAG.getDataLayout()); SDValue Hi = getTargetNode(N, Ty, DAG, AArch64II::MO_PAGE | Flags); @@ -5073,7 +5074,8 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { // FIXME: We should be able to handle f128 as well with a clever lowering. if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 || (VT == MVT::f16 && Subtarget->hasFullFP16()))) { - DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n"); + LLVM_DEBUG( + dbgs() << "Legal fp imm: materialize 0 using the zero register\n"); return true; } @@ -5094,14 +5096,17 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { } if (IsLegal) { - DEBUG(dbgs() << "Legal " << FPType << " imm value: " << ImmStrVal << "\n"); + LLVM_DEBUG(dbgs() << "Legal " << FPType << " imm value: " << ImmStrVal + << "\n"); return true; } if (!FPType.empty()) - DEBUG(dbgs() << "Illegal " << FPType << " imm value: " << ImmStrVal << "\n"); + LLVM_DEBUG(dbgs() << "Illegal " << FPType << " imm value: " << ImmStrVal + << "\n"); else - DEBUG(dbgs() << "Illegal fp imm " << ImmStrVal << ": unsupported fp type\n"); + LLVM_DEBUG(dbgs() << "Illegal fp imm " << ImmStrVal + << ": unsupported fp type\n"); return false; } @@ -5540,7 +5545,7 @@ static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) { SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const { assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!"); - DEBUG(dbgs() << "AArch64TargetLowering::ReconstructShuffle\n"); + LLVM_DEBUG(dbgs() << "AArch64TargetLowering::ReconstructShuffle\n"); SDLoc dl(Op); EVT VT = Op.getValueType(); unsigned NumElts = VT.getVectorNumElements(); @@ -5576,10 +5581,11 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, continue; else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT || !isa<ConstantSDNode>(V.getOperand(1))) { - DEBUG(dbgs() << "Reshuffle failed: " - "a shuffle can only come from building a vector from " - "various elements of other vectors, provided their " - "indices are constant\n"); + LLVM_DEBUG( + dbgs() << "Reshuffle failed: " + "a shuffle can only come from building a vector from " + "various elements of other vectors, provided their " + "indices are constant\n"); return SDValue(); } @@ -5596,8 +5602,9 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, } if (Sources.size() > 2) { - DEBUG(dbgs() << "Reshuffle failed: currently only do something sane when at " - "most two source vectors are involved\n"); + LLVM_DEBUG( + dbgs() << "Reshuffle failed: currently only do something sane when at " + "most two source vectors are involved\n"); return SDValue(); } @@ -5643,7 +5650,8 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()); if (Src.MaxElt - Src.MinElt >= NumSrcElts) { - DEBUG(dbgs() << "Reshuffle failed: span too large for a VEXT to cope\n"); + LLVM_DEBUG( + dbgs() << "Reshuffle failed: span too large for a VEXT to cope\n"); return SDValue(); } @@ -5689,10 +5697,9 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, } // Final sanity check before we try to actually produce a shuffle. - DEBUG( - for (auto Src : Sources) - assert(Src.ShuffleVec.getValueType() == ShuffleVT); - ); + LLVM_DEBUG(for (auto Src + : Sources) + assert(Src.ShuffleVec.getValueType() == ShuffleVT);); // The stars all align, our next step is to produce the mask for the shuffle. SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1); @@ -5725,7 +5732,7 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, // Final check before we try to produce nonsense... if (!isShuffleMaskLegal(Mask, ShuffleVT)) { - DEBUG(dbgs() << "Reshuffle failed: illegal shuffle mask\n"); + LLVM_DEBUG(dbgs() << "Reshuffle failed: illegal shuffle mask\n"); return SDValue(); } @@ -5737,12 +5744,8 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, ShuffleOps[1], Mask); SDValue V = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); - DEBUG( - dbgs() << "Reshuffle, creating node: "; - Shuffle.dump(); - dbgs() << "Reshuffle, creating node: "; - V.dump(); - ); + LLVM_DEBUG(dbgs() << "Reshuffle, creating node: "; Shuffle.dump(); + dbgs() << "Reshuffle, creating node: "; V.dump();); return V; } @@ -6699,10 +6702,10 @@ static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) { DAG.getConstant(Intrin, DL, MVT::i32), X, Y, Shift.getOperand(1)); - DEBUG(dbgs() << "aarch64-lower: transformed: \n"); - DEBUG(N->dump(&DAG)); - DEBUG(dbgs() << "into: \n"); - DEBUG(ResultSLI->dump(&DAG)); + LLVM_DEBUG(dbgs() << "aarch64-lower: transformed: \n"); + LLVM_DEBUG(N->dump(&DAG)); + LLVM_DEBUG(dbgs() << "into: \n"); + LLVM_DEBUG(ResultSLI->dump(&DAG)); ++NumShiftInserts; return ResultSLI; @@ -6889,13 +6892,14 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, } if (!Value.getNode()) { - DEBUG(dbgs() << "LowerBUILD_VECTOR: value undefined, creating undef node\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: value undefined, creating undef node\n"); return DAG.getUNDEF(VT); } if (isOnlyLowElement) { - DEBUG(dbgs() << "LowerBUILD_VECTOR: only low element used, creating 1 " - "SCALAR_TO_VECTOR node\n"); + LLVM_DEBUG(dbgs() << "LowerBUILD_VECTOR: only low element used, creating 1 " + "SCALAR_TO_VECTOR node\n"); return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); } @@ -6966,7 +6970,8 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, if (!isConstant) { if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT || Value.getValueType() != VT) { - DEBUG(dbgs() << "LowerBUILD_VECTOR: use DUP for non-constant splats\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: use DUP for non-constant splats\n"); return DAG.getNode(AArch64ISD::DUP, dl, VT, Value); } @@ -6975,8 +6980,9 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SDValue Lane = Value.getOperand(1); Value = Value.getOperand(0); if (Value.getValueSizeInBits() == 64) { - DEBUG(dbgs() << "LowerBUILD_VECTOR: DUPLANE works on 128-bit vectors, " - "widening it\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: DUPLANE works on 128-bit vectors, " + "widening it\n"); Value = WidenVector(Value, DAG); } @@ -6989,17 +6995,16 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, EVT EltTy = VT.getVectorElementType(); assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) && "Unsupported floating-point vector type"); - DEBUG(dbgs() << "LowerBUILD_VECTOR: float constant splats, creating int " - "BITCASTS, and try again\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: float constant splats, creating int " + "BITCASTS, and try again\n"); MVT NewType = MVT::getIntegerVT(EltTy.getSizeInBits()); for (unsigned i = 0; i < NumElts; ++i) Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i))); EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); SDValue Val = DAG.getBuildVector(VecVT, dl, Ops); - DEBUG( - dbgs() << "LowerBUILD_VECTOR: trying to lower new vector: "; - Val.dump(); - ); + LLVM_DEBUG(dbgs() << "LowerBUILD_VECTOR: trying to lower new vector: "; + Val.dump();); Val = LowerBUILD_VECTOR(Val, DAG); if (Val.getNode()) return DAG.getNode(ISD::BITCAST, dl, VT, Val); @@ -7034,8 +7039,9 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, // This will generate a load from the constant pool. if (isConstant) { - DEBUG(dbgs() << "LowerBUILD_VECTOR: all elements are constant, use default " - "expansion\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: all elements are constant, use default " + "expansion\n"); return SDValue(); } @@ -7052,8 +7058,9 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, // shuffle is valid for the target) and materialization element by element // on the stack followed by a load for everything else. if (!isConstant && !usesOnlyOneValue) { - DEBUG(dbgs() << "LowerBUILD_VECTOR: alternatives failed, creating sequence " - "of INSERT_VECTOR_ELT\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: alternatives failed, creating sequence " + "of INSERT_VECTOR_ELT\n"); SDValue Vec = DAG.getUNDEF(VT); SDValue Op0 = Op.getOperand(0); @@ -7070,14 +7077,12 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, // extended (i32) and it is safe to cast them to the vector type by ignoring // the upper bits of the lowest lane (e.g. v8i8, v4i16). if (!Op0.isUndef()) { - DEBUG(dbgs() << "Creating node for op0, it is not undefined:\n"); + LLVM_DEBUG(dbgs() << "Creating node for op0, it is not undefined:\n"); Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0); ++i; } - DEBUG( - if (i < NumElts) - dbgs() << "Creating nodes for the other vector elements:\n"; - ); + LLVM_DEBUG(if (i < NumElts) dbgs() + << "Creating nodes for the other vector elements:\n";); for (; i < NumElts; ++i) { SDValue V = Op.getOperand(i); if (V.isUndef()) @@ -7088,8 +7093,9 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, return Vec; } - DEBUG(dbgs() << "LowerBUILD_VECTOR: use default expansion, failed to find " - "better alternative\n"); + LLVM_DEBUG( + dbgs() << "LowerBUILD_VECTOR: use default expansion, failed to find " + "better alternative\n"); return SDValue(); } @@ -8216,15 +8222,16 @@ EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, // 12-bit optionally shifted immediates are legal for adds. bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const { if (Immed == std::numeric_limits<int64_t>::min()) { - DEBUG(dbgs() << "Illegal add imm " << Immed << ": avoid UB for INT64_MIN\n"); + LLVM_DEBUG(dbgs() << "Illegal add imm " << Immed + << ": avoid UB for INT64_MIN\n"); return false; } // Same encoding for add/sub, just flip the sign. Immed = std::abs(Immed); bool IsLegal = ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0)); - DEBUG(dbgs() << "Is " << Immed << " legal add imm: " << - (IsLegal ? "yes" : "no") << "\n"); + LLVM_DEBUG(dbgs() << "Is " << Immed + << " legal add imm: " << (IsLegal ? "yes" : "no") << "\n"); return IsLegal; } @@ -9028,7 +9035,8 @@ static SDValue performBitcastCombine(SDNode *N, SVT.getVectorNumElements() != VT.getVectorNumElements() * 2) return SDValue(); - DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n"); + LLVM_DEBUG( + dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n"); // Create the simplified form to just extract the low or high half of the // vector directly rather than bothering with the bitcasts. @@ -9116,7 +9124,8 @@ static SDValue performConcatVectorsCombine(SDNode *N, if (!RHSTy.isVector()) return SDValue(); - DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n"); + LLVM_DEBUG( + dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n"); MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(), RHSTy.getVectorNumElements() * 2); @@ -10758,7 +10767,7 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, SelectionDAG &DAG = DCI.DAG; switch (N->getOpcode()) { default: - DEBUG(dbgs() << "Custom combining: skipping\n"); + LLVM_DEBUG(dbgs() << "Custom combining: skipping\n"); break; case ISD::ADD: case ISD::SUB: diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index c7ece250aa8..4d7ca2349ed 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -174,7 +174,7 @@ static bool unsupportedBinOp(const MachineInstr &I, const AArch64RegisterInfo &TRI) { LLT Ty = MRI.getType(I.getOperand(0).getReg()); if (!Ty.isValid()) { - DEBUG(dbgs() << "Generic binop register should be typed\n"); + LLVM_DEBUG(dbgs() << "Generic binop register should be typed\n"); return true; } @@ -182,7 +182,7 @@ static bool unsupportedBinOp(const MachineInstr &I, for (auto &MO : I.operands()) { // FIXME: Support non-register operands. if (!MO.isReg()) { - DEBUG(dbgs() << "Generic inst non-reg operands are unsupported\n"); + LLVM_DEBUG(dbgs() << "Generic inst non-reg operands are unsupported\n"); return true; } @@ -191,18 +191,18 @@ static bool unsupportedBinOp(const MachineInstr &I, // bank out of the minimal class for the register. // Either way, this needs to be documented (and possibly verified). if (!TargetRegisterInfo::isVirtualRegister(MO.getReg())) { - DEBUG(dbgs() << "Generic inst has physical register operand\n"); + LLVM_DEBUG(dbgs() << "Generic inst has physical register operand\n"); return true; } const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); if (!OpBank) { - DEBUG(dbgs() << "Generic register has no bank or class\n"); + LLVM_DEBUG(dbgs() << "Generic register has no bank or class\n"); return true; } if (PrevOpBank && OpBank != PrevOpBank) { - DEBUG(dbgs() << "Generic inst operands have different banks\n"); + LLVM_DEBUG(dbgs() << "Generic inst operands have different banks\n"); return true; } PrevOpBank = OpBank; @@ -378,7 +378,7 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterClass *RC = getRegClassForTypeOnBank( MRI.getType(DstReg), RegBank, RBI, /* GetAllRegSet */ true); if (!RC) { - DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n'); + LLVM_DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n'); return false; } @@ -412,8 +412,8 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, // we hit another of its use or its defs. // Copies do not have constraints. if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } I.setDesc(TII.get(AArch64::COPY)); @@ -686,13 +686,13 @@ bool AArch64InstructionSelector::select(MachineInstr &I, DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>(); if (!DefRC) { if (!DefTy.isValid()) { - DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n"); + LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n"); return false; } const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); if (!DefRC) { - DEBUG(dbgs() << "PHI operand has unexpected size/bank\n"); + LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n"); return false; } } @@ -710,7 +710,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, if (I.getNumOperands() != I.getNumExplicitOperands()) { - DEBUG(dbgs() << "Generic instruction has unexpected implicit operands\n"); + LLVM_DEBUG( + dbgs() << "Generic instruction has unexpected implicit operands\n"); return false; } @@ -726,8 +727,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, // We shouldn't need this on AArch64, but it would be implemented as an // EXTRACT_SUBREG followed by a TBNZW because TBNZX has no encoding if the // bit being tested is < 32. - DEBUG(dbgs() << "G_BRCOND has type: " << Ty - << ", expected at most 32-bits"); + LLVM_DEBUG(dbgs() << "G_BRCOND has type: " << Ty + << ", expected at most 32-bits"); return false; } @@ -767,15 +768,16 @@ bool AArch64InstructionSelector::select(MachineInstr &I, // FIXME: Redundant check, but even less readable when factored out. if (isFP) { if (Ty != s32 && Ty != s64) { - DEBUG(dbgs() << "Unable to materialize FP " << Ty - << " constant, expected: " << s32 << " or " << s64 - << '\n'); + LLVM_DEBUG(dbgs() << "Unable to materialize FP " << Ty + << " constant, expected: " << s32 << " or " << s64 + << '\n'); return false; } if (RB.getID() != AArch64::FPRRegBankID) { - DEBUG(dbgs() << "Unable to materialize FP " << Ty - << " constant on bank: " << RB << ", expected: FPR\n"); + LLVM_DEBUG(dbgs() << "Unable to materialize FP " << Ty + << " constant on bank: " << RB + << ", expected: FPR\n"); return false; } @@ -786,15 +788,16 @@ bool AArch64InstructionSelector::select(MachineInstr &I, } else { // s32 and s64 are covered by tablegen. if (Ty != p0) { - DEBUG(dbgs() << "Unable to materialize integer " << Ty - << " constant, expected: " << s32 << ", " << s64 << ", or " - << p0 << '\n'); + LLVM_DEBUG(dbgs() << "Unable to materialize integer " << Ty + << " constant, expected: " << s32 << ", " << s64 + << ", or " << p0 << '\n'); return false; } if (RB.getID() != AArch64::GPRRegBankID) { - DEBUG(dbgs() << "Unable to materialize integer " << Ty - << " constant on bank: " << RB << ", expected: GPR\n"); + LLVM_DEBUG(dbgs() << "Unable to materialize integer " << Ty + << " constant on bank: " << RB + << ", expected: GPR\n"); return false; } } @@ -820,7 +823,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I, .addUse(DefGPRReg); if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain G_FCONSTANT def operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain G_FCONSTANT def operand\n"); return false; } @@ -908,8 +911,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, case TargetOpcode::G_FRAME_INDEX: { // allocas and G_FRAME_INDEX are only supported in addrspace(0). if (Ty != LLT::pointer(0, 64)) { - DEBUG(dbgs() << "G_FRAME_INDEX pointer has type: " << Ty - << ", expected: " << LLT::pointer(0, 64) << '\n'); + LLVM_DEBUG(dbgs() << "G_FRAME_INDEX pointer has type: " << Ty + << ", expected: " << LLT::pointer(0, 64) << '\n'); return false; } I.setDesc(TII.get(AArch64::ADDXri)); @@ -980,14 +983,14 @@ bool AArch64InstructionSelector::select(MachineInstr &I, LLT PtrTy = MRI.getType(I.getOperand(1).getReg()); if (PtrTy != LLT::pointer(0, 64)) { - DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy - << ", expected: " << LLT::pointer(0, 64) << '\n'); + LLVM_DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy + << ", expected: " << LLT::pointer(0, 64) << '\n'); return false; } auto &MemOp = **I.memoperands_begin(); if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) { - DEBUG(dbgs() << "Atomic load/store not supported yet\n"); + LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n"); return false; } unsigned MemSizeInBits = MemOp.getSize() * 8; @@ -1066,13 +1069,13 @@ bool AArch64InstructionSelector::select(MachineInstr &I, const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); if (RB.getID() != AArch64::GPRRegBankID) { - DEBUG(dbgs() << "G_[SU]MULH on bank: " << RB << ", expected: GPR\n"); + LLVM_DEBUG(dbgs() << "G_[SU]MULH on bank: " << RB << ", expected: GPR\n"); return false; } if (Ty != LLT::scalar(64)) { - DEBUG(dbgs() << "G_[SU]MULH has type: " << Ty - << ", expected: " << LLT::scalar(64) << '\n'); + LLVM_DEBUG(dbgs() << "G_[SU]MULH has type: " << Ty + << ", expected: " << LLT::scalar(64) << '\n'); return false; } @@ -1138,7 +1141,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); if (DstRB.getID() != SrcRB.getID()) { - DEBUG(dbgs() << "G_TRUNC/G_PTRTOINT input/output on different banks\n"); + LLVM_DEBUG( + dbgs() << "G_TRUNC/G_PTRTOINT input/output on different banks\n"); return false; } @@ -1155,7 +1159,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I, if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain G_TRUNC/G_PTRTOINT\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain G_TRUNC/G_PTRTOINT\n"); return false; } @@ -1169,7 +1173,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, SrcRC == &AArch64::GPR64RegClass) { I.getOperand(1).setSubReg(AArch64::sub_32); } else { - DEBUG(dbgs() << "Unhandled mismatched classes in G_TRUNC/G_PTRTOINT\n"); + LLVM_DEBUG( + dbgs() << "Unhandled mismatched classes in G_TRUNC/G_PTRTOINT\n"); return false; } @@ -1192,26 +1197,28 @@ bool AArch64InstructionSelector::select(MachineInstr &I, const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI); if (RBDst.getID() != AArch64::GPRRegBankID) { - DEBUG(dbgs() << "G_ANYEXT on bank: " << RBDst << ", expected: GPR\n"); + LLVM_DEBUG(dbgs() << "G_ANYEXT on bank: " << RBDst + << ", expected: GPR\n"); return false; } const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI); if (RBSrc.getID() != AArch64::GPRRegBankID) { - DEBUG(dbgs() << "G_ANYEXT on bank: " << RBSrc << ", expected: GPR\n"); + LLVM_DEBUG(dbgs() << "G_ANYEXT on bank: " << RBSrc + << ", expected: GPR\n"); return false; } const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); if (DstSize == 0) { - DEBUG(dbgs() << "G_ANYEXT operand has no size, not a gvreg?\n"); + LLVM_DEBUG(dbgs() << "G_ANYEXT operand has no size, not a gvreg?\n"); return false; } if (DstSize != 64 && DstSize > 32) { - DEBUG(dbgs() << "G_ANYEXT to size: " << DstSize - << ", expected: 32 or 64\n"); + LLVM_DEBUG(dbgs() << "G_ANYEXT to size: " << DstSize + << ", expected: 32 or 64\n"); return false; } // At this point G_ANYEXT is just like a plain COPY, but we need @@ -1239,8 +1246,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); if (RB.getID() != AArch64::GPRRegBankID) { - DEBUG(dbgs() << TII.getName(I.getOpcode()) << " on bank: " << RB - << ", expected: GPR\n"); + LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode()) << " on bank: " << RB + << ", expected: GPR\n"); return false; } @@ -1248,8 +1255,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, if (DstTy == LLT::scalar(64)) { // FIXME: Can we avoid manually doing this? if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(Opcode) + << " operand\n"); return false; } @@ -1317,8 +1324,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, case TargetOpcode::G_SELECT: { if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) { - DEBUG(dbgs() << "G_SELECT cond has type: " << Ty - << ", expected: " << LLT::scalar(1) << '\n'); + LLVM_DEBUG(dbgs() << "G_SELECT cond has type: " << Ty + << ", expected: " << LLT::scalar(1) << '\n'); return false; } @@ -1356,8 +1363,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, } case TargetOpcode::G_ICMP: { if (Ty != LLT::scalar(32)) { - DEBUG(dbgs() << "G_ICMP result has type: " << Ty - << ", expected: " << LLT::scalar(32) << '\n'); + LLVM_DEBUG(dbgs() << "G_ICMP result has type: " << Ty + << ", expected: " << LLT::scalar(32) << '\n'); return false; } @@ -1403,8 +1410,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I, case TargetOpcode::G_FCMP: { if (Ty != LLT::scalar(32)) { - DEBUG(dbgs() << "G_FCMP result has type: " << Ty - << ", expected: " << LLT::scalar(32) << '\n'); + LLVM_DEBUG(dbgs() << "G_FCMP result has type: " << Ty + << ", expected: " << LLT::scalar(32) << '\n'); return false; } diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index 14b9e675176..4a19ecd6910 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -706,13 +706,13 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I, .setMIFlags(I->mergeFlagsWith(*MergeMI)); (void)MIB; - DEBUG(dbgs() << "Creating wider store. Replacing instructions:\n "); - DEBUG(I->print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(MergeMI->print(dbgs())); - DEBUG(dbgs() << " with instruction:\n "); - DEBUG(((MachineInstr *)MIB)->print(dbgs())); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Creating wider store. Replacing instructions:\n "); + LLVM_DEBUG(I->print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(MergeMI->print(dbgs())); + LLVM_DEBUG(dbgs() << " with instruction:\n "); + LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); // Erase the old instructions. I->eraseFromParent(); @@ -824,11 +824,12 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I, (void)MIB; - DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n "); - DEBUG(I->print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(Paired->print(dbgs())); - DEBUG(dbgs() << " with instruction:\n "); + LLVM_DEBUG( + dbgs() << "Creating pair load/store. Replacing instructions:\n "); + LLVM_DEBUG(I->print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(Paired->print(dbgs())); + LLVM_DEBUG(dbgs() << " with instruction:\n "); if (SExtIdx != -1) { // Generate the sign extension for the proper result of the ldp. // I.e., with X1, that would be: @@ -842,8 +843,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I, unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32); // Update the result of LDP to use the W instead of the X variant. DstMO.setReg(DstRegW); - DEBUG(((MachineInstr *)MIB)->print(dbgs())); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); // Make the machine verifier happy by providing a definition for // the X register. // Insert this definition right after the generated LDP, i.e., before @@ -860,12 +861,12 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I, .addImm(0) .addImm(31); (void)MIBSXTW; - DEBUG(dbgs() << " Extend operand:\n "); - DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs())); + LLVM_DEBUG(dbgs() << " Extend operand:\n "); + LLVM_DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs())); } else { - DEBUG(((MachineInstr *)MIB)->print(dbgs())); + LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs())); } - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\n"); // Erase the old instructions. I->eraseFromParent(); @@ -903,9 +904,9 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI, break; } } - DEBUG(dbgs() << "Remove load instruction:\n "); - DEBUG(LoadI->print(dbgs())); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Remove load instruction:\n "); + LLVM_DEBUG(LoadI->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); LoadI->eraseFromParent(); return NextI; } @@ -979,15 +980,15 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI, break; } - DEBUG(dbgs() << "Promoting load by replacing :\n "); - DEBUG(StoreI->print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(LoadI->print(dbgs())); - DEBUG(dbgs() << " with instructions:\n "); - DEBUG(StoreI->print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG((BitExtMI)->print(dbgs())); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Promoting load by replacing :\n "); + LLVM_DEBUG(StoreI->print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(LoadI->print(dbgs())); + LLVM_DEBUG(dbgs() << " with instructions:\n "); + LLVM_DEBUG(StoreI->print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG((BitExtMI)->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); // Erase the old instructions. LoadI->eraseFromParent(); @@ -1355,18 +1356,18 @@ AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I, if (IsPreIdx) { ++NumPreFolded; - DEBUG(dbgs() << "Creating pre-indexed load/store."); + LLVM_DEBUG(dbgs() << "Creating pre-indexed load/store."); } else { ++NumPostFolded; - DEBUG(dbgs() << "Creating post-indexed load/store."); + LLVM_DEBUG(dbgs() << "Creating post-indexed load/store."); } - DEBUG(dbgs() << " Replacing instructions:\n "); - DEBUG(I->print(dbgs())); - DEBUG(dbgs() << " "); - DEBUG(Update->print(dbgs())); - DEBUG(dbgs() << " with instruction:\n "); - DEBUG(((MachineInstr *)MIB)->print(dbgs())); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << " Replacing instructions:\n "); + LLVM_DEBUG(I->print(dbgs())); + LLVM_DEBUG(dbgs() << " "); + LLVM_DEBUG(Update->print(dbgs())); + LLVM_DEBUG(dbgs() << " with instruction:\n "); + LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); // Erase the old instructions for the block. I->eraseFromParent(); diff --git a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp index ee6703aed1e..ccf64657529 100644 --- a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp +++ b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp @@ -164,10 +164,10 @@ bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, LiveIntervals &LIs = G.getMetadata().LIS; if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) { - DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd) - << '\n'); - DEBUG(dbgs() << "Ra is a physical reg:" << TRI->isPhysicalRegister(Ra) - << '\n'); + LLVM_DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd) + << '\n'); + LLVM_DEBUG(dbgs() << "Ra is a physical reg:" << TRI->isPhysicalRegister(Ra) + << '\n'); return false; } @@ -247,14 +247,14 @@ void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, // Do some Chain management if (Chains.count(Ra)) { if (Rd != Ra) { - DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) << " to " - << printReg(Rd, TRI) << '\n';); + LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) + << " to " << printReg(Rd, TRI) << '\n';); Chains.remove(Ra); Chains.insert(Rd); } } else { - DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) - << '\n';); + LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) + << '\n';); Chains.insert(Rd); } @@ -279,7 +279,7 @@ void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, assert(edge != G.invalidEdgeId() && "PBQP error ! The edge should exist !"); - DEBUG(dbgs() << "Refining constraint !\n";); + LLVM_DEBUG(dbgs() << "Refining constraint !\n";); if (G.getEdgeNode1Id(edge) == node2) { std::swap(node1, node2); @@ -329,7 +329,7 @@ void A57ChainingConstraint::apply(PBQPRAGraph &G) { LiveIntervals &LIs = G.getMetadata().LIS; TRI = MF.getSubtarget().getRegisterInfo(); - DEBUG(MF.dump()); + LLVM_DEBUG(MF.dump()); for (const auto &MBB: MF) { Chains.clear(); // FIXME: really needed ? Could not work at MF level ? @@ -340,8 +340,8 @@ void A57ChainingConstraint::apply(PBQPRAGraph &G) { for (auto r : Chains) { SmallVector<unsigned, 8> toDel; if(regJustKilledBefore(LIs, r, MI)) { - DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; - MI.print(dbgs());); + LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; + MI.print(dbgs());); toDel.push_back(r); } diff --git a/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp b/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp index a8dc6e74ef6..01d8a35bbc2 100644 --- a/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp +++ b/llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp @@ -119,7 +119,7 @@ public: /// Iterate over the functions and promote the interesting constants into /// global variables with module scope. bool runOnModule(Module &M) override { - DEBUG(dbgs() << getPassName() << '\n'); + LLVM_DEBUG(dbgs() << getPassName() << '\n'); if (skipModule(M)) return false; bool Changed = false; @@ -380,9 +380,9 @@ bool AArch64PromoteConstant::isDominated(Instruction *NewPt, Instruction *User, (IPI.first->getParent() != NewPt->getParent() && DT.dominates(IPI.first->getParent(), NewPt->getParent()))) { // No need to insert this point. Just record the dominated use. - DEBUG(dbgs() << "Insertion point dominated by:\n"); - DEBUG(IPI.first->print(dbgs())); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Insertion point dominated by:\n"); + LLVM_DEBUG(IPI.first->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); IPI.second.emplace_back(User, OpNo); return true; } @@ -408,9 +408,9 @@ bool AArch64PromoteConstant::tryAndMerge(Instruction *NewPt, Instruction *User, // Instructions are in the same block. // By construction, NewPt is dominating the other. // Indeed, isDominated returned false with the exact same arguments. - DEBUG(dbgs() << "Merge insertion point with:\n"); - DEBUG(IPI->first->print(dbgs())); - DEBUG(dbgs() << "\nat considered insertion point.\n"); + LLVM_DEBUG(dbgs() << "Merge insertion point with:\n"); + LLVM_DEBUG(IPI->first->print(dbgs())); + LLVM_DEBUG(dbgs() << "\nat considered insertion point.\n"); appendAndTransferDominatedUses(NewPt, User, OpNo, IPI, InsertPts); return true; } @@ -430,11 +430,11 @@ bool AArch64PromoteConstant::tryAndMerge(Instruction *NewPt, Instruction *User, } // else, CommonDominator is the block of NewBB, hence NewBB is the last // possible insertion point in that block. - DEBUG(dbgs() << "Merge insertion point with:\n"); - DEBUG(IPI->first->print(dbgs())); - DEBUG(dbgs() << '\n'); - DEBUG(NewPt->print(dbgs())); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Merge insertion point with:\n"); + LLVM_DEBUG(IPI->first->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); + LLVM_DEBUG(NewPt->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); appendAndTransferDominatedUses(NewPt, User, OpNo, IPI, InsertPts); return true; } @@ -443,15 +443,15 @@ bool AArch64PromoteConstant::tryAndMerge(Instruction *NewPt, Instruction *User, void AArch64PromoteConstant::computeInsertionPoint( Instruction *User, unsigned OpNo, InsertionPoints &InsertPts) { - DEBUG(dbgs() << "Considered use, opidx " << OpNo << ":\n"); - DEBUG(User->print(dbgs())); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Considered use, opidx " << OpNo << ":\n"); + LLVM_DEBUG(User->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); Instruction *InsertionPoint = findInsertionPoint(*User, OpNo); - DEBUG(dbgs() << "Considered insertion point:\n"); - DEBUG(InsertionPoint->print(dbgs())); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Considered insertion point:\n"); + LLVM_DEBUG(InsertionPoint->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); if (isDominated(InsertionPoint, User, OpNo, InsertPts)) return; @@ -460,7 +460,7 @@ void AArch64PromoteConstant::computeInsertionPoint( if (tryAndMerge(InsertionPoint, User, OpNo, InsertPts)) return; - DEBUG(dbgs() << "Keep considered insertion point\n"); + LLVM_DEBUG(dbgs() << "Keep considered insertion point\n"); // It is definitely useful by its own InsertPts[InsertionPoint].emplace_back(User, OpNo); @@ -476,9 +476,9 @@ static void ensurePromotedGV(Function &F, Constant &C, *F.getParent(), C.getType(), true, GlobalValue::InternalLinkage, nullptr, "_PromotedConst", nullptr, GlobalVariable::NotThreadLocal); PC.GV->setInitializer(&C); - DEBUG(dbgs() << "Global replacement: "); - DEBUG(PC.GV->print(dbgs())); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Global replacement: "); + LLVM_DEBUG(PC.GV->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); ++NumPromoted; } @@ -495,10 +495,10 @@ void AArch64PromoteConstant::insertDefinitions(Function &F, // Create the load of the global variable. IRBuilder<> Builder(IPI.first); LoadInst *LoadedCst = Builder.CreateLoad(&PromotedGV); - DEBUG(dbgs() << "**********\n"); - DEBUG(dbgs() << "New def: "); - DEBUG(LoadedCst->print(dbgs())); - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "**********\n"); + LLVM_DEBUG(dbgs() << "New def: "); + LLVM_DEBUG(LoadedCst->print(dbgs())); + LLVM_DEBUG(dbgs() << '\n'); // Update the dominated uses. for (auto Use : IPI.second) { @@ -507,11 +507,11 @@ void AArch64PromoteConstant::insertDefinitions(Function &F, findInsertionPoint(*Use.first, Use.second)) && "Inserted definition does not dominate all its uses!"); #endif - DEBUG({ - dbgs() << "Use to update " << Use.second << ":"; - Use.first->print(dbgs()); - dbgs() << '\n'; - }); + LLVM_DEBUG({ + dbgs() << "Use to update " << Use.second << ":"; + Use.first->print(dbgs()); + dbgs() << '\n'; + }); Use.first->setOperand(Use.second, LoadedCst); ++NumPromotedUses; } @@ -523,7 +523,7 @@ void AArch64PromoteConstant::promoteConstants( PromotionCacheTy &PromotionCache) { // Promote the constants. for (auto U = Updates.begin(), E = Updates.end(); U != E;) { - DEBUG(dbgs() << "** Compute insertion points **\n"); + LLVM_DEBUG(dbgs() << "** Compute insertion points **\n"); auto First = U; Constant *C = First->C; InsertionPoints InsertPts; diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index e5822b11432..fac9ec3e74c 100644 --- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -427,9 +427,9 @@ bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) { } if (IsCopy) - DEBUG(dbgs() << "Remove redundant Copy : " << *MI); + LLVM_DEBUG(dbgs() << "Remove redundant Copy : " << *MI); else - DEBUG(dbgs() << "Remove redundant Move : " << *MI); + LLVM_DEBUG(dbgs() << "Remove redundant Move : " << *MI); MI->eraseFromParent(); Changed = true; @@ -473,8 +473,8 @@ bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) { // Clear kills in the range where changes were made. This is conservative, // but should be okay since kill markers are being phased out. - DEBUG(dbgs() << "Clearing kill flags.\n\tFirstUse: " << *FirstUse - << "\tLastChange: " << *LastChange); + LLVM_DEBUG(dbgs() << "Clearing kill flags.\n\tFirstUse: " << *FirstUse + << "\tLastChange: " << *LastChange); for (MachineInstr &MMI : make_range(FirstUse, PredMBB->end())) MMI.clearKillInfo(); for (MachineInstr &MMI : make_range(MBB->begin(), LastChange)) diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp index 2f7a597f3bf..fc7b5984fe3 100644 --- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp +++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp @@ -91,9 +91,9 @@ bool AArch64StorePairSuppress::shouldAddSTPToBlock(const MachineBasicBlock *BB) if (SCDesc->isValid() && !SCDesc->isVariant()) { unsigned ResLenWithSTP = BBTrace.getResourceLength(None, SCDesc); if (ResLenWithSTP > ResLength) { - DEBUG(dbgs() << " Suppress STP in BB: " << BB->getNumber() - << " resources " << ResLength << " -> " << ResLenWithSTP - << "\n"); + LLVM_DEBUG(dbgs() << " Suppress STP in BB: " << BB->getNumber() + << " resources " << ResLength << " -> " << ResLenWithSTP + << "\n"); return false; } } @@ -131,10 +131,10 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) { Traces = &getAnalysis<MachineTraceMetrics>(); MinInstr = nullptr; - DEBUG(dbgs() << "*** " << getPassName() << ": " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << MF.getName() << '\n'); if (!SchedModel.hasInstrSchedModel()) { - DEBUG(dbgs() << " Skipping pass: no machine model present.\n"); + LLVM_DEBUG(dbgs() << " Skipping pass: no machine model present.\n"); return false; } @@ -156,7 +156,7 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) { if (!SuppressSTP && shouldAddSTPToBlock(MI.getParent())) break; // Otherwise, continue unpairing the stores in this block. - DEBUG(dbgs() << "Unpairing store " << MI << "\n"); + LLVM_DEBUG(dbgs() << "Unpairing store " << MI << "\n"); SuppressSTP = true; TII->suppressLdStPair(MI); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 098272dc2e2..7eb4c1c9667 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -728,14 +728,14 @@ getFalkorUnrollingPreferences(Loop *L, ScalarEvolution &SE, }; int StridedLoads = countStridedLoads(L, SE); - DEBUG(dbgs() << "falkor-hwpf: detected " << StridedLoads - << " strided loads\n"); + LLVM_DEBUG(dbgs() << "falkor-hwpf: detected " << StridedLoads + << " strided loads\n"); // Pick the largest power of 2 unroll count that won't result in too many // strided loads. if (StridedLoads) { UP.MaxCount = 1 << Log2_32(MaxStridedLoads / StridedLoads); - DEBUG(dbgs() << "falkor-hwpf: setting unroll MaxCount to " << UP.MaxCount - << '\n'); + LLVM_DEBUG(dbgs() << "falkor-hwpf: setting unroll MaxCount to " + << UP.MaxCount << '\n'); } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp index ca77795ce10..35dd9eb0a47 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInline.cpp @@ -161,8 +161,8 @@ static bool isWrapperOnlyCall(CallSite CS) { return false; } if (isa<ReturnInst>(*std::next(I->getIterator()))) { - DEBUG(dbgs() << " Wrapper only call detected: " - << Callee->getName() << '\n'); + LLVM_DEBUG(dbgs() << " Wrapper only call detected: " + << Callee->getName() << '\n'); return true; } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp index dd45ced6ecc..7a7ed7a4f06 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp @@ -765,8 +765,7 @@ bool AMDGPULibCalls::TDOFold(CallInst *CI, const FuncInfo &FInfo) { ArrayRef<double> tmp(DVal); nval = ConstantDataVector::get(context, tmp); } - DEBUG(errs() << "AMDIC: " << *CI - << " ---> " << *nval << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *nval << "\n"); replaceCall(nval); return true; } @@ -776,8 +775,7 @@ bool AMDGPULibCalls::TDOFold(CallInst *CI, const FuncInfo &FInfo) { for (int i = 0; i < sz; ++i) { if (CF->isExactlyValue(ftbl[i].input)) { Value *nval = ConstantFP::get(CF->getType(), ftbl[i].result); - DEBUG(errs() << "AMDIC: " << *CI - << " ---> " << *nval << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *nval << "\n"); replaceCall(nval); return true; } @@ -798,11 +796,11 @@ bool AMDGPULibCalls::replaceWithNative(CallInst *CI, const FuncInfo &FInfo) { AMDGPULibFunc nf = FInfo; nf.setPrefix(AMDGPULibFunc::NATIVE); if (Constant *FPExpr = getFunction(M, nf)) { - DEBUG(dbgs() << "AMDIC: " << *CI << " ---> "); + LLVM_DEBUG(dbgs() << "AMDIC: " << *CI << " ---> "); CI->setCalledFunction(FPExpr); - DEBUG(dbgs() << *CI << '\n'); + LLVM_DEBUG(dbgs() << *CI << '\n'); return true; } @@ -820,8 +818,7 @@ bool AMDGPULibCalls::fold_recip(CallInst *CI, IRBuilder<> &B, Value *nval = B.CreateFDiv(ConstantFP::get(CF->getType(), 1.0), opr0, "recip2div"); - DEBUG(errs() << "AMDIC: " << *CI - << " ---> " << *nval << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *nval << "\n"); replaceCall(nval); return true; } @@ -899,7 +896,7 @@ bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B, if ((CF && CF->isZero()) || (CINT && ci_opr1 == 0) || CZero) { // pow/powr/pown(x, 0) == 1 - DEBUG(errs() << "AMDIC: " << *CI << " ---> 1\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> 1\n"); Constant *cnval = ConstantFP::get(eltType, 1.0); if (getVecSize(FInfo) > 1) { cnval = ConstantDataVector::getSplat(getVecSize(FInfo), cnval); @@ -909,23 +906,21 @@ bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B, } if ((CF && CF->isExactlyValue(1.0)) || (CINT && ci_opr1 == 1)) { // pow/powr/pown(x, 1.0) = x - DEBUG(errs() << "AMDIC: " << *CI - << " ---> " << *opr0 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr0 << "\n"); replaceCall(opr0); return true; } if ((CF && CF->isExactlyValue(2.0)) || (CINT && ci_opr1 == 2)) { // pow/powr/pown(x, 2.0) = x*x - DEBUG(errs() << "AMDIC: " << *CI - << " ---> " << *opr0 << " * " << *opr0 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr0 << " * " << *opr0 + << "\n"); Value *nval = B.CreateFMul(opr0, opr0, "__pow2"); replaceCall(nval); return true; } if ((CF && CF->isExactlyValue(-1.0)) || (CINT && ci_opr1 == -1)) { // pow/powr/pown(x, -1.0) = 1.0/x - DEBUG(errs() << "AMDIC: " << *CI - << " ---> 1 / " << *opr0 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> 1 / " << *opr0 << "\n"); Constant *cnval = ConstantFP::get(eltType, 1.0); if (getVecSize(FInfo) > 1) { cnval = ConstantDataVector::getSplat(getVecSize(FInfo), cnval); @@ -942,8 +937,8 @@ bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B, if (Constant *FPExpr = getFunction(M, AMDGPULibFunc(issqrt ? AMDGPULibFunc::EI_SQRT : AMDGPULibFunc::EI_RSQRT, FInfo))) { - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << FInfo.getName().c_str() << "(" << *opr0 << ")\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " + << FInfo.getName().c_str() << "(" << *opr0 << ")\n"); Value *nval = CreateCallEx(B,FPExpr, opr0, issqrt ? "__pow2sqrt" : "__pow2rsqrt"); replaceCall(nval); @@ -999,8 +994,9 @@ bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B, } nval = B.CreateFDiv(cnval, nval, "__1powprod"); } - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << ((ci_opr1 < 0) ? "1/prod(" : "prod(") << *opr0 << ")\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " + << ((ci_opr1 < 0) ? "1/prod(" : "prod(") << *opr0 + << ")\n"); replaceCall(nval); return true; } @@ -1137,8 +1133,8 @@ bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B, nval = B.CreateBitCast(nval, opr0->getType()); } - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << "exp2(" << *opr1 << " * log2(" << *opr0 << "))\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " + << "exp2(" << *opr1 << " * log2(" << *opr0 << "))\n"); replaceCall(nval); return true; @@ -1155,8 +1151,7 @@ bool AMDGPULibCalls::fold_rootn(CallInst *CI, IRBuilder<> &B, } int ci_opr1 = (int)CINT->getSExtValue(); if (ci_opr1 == 1) { // rootn(x, 1) = x - DEBUG(errs() << "AMDIC: " << *CI - << " ---> " << *opr0 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr0 << "\n"); replaceCall(opr0); return true; } @@ -1166,7 +1161,7 @@ bool AMDGPULibCalls::fold_rootn(CallInst *CI, IRBuilder<> &B, Module *M = CI->getModule(); if (Constant *FPExpr = getFunction(M, AMDGPULibFunc(AMDGPULibFunc::EI_SQRT, FInfo))) { - DEBUG(errs() << "AMDIC: " << *CI << " ---> sqrt(" << *opr0 << ")\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> sqrt(" << *opr0 << ")\n"); Value *nval = CreateCallEx(B,FPExpr, opr0, "__rootn2sqrt"); replaceCall(nval); return true; @@ -1175,13 +1170,13 @@ bool AMDGPULibCalls::fold_rootn(CallInst *CI, IRBuilder<> &B, Module *M = CI->getModule(); if (Constant *FPExpr = getFunction(M, AMDGPULibFunc(AMDGPULibFunc::EI_CBRT, FInfo))) { - DEBUG(errs() << "AMDIC: " << *CI << " ---> cbrt(" << *opr0 << ")\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> cbrt(" << *opr0 << ")\n"); Value *nval = CreateCallEx(B,FPExpr, opr0, "__rootn2cbrt"); replaceCall(nval); return true; } } else if (ci_opr1 == -1) { // rootn(x, -1) = 1.0/x - DEBUG(errs() << "AMDIC: " << *CI << " ---> 1.0 / " << *opr0 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> 1.0 / " << *opr0 << "\n"); Value *nval = B.CreateFDiv(ConstantFP::get(opr0->getType(), 1.0), opr0, "__rootn2div"); @@ -1193,7 +1188,8 @@ bool AMDGPULibCalls::fold_rootn(CallInst *CI, IRBuilder<> &B, Module *M = CI->getModule(); if (Constant *FPExpr = getFunction(M, AMDGPULibFunc(AMDGPULibFunc::EI_RSQRT, FInfo))) { - DEBUG(errs() << "AMDIC: " << *CI << " ---> rsqrt(" << *opr0 << ")\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> rsqrt(" << *opr0 + << ")\n"); Value *nval = CreateCallEx(B,FPExpr, opr0, "__rootn2rsqrt"); replaceCall(nval); return true; @@ -1212,22 +1208,22 @@ bool AMDGPULibCalls::fold_fma_mad(CallInst *CI, IRBuilder<> &B, ConstantFP *CF1 = dyn_cast<ConstantFP>(opr1); if ((CF0 && CF0->isZero()) || (CF1 && CF1->isZero())) { // fma/mad(a, b, c) = c if a=0 || b=0 - DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr2 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr2 << "\n"); replaceCall(opr2); return true; } if (CF0 && CF0->isExactlyValue(1.0f)) { // fma/mad(a, b, c) = b+c if a=1 - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << *opr1 << " + " << *opr2 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr1 << " + " << *opr2 + << "\n"); Value *nval = B.CreateFAdd(opr1, opr2, "fmaadd"); replaceCall(nval); return true; } if (CF1 && CF1->isExactlyValue(1.0f)) { // fma/mad(a, b, c) = a+c if b=1 - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << *opr0 << " + " << *opr2 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr0 << " + " << *opr2 + << "\n"); Value *nval = B.CreateFAdd(opr0, opr2, "fmaadd"); replaceCall(nval); return true; @@ -1235,8 +1231,8 @@ bool AMDGPULibCalls::fold_fma_mad(CallInst *CI, IRBuilder<> &B, if (ConstantFP *CF = dyn_cast<ConstantFP>(opr2)) { if (CF->isZero()) { // fma/mad(a, b, c) = a*b if c=0 - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << *opr0 << " * " << *opr1 << "\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " << *opr0 << " * " + << *opr1 << "\n"); Value *nval = B.CreateFMul(opr0, opr1, "fmamul"); replaceCall(nval); return true; @@ -1263,8 +1259,8 @@ bool AMDGPULibCalls::fold_sqrt(CallInst *CI, IRBuilder<> &B, if (Constant *FPExpr = getNativeFunction( CI->getModule(), AMDGPULibFunc(AMDGPULibFunc::EI_SQRT, FInfo))) { Value *opr0 = CI->getArgOperand(0); - DEBUG(errs() << "AMDIC: " << *CI << " ---> " - << "sqrt(" << *opr0 << ")\n"); + LLVM_DEBUG(errs() << "AMDIC: " << *CI << " ---> " + << "sqrt(" << *opr0 << ")\n"); Value *nval = CreateCallEx(B,FPExpr, opr0, "__sqrt"); replaceCall(nval); return true; @@ -1355,8 +1351,8 @@ bool AMDGPULibCalls::fold_sincos(CallInst *CI, IRBuilder<> &B, P = B.CreateAddrSpaceCast(Alloc, PTy); CallInst *Call = CreateCallEx2(B, Fsincos, UI->getArgOperand(0), P); - DEBUG(errs() << "AMDIC: fold_sincos (" << *CI << ", " << *UI - << ") with " << *Call << "\n"); + LLVM_DEBUG(errs() << "AMDIC: fold_sincos (" << *CI << ", " << *UI << ") with " + << *Call << "\n"); if (!isSin) { // CI->cos, UI->sin B.SetInsertPoint(&*ItOld); @@ -1719,9 +1715,8 @@ bool AMDGPUSimplifyLibCalls::runOnFunction(Function &F) { bool Changed = false; auto AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); - DEBUG(dbgs() << "AMDIC: process function "; - F.printAsOperand(dbgs(), false, F.getParent()); - dbgs() << '\n';); + LLVM_DEBUG(dbgs() << "AMDIC: process function "; + F.printAsOperand(dbgs(), false, F.getParent()); dbgs() << '\n';); if (!EnablePreLink) Changed |= setFastFlags(F, Options); @@ -1737,8 +1732,8 @@ bool AMDGPUSimplifyLibCalls::runOnFunction(Function &F) { Function *Callee = CI->getCalledFunction(); if (Callee == 0) continue; - DEBUG(dbgs() << "AMDIC: try folding " << *CI << "\n"; - dbgs().flush()); + LLVM_DEBUG(dbgs() << "AMDIC: try folding " << *CI << "\n"; + dbgs().flush()); if(Simplifier.fold(CI, AA)) Changed = true; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp index b1d61fd3ede..612777981f9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -659,7 +659,7 @@ RegionMRT *MRT::buildMRT(MachineFunction &MF, continue; } - DEBUG(dbgs() << "Visiting " << printMBBReference(*MBB) << "\n"); + LLVM_DEBUG(dbgs() << "Visiting " << printMBBReference(*MBB) << "\n"); MBBMRT *NewMBB = new MBBMRT(MBB); MachineRegion *Region = RegionInfo->getRegionFor(MBB); @@ -696,18 +696,19 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { if (TRI->isVirtualRegister(Reg)) { - DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) + << "\n"); // If this is a source register to a PHI we are chaining, it // must be live out. if (PHIInfo.isSource(Reg)) { - DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { // If this is live out of the MBB for (auto &UI : MRI->use_operands(Reg)) { if (UI.getParent()->getParent() != MBB) { - DEBUG(dbgs() << "Add LiveOut (MBB " << printMBBReference(*MBB) - << "): " << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Add LiveOut (MBB " << printMBBReference(*MBB) + << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { // If the use is in the same MBB we have to make sure @@ -718,8 +719,8 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, MIE = UseInstr->getParent()->instr_end(); MII != MIE; ++MII) { if ((&(*MII)) == DefInstr) { - DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) + << "\n"); addLiveOut(Reg); } } @@ -735,11 +736,12 @@ void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { if (TRI->isVirtualRegister(Reg)) { - DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) + << "\n"); for (auto &UI : MRI->use_operands(Reg)) { if (!Region->contains(UI.getParent()->getParent())) { - DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region - << "): " << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region + << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } } @@ -750,8 +752,8 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { - DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB) - << ")-\n"); + LLVM_DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB) + << ")-\n"); for (auto &II : *MBB) { for (auto &RI : II.defs()) { storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo); @@ -775,9 +777,10 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, for (int i = 0; i < numPreds; ++i) { if (getPHIPred(PHI, i) == MBB) { unsigned PHIReg = getPHISourceReg(PHI, i); - DEBUG(dbgs() << "Add LiveOut (PhiSource " << printMBBReference(*MBB) - << " -> " << printMBBReference(*(*SI)) - << "): " << printReg(PHIReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() + << "Add LiveOut (PhiSource " << printMBBReference(*MBB) + << " -> " << printMBBReference(*(*SI)) + << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } } @@ -785,7 +788,7 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, } } - DEBUG(dbgs() << "-Store Live Outs Endn-\n"); + LLVM_DEBUG(dbgs() << "-Store Live Outs Endn-\n"); } void LinearizedRegion::storeMBBLiveOuts(MachineBasicBlock *MBB, @@ -845,8 +848,8 @@ void LinearizedRegion::storeLiveOuts(RegionMRT *Region, for (int i = 0; i < numPreds; ++i) { if (Region->contains(getPHIPred(PHI, i))) { unsigned PHIReg = getPHISourceReg(PHI, i); - DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region - << "): " << printReg(PHIReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region + << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } } @@ -910,20 +913,21 @@ void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, bool IncludeLoopPHI) { assert(Register != NewRegister && "Cannot replace a reg with itself"); - DEBUG(dbgs() << "Pepareing to replace register (region): " - << printReg(Register, MRI->getTargetRegisterInfo()) << " with " - << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); + LLVM_DEBUG( + dbgs() << "Pepareing to replace register (region): " + << printReg(Register, MRI->getTargetRegisterInfo()) << " with " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n"); // If we are replacing outside, we also need to update the LiveOuts if (ReplaceOutside && (isLiveOut(Register) || this->getParent()->isLiveOut(Register))) { LinearizedRegion *Current = this; while (Current != nullptr && Current->getEntry() != nullptr) { - DEBUG(dbgs() << "Region before register replace\n"); - DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo())); + LLVM_DEBUG(dbgs() << "Region before register replace\n"); + LLVM_DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo())); Current->replaceLiveOut(Register, NewRegister); - DEBUG(dbgs() << "Region after register replace\n"); - DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo())); + LLVM_DEBUG(dbgs() << "Region after register replace\n"); + LLVM_DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo())); Current = Current->getParent(); } } @@ -947,16 +951,16 @@ void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister, if (ShouldReplace) { if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { - DEBUG(dbgs() << "Trying to substitute physical register: " - << printReg(NewRegister, MRI->getTargetRegisterInfo()) - << "\n"); + LLVM_DEBUG(dbgs() << "Trying to substitute physical register: " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) + << "\n"); llvm_unreachable("Cannot substitute physical registers"); } else { - DEBUG(dbgs() << "Replacing register (region): " - << printReg(Register, MRI->getTargetRegisterInfo()) - << " with " - << printReg(NewRegister, MRI->getTargetRegisterInfo()) - << "\n"); + LLVM_DEBUG(dbgs() << "Replacing register (region): " + << printReg(Register, MRI->getTargetRegisterInfo()) + << " with " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) + << "\n"); O.setReg(NewRegister); } } @@ -1023,18 +1027,18 @@ void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) { if (hasNoDef(Reg, MRI)) continue; if (!MRI->hasOneDef(Reg)) { - DEBUG(this->getEntry()->getParent()->dump()); - DEBUG(dbgs() << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(this->getEntry()->getParent()->dump()); + LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << "\n"); } if (MRI->def_begin(Reg) == MRI->def_end()) { - DEBUG(dbgs() << "Register " - << printReg(Reg, MRI->getTargetRegisterInfo()) - << " has NO defs\n"); + LLVM_DEBUG(dbgs() << "Register " + << printReg(Reg, MRI->getTargetRegisterInfo()) + << " has NO defs\n"); } else if (!MRI->hasOneDef(Reg)) { - DEBUG(dbgs() << "Register " - << printReg(Reg, MRI->getTargetRegisterInfo()) - << " has multiple defs\n"); + LLVM_DEBUG(dbgs() << "Register " + << printReg(Reg, MRI->getTargetRegisterInfo()) + << " has multiple defs\n"); } assert(MRI->hasOneDef(Reg) && "Register has multiple definitions"); @@ -1042,8 +1046,8 @@ void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) { MachineOperand *UseOperand = &(RI); bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB; if (UseIsOutsideDefMBB && UseOperand->isKill()) { - DEBUG(dbgs() << "Removing kill flag on register: " - << printReg(Reg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Removing kill flag on register: " + << printReg(Reg, TRI) << "\n"); UseOperand->setIsKill(false); } } @@ -1416,8 +1420,8 @@ void AMDGPUMachineCFGStructurizer::extractKilledPHIs(MachineBasicBlock *MBB) { MachineInstr &Instr = *I; if (Instr.isPHI()) { unsigned PHIDestReg = getPHIDestReg(Instr); - DEBUG(dbgs() << "Extractking killed phi:\n"); - DEBUG(Instr.dump()); + LLVM_DEBUG(dbgs() << "Extractking killed phi:\n"); + LLVM_DEBUG(Instr.dump()); PHIs.insert(&Instr); PHIInfo.addDest(PHIDestReg, Instr.getDebugLoc()); storePHILinearizationInfoDest(PHIDestReg, Instr); @@ -1449,9 +1453,10 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, MachineBasicBlock *SourceMBB, SmallVector<unsigned, 2> &PHIIndices, unsigned *ReplaceReg) { - DEBUG(dbgs() << "Shrink PHI: "); - DEBUG(PHI.dump()); - DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); + LLVM_DEBUG(dbgs() << "Shrink PHI: "); + LLVM_DEBUG(PHI.dump()); + LLVM_DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI) + << " = PHI("); bool Replaced = false; unsigned NumInputs = getPHINumInputs(PHI); @@ -1481,8 +1486,8 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, if (SourceMBB) { MIB.addReg(CombinedSourceReg); MIB.addMBB(SourceMBB); - DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " - << printMBBReference(*SourceMBB)); + LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " + << printMBBReference(*SourceMBB)); } for (unsigned i = 0; i < NumInputs; ++i) { @@ -1493,10 +1498,10 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " - << printMBBReference(*SourcePred)); + LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*SourcePred)); } - DEBUG(dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << ")\n"); } PHI.eraseFromParent(); return Replaced; @@ -1505,9 +1510,10 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, void AMDGPUMachineCFGStructurizer::replacePHI( MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *LastMerge, SmallVector<unsigned, 2> &PHIRegionIndices) { - DEBUG(dbgs() << "Replace PHI: "); - DEBUG(PHI.dump()); - DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); + LLVM_DEBUG(dbgs() << "Replace PHI: "); + LLVM_DEBUG(PHI.dump()); + LLVM_DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI) + << " = PHI("); bool HasExternalEdge = false; unsigned NumInputs = getPHINumInputs(PHI); @@ -1524,8 +1530,8 @@ void AMDGPUMachineCFGStructurizer::replacePHI( getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(LastMerge); - DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " - << printMBBReference(*LastMerge)); + LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " + << printMBBReference(*LastMerge)); for (unsigned i = 0; i < NumInputs; ++i) { if (isPHIRegionIndex(PHIRegionIndices, i)) { continue; @@ -1534,10 +1540,10 @@ void AMDGPUMachineCFGStructurizer::replacePHI( MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " - << printMBBReference(*SourcePred)); + LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*SourcePred)); } - DEBUG(dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << ")\n"); } else { replaceRegisterWith(getPHIDestReg(PHI), CombinedSourceReg); } @@ -1547,9 +1553,9 @@ void AMDGPUMachineCFGStructurizer::replacePHI( void AMDGPUMachineCFGStructurizer::replaceEntryPHI( MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *IfMBB, SmallVector<unsigned, 2> &PHIRegionIndices) { - DEBUG(dbgs() << "Replace entry PHI: "); - DEBUG(PHI.dump()); - DEBUG(dbgs() << " with "); + LLVM_DEBUG(dbgs() << "Replace entry PHI: "); + LLVM_DEBUG(PHI.dump()); + LLVM_DEBUG(dbgs() << " with "); unsigned NumInputs = getPHINumInputs(PHI); unsigned NumNonRegionInputs = NumInputs; @@ -1562,18 +1568,19 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI( if (NumNonRegionInputs == 0) { auto DestReg = getPHIDestReg(PHI); replaceRegisterWith(DestReg, CombinedSourceReg); - DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI) + << "\n"); PHI.eraseFromParent(); } else { - DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); + LLVM_DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << " = PHI("); MachineBasicBlock *MBB = PHI.getParent(); MachineInstrBuilder MIB = BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(IfMBB); - DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " - << printMBBReference(*IfMBB)); + LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " + << printMBBReference(*IfMBB)); unsigned NumInputs = getPHINumInputs(PHI); for (unsigned i = 0; i < NumInputs; ++i) { if (isPHIRegionIndex(PHIRegionIndices, i)) { @@ -1583,10 +1590,10 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI( MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " - << printMBBReference(*SourcePred)); + LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*SourcePred)); } - DEBUG(dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << ")\n"); PHI.eraseFromParent(); } } @@ -1608,8 +1615,9 @@ void AMDGPUMachineCFGStructurizer::replaceLiveOutRegs( } } - DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is " - << (IsDead ? "dead" : "alive") << " after PHI replace\n"); + LLVM_DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is " + << (IsDead ? "dead" : "alive") + << " after PHI replace\n"); if (IsDead) { LRegion->removeLiveOut(Reg); } @@ -1683,8 +1691,8 @@ void AMDGPUMachineCFGStructurizer::rewriteRegionEntryPHIs(LinearizedRegion *Regi void AMDGPUMachineCFGStructurizer::insertUnconditionalBranch(MachineBasicBlock *MBB, MachineBasicBlock *Dest, const DebugLoc &DL) { - DEBUG(dbgs() << "Inserting unconditional branch: " << MBB->getNumber() - << " -> " << Dest->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Inserting unconditional branch: " << MBB->getNumber() + << " -> " << Dest->getNumber() << "\n"); MachineBasicBlock::instr_iterator Terminator = MBB->getFirstInstrTerminator(); bool HasTerminator = Terminator != MBB->instr_end(); if (HasTerminator) { @@ -1733,7 +1741,8 @@ AMDGPUMachineCFGStructurizer::createLinearizedExitBlock(RegionMRT *Region) { MF->insert(ExitIter, LastMerge); LastMerge->addSuccessor(Exit); insertUnconditionalBranch(LastMerge, Exit); - DEBUG(dbgs() << "Created exit block: " << LastMerge->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Created exit block: " << LastMerge->getNumber() + << "\n"); } return LastMerge; } @@ -1749,11 +1758,12 @@ void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB, if (MergeBB->succ_begin() == MergeBB->succ_end()) { return; } - DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB) - << "): " << printReg(DestRegister, TRI) << " = PHI(" - << printReg(IfSourceRegister, TRI) << ", " - << printMBBReference(*IfBB) << printReg(CodeSourceRegister, TRI) - << ", " << printMBBReference(*CodeBB) << ")\n"); + LLVM_DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB) + << "): " << printReg(DestRegister, TRI) << " = PHI(" + << printReg(IfSourceRegister, TRI) << ", " + << printMBBReference(*IfBB) + << printReg(CodeSourceRegister, TRI) << ", " + << printMBBReference(*CodeBB) << ")\n"); const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin()); MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL, TII->get(TargetOpcode::PHI), DestRegister); @@ -1811,8 +1821,8 @@ static void removeExternalCFGEdges(MachineBasicBlock *StartMBB, for (auto SI : Succs) { std::pair<MachineBasicBlock *, MachineBasicBlock *> Edge = SI; - DEBUG(dbgs() << "Removing edge: " << printMBBReference(*Edge.first) - << " -> " << printMBBReference(*Edge.second) << "\n"); + LLVM_DEBUG(dbgs() << "Removing edge: " << printMBBReference(*Edge.first) + << " -> " << printMBBReference(*Edge.second) << "\n"); Edge.first->removeSuccessor(Edge.second); } } @@ -1845,13 +1855,13 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock( IfBB->addSuccessor(MergeBB); IfBB->addSuccessor(CodeBBStart); - DEBUG(dbgs() << "Created If block: " << IfBB->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Created If block: " << IfBB->getNumber() << "\n"); // Ensure that the MergeBB is a successor of the CodeEndBB. if (!CodeBBEnd->isSuccessor(MergeBB)) CodeBBEnd->addSuccessor(MergeBB); - DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart) << " through " - << printMBBReference(*CodeBBEnd) << "\n"); + LLVM_DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart) + << " through " << printMBBReference(*CodeBBEnd) << "\n"); // If we have a single predecessor we can find a reasonable debug location MachineBasicBlock *SinglePred = @@ -1936,16 +1946,18 @@ void AMDGPUMachineCFGStructurizer::rewriteCodeBBTerminator(MachineBasicBlock *Co MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) { if (MRI->def_begin(Reg) == MRI->def_end()) { - DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo()) - << " has NO defs\n"); + LLVM_DEBUG(dbgs() << "Register " + << printReg(Reg, MRI->getTargetRegisterInfo()) + << " has NO defs\n"); } else if (!MRI->hasOneDef(Reg)) { - DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo()) - << " has multiple defs\n"); - DEBUG(dbgs() << "DEFS BEGIN:\n"); + LLVM_DEBUG(dbgs() << "Register " + << printReg(Reg, MRI->getTargetRegisterInfo()) + << " has multiple defs\n"); + LLVM_DEBUG(dbgs() << "DEFS BEGIN:\n"); for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) { - DEBUG(DI->getParent()->dump()); + LLVM_DEBUG(DI->getParent()->dump()); } - DEBUG(dbgs() << "DEFS END\n"); + LLVM_DEBUG(dbgs() << "DEFS END\n"); } assert(MRI->hasOneDef(Reg) && "Register has multiple definitions"); @@ -1987,7 +1999,7 @@ void AMDGPUMachineCFGStructurizer::insertChainedPHI(MachineBasicBlock *IfBB, const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); unsigned NextDestReg = MRI->createVirtualRegister(RegClass); bool IsLastDef = PHIInfo.getNumSources(DestReg) == 1; - DEBUG(dbgs() << "Insert Chained PHI\n"); + LLVM_DEBUG(dbgs() << "Insert Chained PHI\n"); insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, DestReg, NextDestReg, SourceReg, IsLastDef); @@ -2023,16 +2035,16 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB, } for (auto LI : OldLiveOuts) { - DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI)); + LLVM_DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI)); if (!containsDef(CodeBB, InnerRegion, LI) || (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) { // If the register simly lives through the CodeBB, we don't have // to rewrite anything since the register is not defined in this // part of the code. - DEBUG(dbgs() << "- through"); + LLVM_DEBUG(dbgs() << "- through"); continue; } - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\n"); unsigned Reg = LI; if (/*!PHIInfo.isSource(Reg) &&*/ Reg != InnerRegion->getBBSelectRegOut()) { // If the register is live out, we do want to create a phi, @@ -2049,12 +2061,12 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB, unsigned IfSourceReg = MRI->createVirtualRegister(RegClass); // Create initializer, this value is never used, but is needed // to satisfy SSA. - DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n"); + LLVM_DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n"); TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(), IfSourceReg, 0); InnerRegion->replaceRegisterOutsideRegion(Reg, PHIDestReg, true, MRI); - DEBUG(dbgs() << "Insert Non-Chained Live out PHI\n"); + LLVM_DEBUG(dbgs() << "Insert Non-Chained Live out PHI\n"); insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, PHIDestReg, IfSourceReg, Reg, true); } @@ -2064,22 +2076,22 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB, // is a source block for a definition. SmallVector<unsigned, 4> Sources; if (PHIInfo.findSourcesFromMBB(CodeBB, Sources)) { - DEBUG(dbgs() << "Inserting PHI Live Out from " << printMBBReference(*CodeBB) - << "\n"); + LLVM_DEBUG(dbgs() << "Inserting PHI Live Out from " + << printMBBReference(*CodeBB) << "\n"); for (auto SI : Sources) { unsigned DestReg; PHIInfo.findDest(SI, CodeBB, DestReg); insertChainedPHI(IfBB, CodeBB, MergeBB, InnerRegion, DestReg, SI); } - DEBUG(dbgs() << "Insertion done.\n"); + LLVM_DEBUG(dbgs() << "Insertion done.\n"); } - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(PHIInfo.dump(MRI)); } void AMDGPUMachineCFGStructurizer::prunePHIInfo(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Before PHI Prune\n"); - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(dbgs() << "Before PHI Prune\n"); + LLVM_DEBUG(PHIInfo.dump(MRI)); SmallVector<std::tuple<unsigned, unsigned, MachineBasicBlock *>, 4> ElimiatedSources; for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE; @@ -2119,8 +2131,8 @@ void AMDGPUMachineCFGStructurizer::prunePHIInfo(MachineBasicBlock *MBB) { PHIInfo.removeSource(std::get<0>(SourceInfo), std::get<1>(SourceInfo), std::get<2>(SourceInfo)); } - DEBUG(dbgs() << "After PHI Prune\n"); - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(dbgs() << "After PHI Prune\n"); + LLVM_DEBUG(PHIInfo.dump(MRI)); } void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegion, @@ -2128,8 +2140,8 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio MachineBasicBlock *Entry = CurrentRegion->getEntry(); MachineBasicBlock *Exit = CurrentRegion->getExit(); - DEBUG(dbgs() << "RegionExit: " << Exit->getNumber() - << " Pred: " << (*(Entry->pred_begin()))->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "RegionExit: " << Exit->getNumber() << " Pred: " + << (*(Entry->pred_begin()))->getNumber() << "\n"); int NumSources = 0; auto SE = PHIInfo.sources_end(DestReg); @@ -2146,7 +2158,7 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio const DebugLoc &DL = Entry->findDebugLoc(Entry->begin()); MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL, TII->get(TargetOpcode::PHI), DestReg); - DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << " = PHI("); + LLVM_DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << " = PHI("); unsigned CurrentBackedgeReg = 0; @@ -2170,19 +2182,19 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio BackedgePHI.addReg(getPHISourceReg(*PHIDefInstr, 1)); BackedgePHI.addMBB((*SRI).second); CurrentBackedgeReg = NewBackedgeReg; - DEBUG(dbgs() << "Inserting backedge PHI: " - << printReg(NewBackedgeReg, TRI) << " = PHI(" - << printReg(CurrentBackedgeReg, TRI) << ", " - << printMBBReference(*getPHIPred(*PHIDefInstr, 0)) - << ", " - << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) - << ", " << printMBBReference(*(*SRI).second)); + LLVM_DEBUG(dbgs() + << "Inserting backedge PHI: " + << printReg(NewBackedgeReg, TRI) << " = PHI(" + << printReg(CurrentBackedgeReg, TRI) << ", " + << printMBBReference(*getPHIPred(*PHIDefInstr, 0)) << ", " + << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", " + << printMBBReference(*(*SRI).second)); } } else { MIB.addReg(SourceReg); MIB.addMBB((*SRI).second); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " - << printMBBReference(*(*SRI).second) << ", "); + LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*(*SRI).second) << ", "); } } @@ -2190,16 +2202,16 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio if (CurrentBackedgeReg != 0) { MIB.addReg(CurrentBackedgeReg); MIB.addMBB(Exit); - DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", " - << printMBBReference(*Exit) << ")\n"); + LLVM_DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", " + << printMBBReference(*Exit) << ")\n"); } else { - DEBUG(dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << ")\n"); } } } void AMDGPUMachineCFGStructurizer::createEntryPHIs(LinearizedRegion *CurrentRegion) { - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(PHIInfo.dump(MRI)); for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE; ++DRI) { @@ -2220,19 +2232,19 @@ void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register, MachineOperand &O = *I; ++I; if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) { - DEBUG(dbgs() << "Trying to substitute physical register: " - << printReg(NewRegister, MRI->getTargetRegisterInfo()) - << "\n"); + LLVM_DEBUG(dbgs() << "Trying to substitute physical register: " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) + << "\n"); llvm_unreachable("Cannot substitute physical registers"); // We don't handle physical registers, but if we need to // in the future This is how we do it: // O.substPhysReg(NewRegister, *TRI); } else { - DEBUG(dbgs() << "Replacing register: " - << printReg(Register, MRI->getTargetRegisterInfo()) - << " with " - << printReg(NewRegister, MRI->getTargetRegisterInfo()) - << "\n"); + LLVM_DEBUG(dbgs() << "Replacing register: " + << printReg(Register, MRI->getTargetRegisterInfo()) + << " with " + << printReg(NewRegister, MRI->getTargetRegisterInfo()) + << "\n"); O.setReg(NewRegister); } } @@ -2240,20 +2252,20 @@ void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register, getRegionMRT()->replaceLiveOutReg(Register, NewRegister); - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(PHIInfo.dump(MRI)); } void AMDGPUMachineCFGStructurizer::resolvePHIInfos(MachineBasicBlock *FunctionEntry) { - DEBUG(dbgs() << "Resolve PHI Infos\n"); - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(dbgs() << "Resolve PHI Infos\n"); + LLVM_DEBUG(PHIInfo.dump(MRI)); for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE; ++DRI) { unsigned DestReg = *DRI; - DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n"); auto SRI = PHIInfo.sources_begin(DestReg); unsigned SourceReg = (*SRI).first; - DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) - << " SourceReg: " << printReg(SourceReg, TRI) << "\n"); + LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) + << " SourceReg: " << printReg(SourceReg, TRI) << "\n"); assert(PHIInfo.sources_end(DestReg) == ++SRI && "More than one phi source in entry node"); @@ -2327,9 +2339,9 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion( MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); ArrayRef<MachineOperand> Cond(RegOp); - DEBUG(dbgs() << "RegionExitReg: "); - DEBUG(Cond[0].print(dbgs(), TRI)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "RegionExitReg: "); + LLVM_DEBUG(Cond[0].print(dbgs(), TRI)); + LLVM_DEBUG(dbgs() << "\n"); TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit, Cond, DebugLoc()); RegionExit->addSuccessor(CurrentRegion->getEntry()); @@ -2339,12 +2351,12 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion( LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo); InnerRegion.setParent(CurrentRegion); - DEBUG(dbgs() << "Insert BB Select PHI (BB)\n"); + LLVM_DEBUG(dbgs() << "Insert BB Select PHI (BB)\n"); insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn, CodeBBSelectReg); InnerRegion.addMBB(MergeBB); - DEBUG(InnerRegion.print(dbgs(), TRI)); + LLVM_DEBUG(InnerRegion.print(dbgs(), TRI)); rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion); extractKilledPHIs(CodeBB); if (IsRegionEntryBB) { @@ -2385,16 +2397,16 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion( CurrentRegion->getRegionMRT()->getEntry()->getNumber()); MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); ArrayRef<MachineOperand> Cond(RegOp); - DEBUG(dbgs() << "RegionExitReg: "); - DEBUG(Cond[0].print(dbgs(), TRI)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "RegionExitReg: "); + LLVM_DEBUG(Cond[0].print(dbgs(), TRI)); + LLVM_DEBUG(dbgs() << "\n"); TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit, Cond, DebugLoc()); RegionExit->addSuccessor(IfBB); } } CurrentRegion->addMBBs(InnerRegion); - DEBUG(dbgs() << "Insert BB Select PHI (region)\n"); + LLVM_DEBUG(dbgs() << "Insert BB Select PHI (region)\n"); insertMergePHI(IfBB, CodeExitBB, MergeBB, BBSelectRegOut, BBSelectRegIn, CodeBBSelectReg); @@ -2440,15 +2452,16 @@ void AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI, MachineInstrBuilder MIB = BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(), TII->get(TargetOpcode::PHI), NewDestReg); - DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI) << " = PHI("); + LLVM_DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI) + << " = PHI("); MIB.addReg(PHISource); MIB.addMBB(Entry); - DEBUG(dbgs() << printReg(PHISource, TRI) << ", " - << printMBBReference(*Entry)); + LLVM_DEBUG(dbgs() << printReg(PHISource, TRI) << ", " + << printMBBReference(*Entry)); MIB.addReg(RegionSourceReg); MIB.addMBB(RegionSourceMBB); - DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", " - << printMBBReference(*RegionSourceMBB) << ")\n"); + LLVM_DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", " + << printMBBReference(*RegionSourceMBB) << ")\n"); } void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry, @@ -2481,7 +2494,8 @@ AMDGPUMachineCFGStructurizer::splitExit(LinearizedRegion *LRegion) { LRegion->addMBB(NewExit); LRegion->setExit(NewExit); - DEBUG(dbgs() << "Created new exit block: " << NewExit->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Created new exit block: " << NewExit->getNumber() + << "\n"); // Replace any PHI Predecessors in the successor with NewExit for (auto &II : *Succ) { @@ -2529,9 +2543,9 @@ AMDGPUMachineCFGStructurizer::splitEntry(LinearizedRegion *LRegion) { MachineBasicBlock *EntrySucc = split(Entry->getFirstNonPHI()); MachineBasicBlock *Exit = LRegion->getExit(); - DEBUG(dbgs() << "Split " << printMBBReference(*Entry) << " to " - << printMBBReference(*Entry) << " -> " - << printMBBReference(*EntrySucc) << "\n"); + LLVM_DEBUG(dbgs() << "Split " << printMBBReference(*Entry) << " to " + << printMBBReference(*Entry) << " -> " + << printMBBReference(*EntrySucc) << "\n"); LRegion->addMBB(EntrySucc); // Make the backedge go to Entry Succ @@ -2622,21 +2636,21 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { rewriteRegionExitPHIs(Region, LastMerge, LRegion); removeOldExitPreds(Region); - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(PHIInfo.dump(MRI)); SetVector<MRT *> *Children = Region->getChildren(); - DEBUG(dbgs() << "===========If Region Start===============\n"); + LLVM_DEBUG(dbgs() << "===========If Region Start===============\n"); if (LRegion->getHasLoop()) { - DEBUG(dbgs() << "Has Backedge: Yes\n"); + LLVM_DEBUG(dbgs() << "Has Backedge: Yes\n"); } else { - DEBUG(dbgs() << "Has Backedge: No\n"); + LLVM_DEBUG(dbgs() << "Has Backedge: No\n"); } unsigned BBSelectRegIn; unsigned BBSelectRegOut; for (auto CI = Children->begin(), CE = Children->end(); CI != CE; ++CI) { - DEBUG(dbgs() << "CurrentRegion: \n"); - DEBUG(LRegion->print(dbgs(), TRI)); + LLVM_DEBUG(dbgs() << "CurrentRegion: \n"); + LLVM_DEBUG(LRegion->print(dbgs(), TRI)); auto CNI = CI; ++CNI; @@ -2650,9 +2664,9 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { // We found the block is the exit of an inner region, we need // to put it in the current linearized region. - DEBUG(dbgs() << "Linearizing region: "); - DEBUG(InnerLRegion->print(dbgs(), TRI)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Linearizing region: "); + LLVM_DEBUG(InnerLRegion->print(dbgs(), TRI)); + LLVM_DEBUG(dbgs() << "\n"); MachineBasicBlock *InnerEntry = InnerLRegion->getEntry(); if ((&(*(InnerEntry->getParent()->begin()))) == InnerEntry) { @@ -2670,10 +2684,10 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegIn = Child->getBBSelectRegIn(); - DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) - << "\n"); - DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) + << "\n"); + LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) + << "\n"); MachineBasicBlock *IfEnd = CurrentMerge; CurrentMerge = createIfRegion(CurrentMerge, InnerLRegion, LRegion, @@ -2682,7 +2696,7 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { TII->convertNonUniformIfRegion(CurrentMerge, IfEnd); } else { MachineBasicBlock *MBB = Child->getMBBMRT()->getMBB(); - DEBUG(dbgs() << "Linearizing block: " << MBB->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Linearizing block: " << MBB->getNumber() << "\n"); if (MBB == getSingleExitNode(*(MBB->getParent()))) { // If this is the exit block then we need to skip to the next. @@ -2694,10 +2708,10 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { BBSelectRegOut = Child->getBBSelectRegOut(); BBSelectRegIn = Child->getBBSelectRegIn(); - DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) - << "\n"); - DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI) + << "\n"); + LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI) + << "\n"); MachineBasicBlock *IfEnd = CurrentMerge; // This is a basic block that is not part of an inner region, we @@ -2708,7 +2722,7 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { TII->convertNonUniformIfRegion(CurrentMerge, IfEnd); } - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(PHIInfo.dump(MRI)); } } @@ -2729,7 +2743,7 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { NewInReg, Region->getEntry()->getNumber()); // Need to be careful about updating the registers inside the region. LRegion->replaceRegisterInsideRegion(InReg, InnerSelectReg, false, MRI); - DEBUG(dbgs() << "Loop BBSelect Merge PHI:\n"); + LLVM_DEBUG(dbgs() << "Loop BBSelect Merge PHI:\n"); insertMergePHI(LRegion->getEntry(), LRegion->getExit(), NewSucc, InnerSelectReg, NewInReg, LRegion->getRegionMRT()->getInnerOutputRegister()); @@ -2741,11 +2755,11 @@ bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) { TII->insertReturn(*LastMerge); } - DEBUG(Region->getEntry()->getParent()->dump()); - DEBUG(LRegion->print(dbgs(), TRI)); - DEBUG(PHIInfo.dump(MRI)); + LLVM_DEBUG(Region->getEntry()->getParent()->dump()); + LLVM_DEBUG(LRegion->print(dbgs(), TRI)); + LLVM_DEBUG(PHIInfo.dump(MRI)); - DEBUG(dbgs() << "===========If Region End===============\n"); + LLVM_DEBUG(dbgs() << "===========If Region End===============\n"); Region->setLinearizedRegion(LRegion); return true; @@ -2785,12 +2799,12 @@ bool AMDGPUMachineCFGStructurizer::structurizeRegions(RegionMRT *Region, } void AMDGPUMachineCFGStructurizer::initFallthroughMap(MachineFunction &MF) { - DEBUG(dbgs() << "Fallthrough Map:\n"); + LLVM_DEBUG(dbgs() << "Fallthrough Map:\n"); for (auto &MBBI : MF) { MachineBasicBlock *MBB = MBBI.getFallThrough(); if (MBB != nullptr) { - DEBUG(dbgs() << "Fallthrough: " << MBBI.getNumber() << " -> " - << MBB->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Fallthrough: " << MBBI.getNumber() << " -> " + << MBB->getNumber() << "\n"); } FallthroughMap[&MBBI] = MBB; } @@ -2801,8 +2815,8 @@ void AMDGPUMachineCFGStructurizer::createLinearizedRegion(RegionMRT *Region, LinearizedRegion *LRegion = new LinearizedRegion(); if (SelectOut) { LRegion->addLiveOut(SelectOut); - DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI) - << "\n"); + LLVM_DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI) + << "\n"); } LRegion->setRegionMRT(Region); Region->setLinearizedRegion(LRegion); @@ -2864,19 +2878,19 @@ bool AMDGPUMachineCFGStructurizer::runOnMachineFunction(MachineFunction &MF) { initFallthroughMap(MF); checkRegOnlyPHIInputs(MF); - DEBUG(dbgs() << "----STRUCTURIZER START----\n"); - DEBUG(MF.dump()); + LLVM_DEBUG(dbgs() << "----STRUCTURIZER START----\n"); + LLVM_DEBUG(MF.dump()); Regions = &(getAnalysis<MachineRegionInfoPass>().getRegionInfo()); - DEBUG(Regions->dump()); + LLVM_DEBUG(Regions->dump()); RegionMRT *RTree = MRT::buildMRT(MF, Regions, TII, MRI); setRegionMRT(RTree); initializeSelectRegisters(RTree, 0, MRI, TII); - DEBUG(RTree->dump(TRI)); + LLVM_DEBUG(RTree->dump(TRI)); bool result = structurizeRegions(RTree, true); delete RTree; - DEBUG(dbgs() << "----STRUCTURIZER END----\n"); + LLVM_DEBUG(dbgs() << "----STRUCTURIZER END----\n"); initFallthroughMap(MF); return result; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp index 265104a8643..4ff6c6e01c6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp @@ -114,7 +114,7 @@ bool AMDGPUOpenCLEnqueuedBlockLowering::runOnModule(Module &M) { M.getDataLayout()); F.setName(Name); } - DEBUG(dbgs() << "found enqueued kernel: " << F.getName() << '\n'); + LLVM_DEBUG(dbgs() << "found enqueued kernel: " << F.getName() << '\n'); auto RuntimeHandle = (F.getName() + ".runtime_handle").str(); auto T = Type::getInt8Ty(C)->getPointerTo(AMDGPUAS::GLOBAL_ADDRESS); auto *GV = new GlobalVariable( @@ -124,7 +124,7 @@ bool AMDGPUOpenCLEnqueuedBlockLowering::runOnModule(Module &M) { /*InsertBefore=*/nullptr, GlobalValue::NotThreadLocal, AMDGPUAS::GLOBAL_ADDRESS, /*IsExternallyInitialized=*/false); - DEBUG(dbgs() << "runtime handle created: " << *GV << '\n'); + LLVM_DEBUG(dbgs() << "runtime handle created: " << *GV << '\n'); for (auto U : F.users()) { auto *UU = &*U; @@ -145,7 +145,7 @@ bool AMDGPUOpenCLEnqueuedBlockLowering::runOnModule(Module &M) { if (F->getCallingConv() != CallingConv::AMDGPU_KERNEL) continue; F->addFnAttr("calls-enqueue-kernel"); - DEBUG(dbgs() << "mark enqueue_kernel caller:" << F->getName() << '\n'); + LLVM_DEBUG(dbgs() << "mark enqueue_kernel caller:" << F->getName() << '\n'); } return Changed; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index 7d28c3c8259..9264cb11fb8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -343,13 +343,13 @@ static bool canVectorizeInst(Instruction *Inst, User *User) { static bool tryPromoteAllocaToVector(AllocaInst *Alloca, AMDGPUAS AS) { if (DisablePromoteAllocaToVector) { - DEBUG(dbgs() << " Promotion alloca to vector is disabled\n"); + LLVM_DEBUG(dbgs() << " Promotion alloca to vector is disabled\n"); return false; } ArrayType *AllocaTy = dyn_cast<ArrayType>(Alloca->getAllocatedType()); - DEBUG(dbgs() << "Alloca candidate for vectorization\n"); + LLVM_DEBUG(dbgs() << "Alloca candidate for vectorization\n"); // FIXME: There is no reason why we can't support larger arrays, we // are just being conservative for now. @@ -359,7 +359,7 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca, AMDGPUAS AS) { AllocaTy->getNumElements() > 16 || AllocaTy->getNumElements() < 2 || !VectorType::isValidElementType(AllocaTy->getElementType())) { - DEBUG(dbgs() << " Cannot convert type to vector\n"); + LLVM_DEBUG(dbgs() << " Cannot convert type to vector\n"); return false; } @@ -380,7 +380,8 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca, AMDGPUAS AS) { // If we can't compute a vector index from this GEP, then we can't // promote this alloca to vector. if (!Index) { - DEBUG(dbgs() << " Cannot compute vector index for GEP " << *GEP << '\n'); + LLVM_DEBUG(dbgs() << " Cannot compute vector index for GEP " << *GEP + << '\n'); return false; } @@ -395,8 +396,8 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca, AMDGPUAS AS) { VectorType *VectorTy = arrayTypeToVecType(AllocaTy); - DEBUG(dbgs() << " Converting alloca to vector " - << *AllocaTy << " -> " << *VectorTy << '\n'); + LLVM_DEBUG(dbgs() << " Converting alloca to vector " << *AllocaTy << " -> " + << *VectorTy << '\n'); for (Value *V : WorkList) { Instruction *Inst = cast<Instruction>(V); @@ -485,7 +486,8 @@ bool AMDGPUPromoteAlloca::binaryOpIsDerivedFromSameAlloca(Value *BaseAlloca, // important part is both must have the same address space at // the end. if (OtherObj != BaseAlloca) { - DEBUG(dbgs() << "Found a binary instruction with another alloca object\n"); + LLVM_DEBUG( + dbgs() << "Found a binary instruction with another alloca object\n"); return false; } @@ -607,8 +609,8 @@ bool AMDGPUPromoteAlloca::hasSufficientLocalMem(const Function &F) { PointerType *PtrTy = dyn_cast<PointerType>(ParamTy); if (PtrTy && PtrTy->getAddressSpace() == AS.LOCAL_ADDRESS) { LocalMemLimit = 0; - DEBUG(dbgs() << "Function has local memory argument. Promoting to " - "local memory disabled.\n"); + LLVM_DEBUG(dbgs() << "Function has local memory argument. Promoting to " + "local memory disabled.\n"); return false; } } @@ -677,13 +679,12 @@ bool AMDGPUPromoteAlloca::hasSufficientLocalMem(const Function &F) { LocalMemLimit = MaxSizeWithWaveCount; - DEBUG( - dbgs() << F.getName() << " uses " << CurrentLocalMemUsage << " bytes of LDS\n" - << " Rounding size to " << MaxSizeWithWaveCount - << " with a maximum occupancy of " << MaxOccupancy << '\n' - << " and " << (LocalMemLimit - CurrentLocalMemUsage) - << " available for promotion\n" - ); + LLVM_DEBUG(dbgs() << F.getName() << " uses " << CurrentLocalMemUsage + << " bytes of LDS\n" + << " Rounding size to " << MaxSizeWithWaveCount + << " with a maximum occupancy of " << MaxOccupancy << '\n' + << " and " << (LocalMemLimit - CurrentLocalMemUsage) + << " available for promotion\n"); return true; } @@ -700,7 +701,7 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) { // First try to replace the alloca with a vector Type *AllocaTy = I.getAllocatedType(); - DEBUG(dbgs() << "Trying to promote " << I << '\n'); + LLVM_DEBUG(dbgs() << "Trying to promote " << I << '\n'); if (tryPromoteAllocaToVector(&I, AS)) return true; // Promoted to vector. @@ -716,7 +717,9 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) { case CallingConv::SPIR_KERNEL: break; default: - DEBUG(dbgs() << " promote alloca to LDS not supported with calling convention.\n"); + LLVM_DEBUG( + dbgs() + << " promote alloca to LDS not supported with calling convention.\n"); return false; } @@ -745,8 +748,8 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) { NewSize += AllocSize; if (NewSize > LocalMemLimit) { - DEBUG(dbgs() << " " << AllocSize - << " bytes of local memory not available to promote\n"); + LLVM_DEBUG(dbgs() << " " << AllocSize + << " bytes of local memory not available to promote\n"); return false; } @@ -755,11 +758,11 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) { std::vector<Value*> WorkList; if (!collectUsesWithPtrTypes(&I, &I, WorkList)) { - DEBUG(dbgs() << " Do not know how to convert all uses\n"); + LLVM_DEBUG(dbgs() << " Do not know how to convert all uses\n"); return false; } - DEBUG(dbgs() << "Promoting alloca to local memory\n"); + LLVM_DEBUG(dbgs() << "Promoting alloca to local memory\n"); Function *F = I.getParent()->getParent(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp index 83e56a9ab49..a861762a8c9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp @@ -249,8 +249,8 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) { SmallVector<Argument *, 4> OutArgs; for (Argument &Arg : F.args()) { if (isOutArgumentCandidate(Arg)) { - DEBUG(dbgs() << "Found possible out argument " << Arg - << " in function " << F.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Found possible out argument " << Arg + << " in function " << F.getName() << '\n'); OutArgs.push_back(&Arg); } } @@ -310,7 +310,7 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) { SI = dyn_cast<StoreInst>(Q.getInst()); if (SI) { - DEBUG(dbgs() << "Found out argument store: " << *SI << '\n'); + LLVM_DEBUG(dbgs() << "Found out argument store: " << *SI << '\n'); ReplaceableStores.emplace_back(RI, SI); } else { ThisReplaceable = false; @@ -328,7 +328,8 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) { if (llvm::find_if(ValVec, [OutArg](const std::pair<Argument *, Value *> &Entry) { return Entry.first == OutArg;}) != ValVec.end()) { - DEBUG(dbgs() << "Saw multiple out arg stores" << *OutArg << '\n'); + LLVM_DEBUG(dbgs() + << "Saw multiple out arg stores" << *OutArg << '\n'); // It is possible to see stores to the same argument multiple times, // but we expect these would have been optimized out already. ThisReplaceable = false; @@ -358,7 +359,7 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) { F.getFunctionType()->params(), F.isVarArg()); - DEBUG(dbgs() << "Computed new return type: " << *NewRetTy << '\n'); + LLVM_DEBUG(dbgs() << "Computed new return type: " << *NewRetTy << '\n'); Function *NewFunc = Function::Create(NewFuncTy, Function::PrivateLinkage, F.getName() + ".body"); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 3ea7a82ea7a..ce17f027b52 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -124,8 +124,9 @@ void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, continue; if (dependsOnLocalPhi(L, Br->getCondition())) { UP.Threshold += UnrollThresholdIf; - DEBUG(dbgs() << "Set unroll threshold " << UP.Threshold - << " for loop:\n" << *L << " due to " << *Br << '\n'); + LLVM_DEBUG(dbgs() << "Set unroll threshold " << UP.Threshold + << " for loop:\n" + << *L << " due to " << *Br << '\n'); if (UP.Threshold >= MaxBoost) return; } @@ -201,8 +202,9 @@ void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, // Don't use the maximum allowed value here as it will make some // programs way too big. UP.Threshold = Threshold; - DEBUG(dbgs() << "Set unroll threshold " << Threshold << " for loop:\n" - << *L << " due to " << *GEP << '\n'); + LLVM_DEBUG(dbgs() << "Set unroll threshold " << Threshold + << " for loop:\n" + << *L << " due to " << *GEP << '\n'); if (UP.Threshold >= MaxBoost) return; } diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp index 1793de63b59..cd1801a8244 100644 --- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -78,23 +78,18 @@ namespace { // //===----------------------------------------------------------------------===// -#define SHOWNEWINSTR(i) \ - DEBUG(dbgs() << "New instr: " << *i << "\n"); - -#define SHOWNEWBLK(b, msg) \ -DEBUG( \ - dbgs() << msg << "BB" << b->getNumber() << "size " << b->size(); \ - dbgs() << "\n"; \ -); - -#define SHOWBLK_DETAIL(b, msg) \ -DEBUG( \ - if (b) { \ - dbgs() << msg << "BB" << b->getNumber() << "size " << b->size(); \ - b->print(dbgs()); \ - dbgs() << "\n"; \ - } \ -); +#define SHOWNEWINSTR(i) LLVM_DEBUG(dbgs() << "New instr: " << *i << "\n"); + +#define SHOWNEWBLK(b, msg) \ + LLVM_DEBUG(dbgs() << msg << "BB" << b->getNumber() << "size " << b->size(); \ + dbgs() << "\n";); + +#define SHOWBLK_DETAIL(b, msg) \ + LLVM_DEBUG(if (b) { \ + dbgs() << msg << "BB" << b->getNumber() << "size " << b->size(); \ + b->print(dbgs()); \ + dbgs() << "\n"; \ + }); #define INVALIDSCCNUM -1 @@ -158,19 +153,19 @@ public: bool runOnMachineFunction(MachineFunction &MF) override { TII = MF.getSubtarget<R600Subtarget>().getInstrInfo(); TRI = &TII->getRegisterInfo(); - DEBUG(MF.dump();); + LLVM_DEBUG(MF.dump();); OrderedBlks.clear(); Visited.clear(); FuncRep = &MF; MLI = &getAnalysis<MachineLoopInfo>(); - DEBUG(dbgs() << "LoopInfo:\n"; PrintLoopinfo(*MLI);); + LLVM_DEBUG(dbgs() << "LoopInfo:\n"; PrintLoopinfo(*MLI);); MDT = &getAnalysis<MachineDominatorTree>(); - DEBUG(MDT->print(dbgs(), (const Module*)nullptr);); + LLVM_DEBUG(MDT->print(dbgs(), (const Module *)nullptr);); PDT = &getAnalysis<MachinePostDominatorTree>(); - DEBUG(PDT->print(dbgs());); + LLVM_DEBUG(PDT->print(dbgs());); prepare(); run(); - DEBUG(MF.dump();); + LLVM_DEBUG(MF.dump();); return true; } @@ -650,9 +645,8 @@ bool AMDGPUCFGStructurizer::isReturnBlock(MachineBasicBlock *MBB) { if (MI) assert(IsReturn); else if (IsReturn) - DEBUG( - dbgs() << "BB" << MBB->getNumber() - <<" is return block without RETURN instr\n";); + LLVM_DEBUG(dbgs() << "BB" << MBB->getNumber() + << " is return block without RETURN instr\n";); return IsReturn; } @@ -714,7 +708,7 @@ bool AMDGPUCFGStructurizer::prepare() { //FIXME: if not reducible flow graph, make it so ??? - DEBUG(dbgs() << "AMDGPUCFGStructurizer::prepare\n";); + LLVM_DEBUG(dbgs() << "AMDGPUCFGStructurizer::prepare\n";); orderBlocks(FuncRep); @@ -757,14 +751,14 @@ bool AMDGPUCFGStructurizer::prepare() { bool AMDGPUCFGStructurizer::run() { //Assume reducible CFG... - DEBUG(dbgs() << "AMDGPUCFGStructurizer::run\n"); + LLVM_DEBUG(dbgs() << "AMDGPUCFGStructurizer::run\n"); #ifdef STRESSTEST //Use the worse block ordering to test the algorithm. ReverseVector(orderedBlks); #endif - DEBUG(dbgs() << "Ordered blocks:\n"; printOrderedBlocks();); + LLVM_DEBUG(dbgs() << "Ordered blocks:\n"; printOrderedBlocks();); int NumIter = 0; bool Finish = false; MachineBasicBlock *MBB; @@ -774,10 +768,8 @@ bool AMDGPUCFGStructurizer::run() { do { ++NumIter; - DEBUG( - dbgs() << "numIter = " << NumIter - << ", numRemaintedBlk = " << NumRemainedBlk << "\n"; - ); + LLVM_DEBUG(dbgs() << "numIter = " << NumIter + << ", numRemaintedBlk = " << NumRemainedBlk << "\n";); SmallVectorImpl<MachineBasicBlock *>::const_iterator It = OrderedBlks.begin(); @@ -799,10 +791,8 @@ bool AMDGPUCFGStructurizer::run() { SccBeginMBB = MBB; SccNumIter = 0; SccNumBlk = NumRemainedBlk; // Init to maximum possible number. - DEBUG( - dbgs() << "start processing SCC" << getSCCNum(SccBeginMBB); - dbgs() << "\n"; - ); + LLVM_DEBUG(dbgs() << "start processing SCC" << getSCCNum(SccBeginMBB); + dbgs() << "\n";); } if (!isRetiredBlock(MBB)) @@ -817,20 +807,16 @@ bool AMDGPUCFGStructurizer::run() { ++SccNumIter; int sccRemainedNumBlk = countActiveBlock(SccBeginIter, It); if (sccRemainedNumBlk != 1 && sccRemainedNumBlk >= SccNumBlk) { - DEBUG( - dbgs() << "Can't reduce SCC " << getSCCNum(MBB) - << ", sccNumIter = " << SccNumIter; - dbgs() << "doesn't make any progress\n"; - ); + LLVM_DEBUG(dbgs() << "Can't reduce SCC " << getSCCNum(MBB) + << ", sccNumIter = " << SccNumIter; + dbgs() << "doesn't make any progress\n";); ContNextScc = true; } else if (sccRemainedNumBlk != 1 && sccRemainedNumBlk < SccNumBlk) { SccNumBlk = sccRemainedNumBlk; It = SccBeginIter; ContNextScc = false; - DEBUG( - dbgs() << "repeat processing SCC" << getSCCNum(MBB) - << "sccNumIter = " << SccNumIter << '\n'; - ); + LLVM_DEBUG(dbgs() << "repeat processing SCC" << getSCCNum(MBB) + << "sccNumIter = " << SccNumIter << '\n';); } else { // Finish the current scc. ContNextScc = true; @@ -848,9 +834,7 @@ bool AMDGPUCFGStructurizer::run() { *GraphTraits<MachineFunction *>::nodes_begin(FuncRep); if (EntryMBB->succ_size() == 0) { Finish = true; - DEBUG( - dbgs() << "Reduce to one block\n"; - ); + LLVM_DEBUG(dbgs() << "Reduce to one block\n";); } else { int NewnumRemainedBlk = countActiveBlock(OrderedBlks.begin(), OrderedBlks.end()); @@ -860,9 +844,7 @@ bool AMDGPUCFGStructurizer::run() { NumRemainedBlk = NewnumRemainedBlk; } else { MakeProgress = false; - DEBUG( - dbgs() << "No progress\n"; - ); + LLVM_DEBUG(dbgs() << "No progress\n";); } } } while (!Finish && MakeProgress); @@ -875,9 +857,7 @@ bool AMDGPUCFGStructurizer::run() { It != E; ++It) { if ((*It).second && (*It).second->IsRetired) { assert(((*It).first)->getNumber() != -1); - DEBUG( - dbgs() << "Erase BB" << ((*It).first)->getNumber() << "\n"; - ); + LLVM_DEBUG(dbgs() << "Erase BB" << ((*It).first)->getNumber() << "\n";); (*It).first->eraseFromParent(); //Remove from the parent Function. } delete (*It).second; @@ -886,7 +866,7 @@ bool AMDGPUCFGStructurizer::run() { LLInfoMap.clear(); if (!Finish) { - DEBUG(FuncRep->viewCFG()); + LLVM_DEBUG(FuncRep->viewCFG()); report_fatal_error("IRREDUCIBLE_CFG"); } @@ -920,17 +900,13 @@ int AMDGPUCFGStructurizer::patternMatch(MachineBasicBlock *MBB) { int NumMatch = 0; int CurMatch; - DEBUG( - dbgs() << "Begin patternMatch BB" << MBB->getNumber() << "\n"; - ); + LLVM_DEBUG(dbgs() << "Begin patternMatch BB" << MBB->getNumber() << "\n";); while ((CurMatch = patternMatchGroup(MBB)) > 0) NumMatch += CurMatch; - DEBUG( - dbgs() << "End patternMatch BB" << MBB->getNumber() - << ", numMatch = " << NumMatch << "\n"; - ); + LLVM_DEBUG(dbgs() << "End patternMatch BB" << MBB->getNumber() + << ", numMatch = " << NumMatch << "\n";); return NumMatch; } @@ -1050,7 +1026,7 @@ int AMDGPUCFGStructurizer::loopendPatternMatch() { for (MachineLoop *ExaminedLoop : NestedLoops) { if (ExaminedLoop->getNumBlocks() == 0 || Visited[ExaminedLoop]) continue; - DEBUG(dbgs() << "Processing:\n"; ExaminedLoop->dump();); + LLVM_DEBUG(dbgs() << "Processing:\n"; ExaminedLoop->dump();); int NumBreak = mergeLoop(ExaminedLoop); if (NumBreak == -1) break; @@ -1064,7 +1040,8 @@ int AMDGPUCFGStructurizer::mergeLoop(MachineLoop *LoopRep) { MBBVector ExitingMBBs; LoopRep->getExitingBlocks(ExitingMBBs); assert(!ExitingMBBs.empty() && "Infinite Loop not supported"); - DEBUG(dbgs() << "Loop has " << ExitingMBBs.size() << " exiting blocks\n";); + LLVM_DEBUG(dbgs() << "Loop has " << ExitingMBBs.size() + << " exiting blocks\n";); // We assume a single ExitBlk MBBVector ExitBlks; LoopRep->getExitBlocks(ExitBlks); @@ -1106,11 +1083,9 @@ bool AMDGPUCFGStructurizer::isSameloopDetachedContbreak( if (LoopRep&& LoopRep == MLI->getLoopFor(Src2MBB)) { MachineBasicBlock *&TheEntry = LLInfoMap[LoopRep]; if (TheEntry) { - DEBUG( - dbgs() << "isLoopContBreakBlock yes src1 = BB" - << Src1MBB->getNumber() - << " src2 = BB" << Src2MBB->getNumber() << "\n"; - ); + LLVM_DEBUG(dbgs() << "isLoopContBreakBlock yes src1 = BB" + << Src1MBB->getNumber() << " src2 = BB" + << Src2MBB->getNumber() << "\n";); return true; } } @@ -1122,9 +1097,8 @@ int AMDGPUCFGStructurizer::handleJumpintoIf(MachineBasicBlock *HeadMBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB) { int Num = handleJumpintoIfImp(HeadMBB, TrueMBB, FalseMBB); if (Num == 0) { - DEBUG( - dbgs() << "handleJumpintoIf swap trueBlk and FalseBlk" << "\n"; - ); + LLVM_DEBUG(dbgs() << "handleJumpintoIf swap trueBlk and FalseBlk" + << "\n";); Num = handleJumpintoIfImp(HeadMBB, FalseMBB, TrueMBB); } return Num; @@ -1138,22 +1112,16 @@ int AMDGPUCFGStructurizer::handleJumpintoIfImp(MachineBasicBlock *HeadMBB, //trueBlk could be the common post dominator DownBlk = TrueMBB; - DEBUG( - dbgs() << "handleJumpintoIfImp head = BB" << HeadMBB->getNumber() - << " true = BB" << TrueMBB->getNumber() - << ", numSucc=" << TrueMBB->succ_size() - << " false = BB" << FalseMBB->getNumber() << "\n"; - ); + LLVM_DEBUG(dbgs() << "handleJumpintoIfImp head = BB" << HeadMBB->getNumber() + << " true = BB" << TrueMBB->getNumber() + << ", numSucc=" << TrueMBB->succ_size() << " false = BB" + << FalseMBB->getNumber() << "\n";); while (DownBlk) { - DEBUG( - dbgs() << "check down = BB" << DownBlk->getNumber(); - ); + LLVM_DEBUG(dbgs() << "check down = BB" << DownBlk->getNumber();); if (singlePathTo(FalseMBB, DownBlk) == SinglePath_InPath) { - DEBUG( - dbgs() << " working\n"; - ); + LLVM_DEBUG(dbgs() << " working\n";); Num += cloneOnSideEntryTo(HeadMBB, TrueMBB, DownBlk); Num += cloneOnSideEntryTo(HeadMBB, FalseMBB, DownBlk); @@ -1166,9 +1134,7 @@ int AMDGPUCFGStructurizer::handleJumpintoIfImp(MachineBasicBlock *HeadMBB, break; } - DEBUG( - dbgs() << " not working\n"; - ); + LLVM_DEBUG(dbgs() << " not working\n";); DownBlk = (DownBlk->succ_size() == 1) ? (*DownBlk->succ_begin()) : nullptr; } // walk down the postDomTree @@ -1247,10 +1213,9 @@ int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB, if (!MigrateFalse && FalseMBB && FalseMBB->pred_size() > 1) MigrateFalse = true; - DEBUG( - dbgs() << "before improveSimpleJumpintoIf: "; - showImproveSimpleJumpintoIf(HeadMBB, TrueMBB, FalseMBB, LandBlk, 0); - ); + LLVM_DEBUG( + dbgs() << "before improveSimpleJumpintoIf: "; + showImproveSimpleJumpintoIf(HeadMBB, TrueMBB, FalseMBB, LandBlk, 0);); // org: headBlk => if () {trueBlk} else {falseBlk} => landBlk // @@ -1385,10 +1350,9 @@ int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB, report_fatal_error("Extra register needed to handle CFG"); } } - DEBUG( - dbgs() << "result from improveSimpleJumpintoIf: "; - showImproveSimpleJumpintoIf(HeadMBB, TrueMBB, FalseMBB, LandBlk, 0); - ); + LLVM_DEBUG( + dbgs() << "result from improveSimpleJumpintoIf: "; + showImproveSimpleJumpintoIf(HeadMBB, TrueMBB, FalseMBB, LandBlk, 0);); // update landBlk *LandMBBPtr = LandBlk; @@ -1398,10 +1362,8 @@ int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB, void AMDGPUCFGStructurizer::mergeSerialBlock(MachineBasicBlock *DstMBB, MachineBasicBlock *SrcMBB) { - DEBUG( - dbgs() << "serialPattern BB" << DstMBB->getNumber() - << " <= BB" << SrcMBB->getNumber() << "\n"; - ); + LLVM_DEBUG(dbgs() << "serialPattern BB" << DstMBB->getNumber() << " <= BB" + << SrcMBB->getNumber() << "\n";); DstMBB->splice(DstMBB->end(), SrcMBB, SrcMBB->begin(), SrcMBB->end()); DstMBB->removeSuccessor(SrcMBB, true); @@ -1416,26 +1378,15 @@ void AMDGPUCFGStructurizer::mergeIfthenelseBlock(MachineInstr *BranchMI, MachineBasicBlock *MBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB, MachineBasicBlock *LandMBB) { assert (TrueMBB); - DEBUG( - dbgs() << "ifPattern BB" << MBB->getNumber(); - dbgs() << "{ "; - if (TrueMBB) { - dbgs() << "BB" << TrueMBB->getNumber(); - } - dbgs() << " } else "; - dbgs() << "{ "; - if (FalseMBB) { - dbgs() << "BB" << FalseMBB->getNumber(); - } - dbgs() << " }\n "; - dbgs() << "landBlock: "; - if (!LandMBB) { - dbgs() << "NULL"; - } else { - dbgs() << "BB" << LandMBB->getNumber(); - } - dbgs() << "\n"; - ); + LLVM_DEBUG(dbgs() << "ifPattern BB" << MBB->getNumber(); dbgs() << "{ "; + if (TrueMBB) { dbgs() << "BB" << TrueMBB->getNumber(); } dbgs() + << " } else "; + dbgs() << "{ "; if (FalseMBB) { + dbgs() << "BB" << FalseMBB->getNumber(); + } dbgs() << " }\n "; + dbgs() << "landBlock: "; if (!LandMBB) { dbgs() << "NULL"; } else { + dbgs() << "BB" << LandMBB->getNumber(); + } dbgs() << "\n";); int OldOpcode = BranchMI->getOpcode(); DebugLoc BranchDL = BranchMI->getDebugLoc(); @@ -1481,8 +1432,8 @@ void AMDGPUCFGStructurizer::mergeIfthenelseBlock(MachineInstr *BranchMI, void AMDGPUCFGStructurizer::mergeLooplandBlock(MachineBasicBlock *DstBlk, MachineBasicBlock *LandMBB) { - DEBUG(dbgs() << "loopPattern header = BB" << DstBlk->getNumber() - << " land = BB" << LandMBB->getNumber() << "\n";); + LLVM_DEBUG(dbgs() << "loopPattern header = BB" << DstBlk->getNumber() + << " land = BB" << LandMBB->getNumber() << "\n";); insertInstrBefore(DstBlk, AMDGPU::WHILELOOP, DebugLoc()); insertInstrEnd(DstBlk, AMDGPU::ENDLOOP, DebugLoc()); @@ -1491,8 +1442,9 @@ void AMDGPUCFGStructurizer::mergeLooplandBlock(MachineBasicBlock *DstBlk, void AMDGPUCFGStructurizer::mergeLoopbreakBlock(MachineBasicBlock *ExitingMBB, MachineBasicBlock *LandMBB) { - DEBUG(dbgs() << "loopbreakPattern exiting = BB" << ExitingMBB->getNumber() - << " land = BB" << LandMBB->getNumber() << "\n";); + LLVM_DEBUG(dbgs() << "loopbreakPattern exiting = BB" + << ExitingMBB->getNumber() << " land = BB" + << LandMBB->getNumber() << "\n";); MachineInstr *BranchMI = getLoopendBlockBranchInstr(ExitingMBB); assert(BranchMI && isCondBranch(BranchMI)); DebugLoc DL = BranchMI->getDebugLoc(); @@ -1511,9 +1463,9 @@ void AMDGPUCFGStructurizer::mergeLoopbreakBlock(MachineBasicBlock *ExitingMBB, void AMDGPUCFGStructurizer::settleLoopcontBlock(MachineBasicBlock *ContingMBB, MachineBasicBlock *ContMBB) { - DEBUG(dbgs() << "settleLoopcontBlock conting = BB" - << ContingMBB->getNumber() - << ", cont = BB" << ContMBB->getNumber() << "\n";); + LLVM_DEBUG(dbgs() << "settleLoopcontBlock conting = BB" + << ContingMBB->getNumber() << ", cont = BB" + << ContMBB->getNumber() << "\n";); MachineInstr *MI = getLoopendBlockBranchInstr(ContingMBB); if (MI) { @@ -1587,10 +1539,9 @@ AMDGPUCFGStructurizer::cloneBlockForPredecessor(MachineBasicBlock *MBB, numClonedInstr += MBB->size(); - DEBUG( - dbgs() << "Cloned block: " << "BB" - << MBB->getNumber() << "size " << MBB->size() << "\n"; - ); + LLVM_DEBUG(dbgs() << "Cloned block: " + << "BB" << MBB->getNumber() << "size " << MBB->size() + << "\n";); SHOWNEWBLK(CloneMBB, "result of Cloned block: "); @@ -1603,26 +1554,22 @@ void AMDGPUCFGStructurizer::migrateInstruction(MachineBasicBlock *SrcMBB, //look for the input branchinstr, not the AMDGPU branchinstr MachineInstr *BranchMI = getNormalBlockBranchInstr(SrcMBB); if (!BranchMI) { - DEBUG( - dbgs() << "migrateInstruction don't see branch instr\n"; - ); + LLVM_DEBUG(dbgs() << "migrateInstruction don't see branch instr\n";); SpliceEnd = SrcMBB->end(); } else { - DEBUG(dbgs() << "migrateInstruction see branch instr: " << *BranchMI); + LLVM_DEBUG(dbgs() << "migrateInstruction see branch instr: " << *BranchMI); SpliceEnd = BranchMI; } - DEBUG( - dbgs() << "migrateInstruction before splice dstSize = " << DstMBB->size() - << "srcSize = " << SrcMBB->size() << "\n"; - ); + LLVM_DEBUG(dbgs() << "migrateInstruction before splice dstSize = " + << DstMBB->size() << "srcSize = " << SrcMBB->size() + << "\n";); //splice insert before insertPos DstMBB->splice(I, SrcMBB, SrcMBB->begin(), SpliceEnd); - DEBUG( - dbgs() << "migrateInstruction after splice dstSize = " << DstMBB->size() - << "srcSize = " << SrcMBB->size() << '\n'; - ); + LLVM_DEBUG(dbgs() << "migrateInstruction after splice dstSize = " + << DstMBB->size() << "srcSize = " << SrcMBB->size() + << '\n';); } MachineBasicBlock * @@ -1640,7 +1587,7 @@ AMDGPUCFGStructurizer::normalizeInfiniteLoopExit(MachineLoop* LoopRep) { MachineBasicBlock *DummyExitBlk = FuncRep->CreateMachineBasicBlock(); FuncRep->push_back(DummyExitBlk); //insert to function SHOWNEWBLK(DummyExitBlk, "DummyExitBlock to normalize infiniteLoop: "); - DEBUG(dbgs() << "Old branch instr: " << *BranchMI << "\n";); + LLVM_DEBUG(dbgs() << "Old branch instr: " << *BranchMI << "\n";); LLVMContext &Ctx = LoopHeader->getParent()->getFunction().getContext(); Ctx.emitError("Extra register needed to handle CFG"); return nullptr; @@ -1653,7 +1600,7 @@ void AMDGPUCFGStructurizer::removeUnconditionalBranch(MachineBasicBlock *MBB) { // test_fc_do_while_or.c need to fix the upstream on this to remove the loop. while ((BranchMI = getLoopendBlockBranchInstr(MBB)) && isUncondBranch(BranchMI)) { - DEBUG(dbgs() << "Removing uncond branch instr: " << *BranchMI); + LLVM_DEBUG(dbgs() << "Removing uncond branch instr: " << *BranchMI); BranchMI->eraseFromParent(); } } @@ -1669,7 +1616,7 @@ void AMDGPUCFGStructurizer::removeRedundantConditionalBranch( MachineInstr *BranchMI = getNormalBlockBranchInstr(MBB); assert(BranchMI && isCondBranch(BranchMI)); - DEBUG(dbgs() << "Removing unneeded cond branch instr: " << *BranchMI); + LLVM_DEBUG(dbgs() << "Removing unneeded cond branch instr: " << *BranchMI); BranchMI->eraseFromParent(); SHOWNEWBLK(MBB1, "Removing redundant successor"); MBB->removeSuccessor(MBB1, true); @@ -1688,10 +1635,8 @@ void AMDGPUCFGStructurizer::addDummyExitBlock( if (MI) MI->eraseFromParent(); MBB->addSuccessor(DummyExitBlk); - DEBUG( - dbgs() << "Add dummyExitBlock to BB" << MBB->getNumber() - << " successors\n"; - ); + LLVM_DEBUG(dbgs() << "Add dummyExitBlock to BB" << MBB->getNumber() + << " successors\n";); } SHOWNEWBLK(DummyExitBlk, "DummyExitBlock: "); } @@ -1710,9 +1655,7 @@ void AMDGPUCFGStructurizer::recordSccnum(MachineBasicBlock *MBB, } void AMDGPUCFGStructurizer::retireBlock(MachineBasicBlock *MBB) { - DEBUG( - dbgs() << "Retiring BB" << MBB->getNumber() << "\n"; - ); + LLVM_DEBUG(dbgs() << "Retiring BB" << MBB->getNumber() << "\n";); BlockInformation *&SrcBlkInfo = BlockInfoMap[MBB]; diff --git a/llvm/lib/Target/AMDGPU/GCNILPSched.cpp b/llvm/lib/Target/AMDGPU/GCNILPSched.cpp index ba8211b189c..651091d4413 100644 --- a/llvm/lib/Target/AMDGPU/GCNILPSched.cpp +++ b/llvm/lib/Target/AMDGPU/GCNILPSched.cpp @@ -149,9 +149,9 @@ static int BUCompareLatency(const SUnit *left, const SUnit *right) { int LDepth = left->getDepth(); int RDepth = right->getDepth(); if (LDepth != RDepth) { - DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum - << ") depth " << LDepth << " vs SU (" << right->NodeNum - << ") depth " << RDepth << "\n"); + LLVM_DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum + << ") depth " << LDepth << " vs SU (" << right->NodeNum + << ") depth " << RDepth << "\n"); return LDepth < RDepth ? 1 : -1; } if (left->Latency != right->Latency) @@ -169,9 +169,9 @@ const SUnit *GCNILPScheduler::pickBest(const SUnit *left, const SUnit *right) if (!DisableSchedCriticalPath) { int spread = (int)left->getDepth() - (int)right->getDepth(); if (std::abs(spread) > MaxReorderWindow) { - DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): " - << left->getDepth() << " != SU(" << right->NodeNum << "): " - << right->getDepth() << "\n"); + LLVM_DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): " + << left->getDepth() << " != SU(" << right->NodeNum + << "): " << right->getDepth() << "\n"); return left->getDepth() < right->getDepth() ? right : left; } } @@ -324,19 +324,18 @@ GCNILPScheduler::schedule(ArrayRef<const SUnit*> BotRoots, if (AvailQueue.empty()) break; - DEBUG( - dbgs() << "\n=== Picking candidate\n" - "Ready queue:"; - for (auto &C : AvailQueue) - dbgs() << ' ' << C.SU->NodeNum; - dbgs() << '\n'; - ); + LLVM_DEBUG(dbgs() << "\n=== Picking candidate\n" + "Ready queue:"; + for (auto &C + : AvailQueue) dbgs() + << ' ' << C.SU->NodeNum; + dbgs() << '\n';); auto C = pickCandidate(); assert(C); AvailQueue.remove(*C); auto SU = C->SU; - DEBUG(dbgs() << "Selected "; SU->dump(&DAG)); + LLVM_DEBUG(dbgs() << "Selected "; SU->dump(&DAG)); advanceToCycle(SU->getHeight()); diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index 182ce1e4f63..7f0d80f3d77 100644 --- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -200,8 +200,8 @@ public: void schedule() { assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); - DEBUG(dbgs() << "\nScheduling "; - printRegion(dbgs(), Rgn.Begin, Rgn.End, Sch.LIS, 2)); + LLVM_DEBUG(dbgs() << "\nScheduling "; + printRegion(dbgs(), Rgn.Begin, Rgn.End, Sch.LIS, 2)); Sch.BaseClass::schedule(); // Unfortunatelly placeDebugValues incorrectly modifies RegionEnd, restore @@ -311,14 +311,13 @@ void GCNIterativeScheduler::enterRegion(MachineBasicBlock *BB, // overriden void GCNIterativeScheduler::schedule() { // overriden // do nothing - DEBUG( - printLivenessInfo(dbgs(), RegionBegin, RegionEnd, LIS); - if (!Regions.empty() && Regions.back()->Begin == RegionBegin) { - dbgs() << "Max RP: "; - Regions.back()->MaxPressure.print(dbgs(), &MF.getSubtarget<SISubtarget>()); - } - dbgs() << '\n'; - ); + LLVM_DEBUG(printLivenessInfo(dbgs(), RegionBegin, RegionEnd, LIS); + if (!Regions.empty() && Regions.back()->Begin == RegionBegin) { + dbgs() << "Max RP: "; + Regions.back()->MaxPressure.print( + dbgs(), &MF.getSubtarget<SISubtarget>()); + } dbgs() + << '\n';); } void GCNIterativeScheduler::finalizeSchedule() { // overriden @@ -453,22 +452,22 @@ unsigned GCNIterativeScheduler::tryMaximizeOccupancy(unsigned TargetOcc) { // TODO: assert Regions are sorted descending by pressure const auto &ST = MF.getSubtarget<SISubtarget>(); const auto Occ = Regions.front()->MaxPressure.getOccupancy(ST); - DEBUG(dbgs() << "Trying to improve occupancy, target = " << TargetOcc - << ", current = " << Occ << '\n'); + LLVM_DEBUG(dbgs() << "Trying to improve occupancy, target = " << TargetOcc + << ", current = " << Occ << '\n'); auto NewOcc = TargetOcc; for (auto R : Regions) { if (R->MaxPressure.getOccupancy(ST) >= NewOcc) break; - DEBUG(printRegion(dbgs(), R->Begin, R->End, LIS, 3); - printLivenessInfo(dbgs(), R->Begin, R->End, LIS)); + LLVM_DEBUG(printRegion(dbgs(), R->Begin, R->End, LIS, 3); + printLivenessInfo(dbgs(), R->Begin, R->End, LIS)); BuildDAG DAG(*R, *this); const auto MinSchedule = makeMinRegSchedule(DAG.getTopRoots(), *this); const auto MaxRP = getSchedulePressure(*R, MinSchedule); - DEBUG(dbgs() << "Occupancy improvement attempt:\n"; - printSchedRP(dbgs(), R->MaxPressure, MaxRP)); + LLVM_DEBUG(dbgs() << "Occupancy improvement attempt:\n"; + printSchedRP(dbgs(), R->MaxPressure, MaxRP)); NewOcc = std::min(NewOcc, MaxRP.getOccupancy(ST)); if (NewOcc <= Occ) @@ -476,8 +475,8 @@ unsigned GCNIterativeScheduler::tryMaximizeOccupancy(unsigned TargetOcc) { setBestSchedule(*R, MinSchedule, MaxRP); } - DEBUG(dbgs() << "New occupancy = " << NewOcc - << ", prev occupancy = " << Occ << '\n'); + LLVM_DEBUG(dbgs() << "New occupancy = " << NewOcc + << ", prev occupancy = " << Occ << '\n'); return std::max(NewOcc, Occ); } @@ -497,8 +496,9 @@ void GCNIterativeScheduler::scheduleLegacyMaxOccupancy( const int NumPasses = Occ < TgtOcc ? 2 : 1; TgtOcc = std::min(Occ, TgtOcc); - DEBUG(dbgs() << "Scheduling using default scheduler, " - "target occupancy = " << TgtOcc << '\n'); + LLVM_DEBUG(dbgs() << "Scheduling using default scheduler, " + "target occupancy = " + << TgtOcc << '\n'); GCNMaxOccupancySchedStrategy LStrgy(Context); for (int I = 0; I < NumPasses; ++I) { @@ -510,16 +510,16 @@ void GCNIterativeScheduler::scheduleLegacyMaxOccupancy( Ovr.schedule(); const auto RP = getRegionPressure(*R); - DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP)); + LLVM_DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP)); if (RP.getOccupancy(ST) < TgtOcc) { - DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc); + LLVM_DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc); if (R->BestSchedule.get() && R->BestSchedule->MaxPressure.getOccupancy(ST) >= TgtOcc) { - DEBUG(dbgs() << ", scheduling minimal register\n"); + LLVM_DEBUG(dbgs() << ", scheduling minimal register\n"); scheduleBest(*R); } else { - DEBUG(dbgs() << ", restoring\n"); + LLVM_DEBUG(dbgs() << ", restoring\n"); Ovr.restoreOrder(); assert(R->MaxPressure.getOccupancy(ST) >= TgtOcc); } @@ -545,7 +545,7 @@ void GCNIterativeScheduler::scheduleMinReg(bool force) { const auto MinSchedule = makeMinRegSchedule(DAG.getTopRoots(), *this); const auto RP = getSchedulePressure(*R, MinSchedule); - DEBUG(if (R->MaxPressure.less(ST, RP, TgtOcc)) { + LLVM_DEBUG(if (R->MaxPressure.less(ST, RP, TgtOcc)) { dbgs() << "\nWarning: Pressure becomes worse after minreg!"; printSchedRP(dbgs(), R->MaxPressure, RP); }); @@ -554,7 +554,7 @@ void GCNIterativeScheduler::scheduleMinReg(bool force) { break; scheduleRegion(*R, MinSchedule, RP); - DEBUG(printSchedResult(dbgs(), R, RP)); + LLVM_DEBUG(printSchedResult(dbgs(), R, RP)); MaxPressure = RP; } @@ -577,26 +577,27 @@ void GCNIterativeScheduler::scheduleILP( Occ = tryMaximizeOccupancy(TgtOcc); TgtOcc = std::min(Occ, TgtOcc); - DEBUG(dbgs() << "Scheduling using default scheduler, " - "target occupancy = " << TgtOcc << '\n'); + LLVM_DEBUG(dbgs() << "Scheduling using default scheduler, " + "target occupancy = " + << TgtOcc << '\n'); for (auto R : Regions) { BuildDAG DAG(*R, *this); const auto ILPSchedule = makeGCNILPScheduler(DAG.getBottomRoots(), *this); const auto RP = getSchedulePressure(*R, ILPSchedule); - DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP)); + LLVM_DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP)); if (RP.getOccupancy(ST) < TgtOcc) { - DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc); + LLVM_DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc); if (R->BestSchedule.get() && R->BestSchedule->MaxPressure.getOccupancy(ST) >= TgtOcc) { - DEBUG(dbgs() << ", scheduling minimal register\n"); + LLVM_DEBUG(dbgs() << ", scheduling minimal register\n"); scheduleBest(*R); } } else { scheduleRegion(*R, ILPSchedule, RP); - DEBUG(printSchedResult(dbgs(), R, RP)); + LLVM_DEBUG(printSchedResult(dbgs(), R, RP)); } } } diff --git a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp index 9904b5f0f4b..192d534bb9c 100644 --- a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp @@ -142,35 +142,38 @@ GCNMinRegScheduler::Candidate* GCNMinRegScheduler::pickCandidate() { unsigned Num = RQ.size(); if (Num == 1) break; - DEBUG(dbgs() << "\nSelecting max priority candidates among " << Num << '\n'); + LLVM_DEBUG(dbgs() << "\nSelecting max priority candidates among " << Num + << '\n'); Num = findMax(Num, [=](const Candidate &C) { return C.Priority; }); if (Num == 1) break; - DEBUG(dbgs() << "\nSelecting min non-ready producing candidate among " - << Num << '\n'); + LLVM_DEBUG(dbgs() << "\nSelecting min non-ready producing candidate among " + << Num << '\n'); Num = findMax(Num, [=](const Candidate &C) { auto SU = C.SU; int Res = getNotReadySuccessors(SU); - DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would left non-ready " - << Res << " successors, metric = " << -Res << '\n'); + LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would left non-ready " + << Res << " successors, metric = " << -Res << '\n'); return -Res; }); if (Num == 1) break; - DEBUG(dbgs() << "\nSelecting most producing candidate among " - << Num << '\n'); + LLVM_DEBUG(dbgs() << "\nSelecting most producing candidate among " << Num + << '\n'); Num = findMax(Num, [=](const Candidate &C) { auto SU = C.SU; auto Res = getReadySuccessors(SU); - DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would make ready " - << Res << " successors, metric = " << Res << '\n'); + LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would make ready " << Res + << " successors, metric = " << Res << '\n'); return Res; }); if (Num == 1) break; Num = Num ? Num : RQ.size(); - DEBUG(dbgs() << "\nCan't find best candidate, selecting in program order among " - << Num << '\n'); + LLVM_DEBUG( + dbgs() + << "\nCan't find best candidate, selecting in program order among " + << Num << '\n'); Num = findMax(Num, [=](const Candidate &C) { return -(int64_t)C.SU->NodeNum; }); assert(Num == 1); } while (false); @@ -202,17 +205,17 @@ void GCNMinRegScheduler::bumpPredsPriority(const SUnit *SchedSU, int Priority) { Worklist.push_back(P.getSUnit()); } } - DEBUG(dbgs() << "Make the predecessors of SU(" << SchedSU->NodeNum - << ")'s non-ready successors of " << Priority - << " priority in ready queue: "); + LLVM_DEBUG(dbgs() << "Make the predecessors of SU(" << SchedSU->NodeNum + << ")'s non-ready successors of " << Priority + << " priority in ready queue: "); const auto SetEnd = Set.end(); for (auto &C : RQ) { if (Set.find(C.SU) != SetEnd) { C.Priority = Priority; - DEBUG(dbgs() << " SU(" << C.SU->NodeNum << ')'); + LLVM_DEBUG(dbgs() << " SU(" << C.SU->NodeNum << ')'); } } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } void GCNMinRegScheduler::releaseSuccessors(const SUnit* SU, int Priority) { @@ -243,19 +246,19 @@ GCNMinRegScheduler::schedule(ArrayRef<const SUnit*> TopRoots, releaseSuccessors(&DAG.EntrySU, StepNo); while (!RQ.empty()) { - DEBUG( - dbgs() << "\n=== Picking candidate, Step = " << StepNo << "\n" - "Ready queue:"; - for (auto &C : RQ) - dbgs() << ' ' << C.SU->NodeNum << "(P" << C.Priority << ')'; - dbgs() << '\n'; - ); + LLVM_DEBUG(dbgs() << "\n=== Picking candidate, Step = " << StepNo + << "\n" + "Ready queue:"; + for (auto &C + : RQ) dbgs() + << ' ' << C.SU->NodeNum << "(P" << C.Priority << ')'; + dbgs() << '\n';); auto C = pickCandidate(); assert(C); RQ.remove(*C); auto SU = C->SU; - DEBUG(dbgs() << "Selected "; SU->dump(&DAG)); + LLVM_DEBUG(dbgs() << "Selected "; SU->dump(&DAG)); releaseSuccessors(SU, StepNo); Schedule.push_back(SU); diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 12305446fa4..c0a6765df34 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -200,34 +200,30 @@ SUnit *GCNMaxOccupancySchedStrategy::pickNodeBidirectional(bool &IsTopNode) { setPolicy(TopPolicy, /*IsPostRA=*/false, Top, &Bot); // See if BotCand is still valid (because we previously scheduled from Top). - DEBUG(dbgs() << "Picking from Bot:\n"); + LLVM_DEBUG(dbgs() << "Picking from Bot:\n"); if (!BotCand.isValid() || BotCand.SU->isScheduled || BotCand.Policy != BotPolicy) { BotCand.reset(CandPolicy()); pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), BotCand); assert(BotCand.Reason != NoCand && "failed to find the first candidate"); } else { - DEBUG(traceCandidate(BotCand)); + LLVM_DEBUG(traceCandidate(BotCand)); } // Check if the top Q has a better candidate. - DEBUG(dbgs() << "Picking from Top:\n"); + LLVM_DEBUG(dbgs() << "Picking from Top:\n"); if (!TopCand.isValid() || TopCand.SU->isScheduled || TopCand.Policy != TopPolicy) { TopCand.reset(CandPolicy()); pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TopCand); assert(TopCand.Reason != NoCand && "failed to find the first candidate"); } else { - DEBUG(traceCandidate(TopCand)); + LLVM_DEBUG(traceCandidate(TopCand)); } // Pick best from BotCand and TopCand. - DEBUG( - dbgs() << "Top Cand: "; - traceCandidate(TopCand); - dbgs() << "Bot Cand: "; - traceCandidate(BotCand); - ); + LLVM_DEBUG(dbgs() << "Top Cand: "; traceCandidate(TopCand); + dbgs() << "Bot Cand: "; traceCandidate(BotCand);); SchedCandidate Cand; if (TopCand.Reason == BotCand.Reason) { Cand = BotCand; @@ -256,10 +252,7 @@ SUnit *GCNMaxOccupancySchedStrategy::pickNodeBidirectional(bool &IsTopNode) { } } } - DEBUG( - dbgs() << "Picking: "; - traceCandidate(Cand); - ); + LLVM_DEBUG(dbgs() << "Picking: "; traceCandidate(Cand);); IsTopNode = Cand.AtTop; return Cand.SU; @@ -305,7 +298,8 @@ SUnit *GCNMaxOccupancySchedStrategy::pickNode(bool &IsTopNode) { if (SU->isBottomReady()) Bot.removeReady(SU); - DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); + LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " + << *SU->getInstr()); return SU; } @@ -319,7 +313,7 @@ GCNScheduleDAGMILive::GCNScheduleDAGMILive(MachineSchedContext *C, MFI.getMaxWavesPerEU())), MinOccupancy(StartingOccupancy), Stage(0), RegionIdx(0) { - DEBUG(dbgs() << "Starting occupancy is " << StartingOccupancy << ".\n"); + LLVM_DEBUG(dbgs() << "Starting occupancy is " << StartingOccupancy << ".\n"); } void GCNScheduleDAGMILive::schedule() { @@ -339,12 +333,12 @@ void GCNScheduleDAGMILive::schedule() { if (LIS) { PressureBefore = Pressure[RegionIdx]; - DEBUG(dbgs() << "Pressure before scheduling:\nRegion live-ins:"; - GCNRPTracker::printLiveRegs(dbgs(), LiveIns[RegionIdx], MRI); - dbgs() << "Region live-in pressure: "; - llvm::getRegPressure(MRI, LiveIns[RegionIdx]).print(dbgs()); - dbgs() << "Region register pressure: "; - PressureBefore.print(dbgs())); + LLVM_DEBUG(dbgs() << "Pressure before scheduling:\nRegion live-ins:"; + GCNRPTracker::printLiveRegs(dbgs(), LiveIns[RegionIdx], MRI); + dbgs() << "Region live-in pressure: "; + llvm::getRegPressure(MRI, LiveIns[RegionIdx]).print(dbgs()); + dbgs() << "Region register pressure: "; + PressureBefore.print(dbgs())); } ScheduleDAGMILive::schedule(); @@ -357,12 +351,13 @@ void GCNScheduleDAGMILive::schedule() { GCNMaxOccupancySchedStrategy &S = (GCNMaxOccupancySchedStrategy&)*SchedImpl; auto PressureAfter = getRealRegPressure(); - DEBUG(dbgs() << "Pressure after scheduling: "; PressureAfter.print(dbgs())); + LLVM_DEBUG(dbgs() << "Pressure after scheduling: "; + PressureAfter.print(dbgs())); if (PressureAfter.getSGPRNum() <= S.SGPRCriticalLimit && PressureAfter.getVGPRNum() <= S.VGPRCriticalLimit) { Pressure[RegionIdx] = PressureAfter; - DEBUG(dbgs() << "Pressure in desired limits, done.\n"); + LLVM_DEBUG(dbgs() << "Pressure in desired limits, done.\n"); return; } unsigned WavesAfter = getMaxWaves(PressureAfter.getSGPRNum(), @@ -371,16 +366,16 @@ void GCNScheduleDAGMILive::schedule() { PressureBefore.getVGPRNum(), MF); WavesAfter = std::min(WavesAfter, MFI.getMaxWavesPerEU()); WavesBefore = std::min(WavesBefore, MFI.getMaxWavesPerEU()); - DEBUG(dbgs() << "Occupancy before scheduling: " << WavesBefore << - ", after " << WavesAfter << ".\n"); + LLVM_DEBUG(dbgs() << "Occupancy before scheduling: " << WavesBefore + << ", after " << WavesAfter << ".\n"); // We could not keep current target occupancy because of the just scheduled // region. Record new occupancy for next scheduling cycle. unsigned NewOccupancy = std::max(WavesAfter, WavesBefore); if (NewOccupancy < MinOccupancy) { MinOccupancy = NewOccupancy; - DEBUG(dbgs() << "Occupancy lowered for the function to " - << MinOccupancy << ".\n"); + LLVM_DEBUG(dbgs() << "Occupancy lowered for the function to " + << MinOccupancy << ".\n"); } if (WavesAfter >= WavesBefore) { @@ -388,7 +383,7 @@ void GCNScheduleDAGMILive::schedule() { return; } - DEBUG(dbgs() << "Attempting to revert scheduling.\n"); + LLVM_DEBUG(dbgs() << "Attempting to revert scheduling.\n"); RegionEnd = RegionBegin; for (MachineInstr *MI : Unsched) { if (MI->isDebugInstr()) @@ -418,7 +413,7 @@ void GCNScheduleDAGMILive::schedule() { } RegionEnd = MI->getIterator(); ++RegionEnd; - DEBUG(dbgs() << "Scheduling " << *MI); + LLVM_DEBUG(dbgs() << "Scheduling " << *MI); } RegionBegin = Unsched.front()->getIterator(); Regions[RegionIdx] = std::make_pair(RegionBegin, RegionEnd); @@ -493,7 +488,7 @@ void GCNScheduleDAGMILive::computeBlockPressure(const MachineBasicBlock *MBB) { void GCNScheduleDAGMILive::finalizeSchedule() { GCNMaxOccupancySchedStrategy &S = (GCNMaxOccupancySchedStrategy&)*SchedImpl; - DEBUG(dbgs() << "All regions recorded, starting actual scheduling.\n"); + LLVM_DEBUG(dbgs() << "All regions recorded, starting actual scheduling.\n"); LiveIns.resize(Regions.size()); Pressure.resize(Regions.size()); @@ -512,9 +507,10 @@ void GCNScheduleDAGMILive::finalizeSchedule() { if (!LIS || StartingOccupancy <= MinOccupancy) break; - DEBUG(dbgs() - << "Retrying function scheduling with lowest recorded occupancy " - << MinOccupancy << ".\n"); + LLVM_DEBUG( + dbgs() + << "Retrying function scheduling with lowest recorded occupancy " + << MinOccupancy << ".\n"); S.setTargetOccupancy(MinOccupancy); } @@ -540,12 +536,13 @@ void GCNScheduleDAGMILive::finalizeSchedule() { continue; } - DEBUG(dbgs() << "********** MI Scheduling **********\n"); - DEBUG(dbgs() << MF.getName() << ":" << printMBBReference(*MBB) << " " - << MBB->getName() << "\n From: " << *begin() << " To: "; - if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; - else dbgs() << "End"; - dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); + LLVM_DEBUG(dbgs() << "********** MI Scheduling **********\n"); + LLVM_DEBUG(dbgs() << MF.getName() << ":" << printMBBReference(*MBB) << " " + << MBB->getName() << "\n From: " << *begin() + << " To: "; + if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; + else dbgs() << "End"; + dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); schedule(); diff --git a/llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp b/llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp index 5e1ba6b506d..a6838875622 100644 --- a/llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp +++ b/llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp @@ -121,7 +121,7 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr &RootCFAlu, LaterInstCount = getCFAluSize(LatrCFAlu); unsigned CumuledInsts = RootInstCount + LaterInstCount; if (CumuledInsts >= TII->getMaxAlusPerClause()) { - DEBUG(dbgs() << "Excess inst counts\n"); + LLVM_DEBUG(dbgs() << "Excess inst counts\n"); return false; } if (RootCFAlu.getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE) @@ -139,7 +139,7 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr &RootCFAlu, RootCFAlu.getOperand(KBank0Idx).getImm() || LatrCFAlu.getOperand(KBank0LineIdx).getImm() != RootCFAlu.getOperand(KBank0LineIdx).getImm())) { - DEBUG(dbgs() << "Wrong KC0\n"); + LLVM_DEBUG(dbgs() << "Wrong KC0\n"); return false; } // Is KCache Bank 1 compatible ? @@ -155,7 +155,7 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr &RootCFAlu, RootCFAlu.getOperand(KBank1Idx).getImm() || LatrCFAlu.getOperand(KBank1LineIdx).getImm() != RootCFAlu.getOperand(KBank1LineIdx).getImm())) { - DEBUG(dbgs() << "Wrong KC0\n"); + LLVM_DEBUG(dbgs() << "Wrong KC0\n"); return false; } if (LatrCFAlu.getOperand(Mode0Idx).getImm()) { diff --git a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp index 0fbc254486d..b4ec8dfb343 100644 --- a/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp @@ -531,7 +531,7 @@ public: for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) { if (TII->usesTextureCache(*I) || TII->usesVertexCache(*I)) { - DEBUG(dbgs() << CfCount << ":"; I->dump();); + LLVM_DEBUG(dbgs() << CfCount << ":"; I->dump();); FetchClauses.push_back(MakeFetchClause(MBB, I)); CfCount++; LastAlu.back() = nullptr; @@ -549,7 +549,8 @@ public: switch (MI->getOpcode()) { case AMDGPU::CF_ALU_PUSH_BEFORE: if (RequiresWorkAround) { - DEBUG(dbgs() << "Applying bug work-around for ALU_PUSH_BEFORE\n"); + LLVM_DEBUG(dbgs() + << "Applying bug work-around for ALU_PUSH_BEFORE\n"); BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(AMDGPU::CF_PUSH_EG)) .addImm(CfCount + 1) .addImm(1); @@ -562,7 +563,7 @@ public: case AMDGPU::CF_ALU: I = MI; AluClauses.push_back(MakeALUClause(MBB, I)); - DEBUG(dbgs() << CfCount << ":"; MI->dump();); + LLVM_DEBUG(dbgs() << CfCount << ":"; MI->dump();); CfCount++; break; case AMDGPU::WHILELOOP: { @@ -597,7 +598,7 @@ public: .addImm(0) .addImm(0); IfThenElseStack.push_back(MIb); - DEBUG(dbgs() << CfCount << ":"; MIb->dump();); + LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); MI->eraseFromParent(); CfCount++; break; @@ -610,7 +611,7 @@ public: getHWInstrDesc(CF_ELSE)) .addImm(0) .addImm(0); - DEBUG(dbgs() << CfCount << ":"; MIb->dump();); + LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); IfThenElseStack.push_back(MIb); MI->eraseFromParent(); CfCount++; @@ -626,7 +627,7 @@ public: .addImm(CfCount + 1) .addImm(1); (void)MIb; - DEBUG(dbgs() << CfCount << ":"; MIb->dump();); + LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); CfCount++; } @@ -673,7 +674,7 @@ public: } default: if (TII->isExport(MI->getOpcode())) { - DEBUG(dbgs() << CfCount << ":"; MI->dump();); + LLVM_DEBUG(dbgs() << CfCount << ":"; MI->dump();); CfCount++; } break; diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp index f8d062ef52d..4bb4c037a44 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp @@ -78,7 +78,7 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { AllowSwitchFromAlu = true; } else { unsigned NeededWF = 62.5f / ALUFetchRationEstimate; - DEBUG( dbgs() << NeededWF << " approx. Wavefronts Required\n" ); + LLVM_DEBUG(dbgs() << NeededWF << " approx. Wavefronts Required\n"); // We assume the local GPR requirements to be "dominated" by the requirement // of the TEX clause (which consumes 128 bits regs) ; ALU inst before and // after TEX are indeed likely to consume or generate values from/for the @@ -124,26 +124,24 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { NextInstKind = IDOther; } - DEBUG( - if (SU) { - dbgs() << " ** Pick node **\n"; - SU->dump(DAG); - } else { - dbgs() << "NO NODE \n"; - for (unsigned i = 0; i < DAG->SUnits.size(); i++) { - const SUnit &S = DAG->SUnits[i]; - if (!S.isScheduled) - S.dump(DAG); - } - } - ); + LLVM_DEBUG(if (SU) { + dbgs() << " ** Pick node **\n"; + SU->dump(DAG); + } else { + dbgs() << "NO NODE \n"; + for (unsigned i = 0; i < DAG->SUnits.size(); i++) { + const SUnit &S = DAG->SUnits[i]; + if (!S.isScheduled) + S.dump(DAG); + } + }); return SU; } void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { if (NextInstKind != CurInstKind) { - DEBUG(dbgs() << "Instruction Type Switch\n"); + LLVM_DEBUG(dbgs() << "Instruction Type Switch\n"); if (NextInstKind != IDAlu) OccupedSlotsMask |= 31; CurEmitted = 0; @@ -172,8 +170,7 @@ void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { ++CurEmitted; } - - DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n"); + LLVM_DEBUG(dbgs() << CurEmitted << " Instructions Emitted in this clause\n"); if (CurInstKind != IDFetch) { MoveUnits(Pending[IDFetch], Available[IDFetch]); @@ -190,11 +187,11 @@ isPhysicalRegCopy(MachineInstr *MI) { } void R600SchedStrategy::releaseTopNode(SUnit *SU) { - DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG);); + LLVM_DEBUG(dbgs() << "Top Releasing "; SU->dump(DAG);); } void R600SchedStrategy::releaseBottomNode(SUnit *SU) { - DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG);); + LLVM_DEBUG(dbgs() << "Bottom Releasing "; SU->dump(DAG);); if (isPhysicalRegCopy(SU->getInstr())) { PhysicalRegCopy.push_back(SU); return; @@ -345,7 +342,7 @@ void R600SchedStrategy::LoadAlu() { } void R600SchedStrategy::PrepareNextSlot() { - DEBUG(dbgs() << "New Slot\n"); + LLVM_DEBUG(dbgs() << "New Slot\n"); assert (OccupedSlotsMask && "Slot wasn't filled"); OccupedSlotsMask = 0; // if (HwGen == R600Subtarget::NORTHERN_ISLANDS) diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index 4a14d95f1cc..cb46855f475 100644 --- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -228,20 +228,20 @@ MachineInstr *R600VectorRegMerger::RebuildVector( UpdatedUndef.erase(ChanPos); assert(!is_contained(UpdatedUndef, Chan) && "UpdatedUndef shouldn't contain Chan more than once!"); - DEBUG(dbgs() << " ->"; Tmp->dump();); + LLVM_DEBUG(dbgs() << " ->"; Tmp->dump();); (void)Tmp; SrcVec = DstReg; } MachineInstr *NewMI = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec); - DEBUG(dbgs() << " ->"; NewMI->dump();); + LLVM_DEBUG(dbgs() << " ->"; NewMI->dump();); - DEBUG(dbgs() << " Updating Swizzle:\n"); + LLVM_DEBUG(dbgs() << " Updating Swizzle:\n"); for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), E = MRI->use_instr_end(); It != E; ++It) { - DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->"); + LLVM_DEBUG(dbgs() << " "; (*It).dump(); dbgs() << " ->"); SwizzleInput(*It, RemapChan); - DEBUG((*It).dump()); + LLVM_DEBUG((*It).dump()); } RSI->Instr->eraseFromParent(); @@ -372,14 +372,14 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { if (!areAllUsesSwizzeable(Reg)) continue; - DEBUG({ + LLVM_DEBUG({ dbgs() << "Trying to optimize "; MI.dump(); }); RegSeqInfo CandidateRSI; std::vector<std::pair<unsigned, unsigned>> RemapChan; - DEBUG(dbgs() << "Using common slots...\n";); + LLVM_DEBUG(dbgs() << "Using common slots...\n";); if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) { // Remove CandidateRSI mapping RemoveMI(CandidateRSI.Instr); @@ -387,7 +387,7 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { trackRSI(RSI); continue; } - DEBUG(dbgs() << "Using free slots...\n";); + LLVM_DEBUG(dbgs() << "Using free slots...\n";); RemapChan.clear(); if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) { RemoveMI(CandidateRSI.Instr); diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp index 7340318d2d8..069e9dcb123 100644 --- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp @@ -236,7 +236,7 @@ public: if (ConsideredInstUsesAlreadyWrittenVectorElement && !TII->isVectorOnly(MI) && VLIW5) { isTransSlot = true; - DEBUG({ + LLVM_DEBUG({ dbgs() << "Considering as Trans Inst :"; MI.dump(); }); @@ -249,7 +249,7 @@ public: // Are the Constants limitations met ? CurrentPacketMIs.push_back(&MI); if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Couldn't pack :\n"; MI.dump(); dbgs() << "with the following packets :\n"; @@ -266,7 +266,7 @@ public: // Is there a BankSwizzle set that meet Read Port limitations ? if (!TII->fitsReadPortLimitations(CurrentPacketMIs, PV, BS, isTransSlot)) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Couldn't pack :\n"; MI.dump(); dbgs() << "with the following packets :\n"; diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp index 11fea5d6ee7..8ef4315e67f 100644 --- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp @@ -201,7 +201,7 @@ bool SIAnnotateControlFlow::isElse(PHINode *Phi) { // Erase "Phi" if it is not used any more void SIAnnotateControlFlow::eraseIfUnused(PHINode *Phi) { if (RecursivelyDeleteDeadPHINode(Phi)) { - DEBUG(dbgs() << "Erased unused condition phi\n"); + LLVM_DEBUG(dbgs() << "Erased unused condition phi\n"); } } diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index e26bc99bd4b..033d08a42b6 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -513,9 +513,9 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, if (MDT.dominates(MI1, MI2)) { if (!intereferes(MI2, MI1)) { - DEBUG(dbgs() << "Erasing from " - << printMBBReference(*MI2->getParent()) << " " - << *MI2); + LLVM_DEBUG(dbgs() + << "Erasing from " + << printMBBReference(*MI2->getParent()) << " " << *MI2); MI2->eraseFromParent(); Defs.erase(I2++); Changed = true; @@ -523,9 +523,9 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, } } else if (MDT.dominates(MI2, MI1)) { if (!intereferes(MI1, MI2)) { - DEBUG(dbgs() << "Erasing from " - << printMBBReference(*MI1->getParent()) << " " - << *MI1); + LLVM_DEBUG(dbgs() + << "Erasing from " + << printMBBReference(*MI1->getParent()) << " " << *MI1); MI1->eraseFromParent(); Defs.erase(I1++); Changed = true; @@ -541,11 +541,12 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, MachineBasicBlock::iterator I = MBB->getFirstNonPHI(); if (!intereferes(MI1, I) && !intereferes(MI2, I)) { - DEBUG(dbgs() << "Erasing from " - << printMBBReference(*MI1->getParent()) << " " << *MI1 - << "and moving from " - << printMBBReference(*MI2->getParent()) << " to " - << printMBBReference(*I->getParent()) << " " << *MI2); + LLVM_DEBUG(dbgs() + << "Erasing from " + << printMBBReference(*MI1->getParent()) << " " << *MI1 + << "and moving from " + << printMBBReference(*MI2->getParent()) << " to " + << printMBBReference(*I->getParent()) << " " << *MI2); I->getParent()->splice(I, MI2->getParent(), MI2); MI1->eraseFromParent(); Defs.erase(I1++); @@ -633,7 +634,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { if (!predsHasDivergentTerminator(MBB0, TRI) && !predsHasDivergentTerminator(MBB1, TRI)) { - DEBUG(dbgs() << "Not fixing PHI for uniform branch: " << MI << '\n'); + LLVM_DEBUG(dbgs() + << "Not fixing PHI for uniform branch: " << MI << '\n'); break; } } @@ -673,7 +675,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { SmallSet<unsigned, 8> Visited; if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) { - DEBUG(dbgs() << "Fixing PHI: " << MI); + LLVM_DEBUG(dbgs() << "Fixing PHI: " << MI); TII->moveToVALU(MI); } break; @@ -685,7 +687,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { continue; } - DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI); + LLVM_DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI); TII->moveToVALU(MI); break; @@ -696,7 +698,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); if (TRI->isSGPRClass(DstRC) && (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { - DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI); + LLVM_DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI); TII->moveToVALU(MI); } break; diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp index 7a3caf4db71..dec88084708 100644 --- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp @@ -58,7 +58,7 @@ bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) { if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) { MI.addOperand(MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); - DEBUG(dbgs() << "Add exec use to " << MI); + LLVM_DEBUG(dbgs() << "Add exec use to " << MI); Changed = true; } break; diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index e4f121368a4..d41d151492d 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -637,14 +637,14 @@ static bool tryFoldInst(const SIInstrInfo *TII, const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); if (Src1->isIdenticalTo(*Src0)) { - DEBUG(dbgs() << "Folded " << *MI << " into "); + LLVM_DEBUG(dbgs() << "Folded " << *MI << " into "); int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); if (Src2Idx != -1) MI->RemoveOperand(Src2Idx); MI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1)); mutateCopyOp(*MI, TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false))); - DEBUG(dbgs() << *MI << '\n'); + LLVM_DEBUG(dbgs() << *MI << '\n'); return true; } } @@ -685,7 +685,7 @@ void SIFoldOperands::foldInstOperand(MachineInstr &MI, // be folded due to multiple uses or operand constraints. if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) { - DEBUG(dbgs() << "Constant folded " << *UseMI <<'\n'); + LLVM_DEBUG(dbgs() << "Constant folded " << *UseMI << '\n'); // Some constant folding cases change the same immediate's use to a new // instruction, e.g. and x, 0 -> 0. Make sure we re-visit the user @@ -752,8 +752,9 @@ void SIFoldOperands::foldInstOperand(MachineInstr &MI, // copies. MRI->clearKillFlags(Fold.OpToFold->getReg()); } - DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " << - static_cast<int>(Fold.UseOpNo) << " of " << *Fold.UseMI << '\n'); + LLVM_DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " + << static_cast<int>(Fold.UseOpNo) << " of " + << *Fold.UseMI << '\n'); tryFoldInst(TII, Fold.UseMI); } else if (Fold.isCommuted()) { // Restoring instruction's original operand order if fold has failed. @@ -833,7 +834,8 @@ bool SIFoldOperands::tryFoldClamp(MachineInstr &MI) { if (!DefClamp) return false; - DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def << '\n'); + LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def + << '\n'); // Clamp is applied after omod, so it is OK if omod is set. DefClamp->setImm(1); @@ -956,7 +958,7 @@ bool SIFoldOperands::tryFoldOMod(MachineInstr &MI) { if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp)) return false; - DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def << '\n'); + LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def << '\n'); DefOMod->setImm(OMod); MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg()); diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index e6aaaf94751..0e1c2bc3172 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -350,9 +350,7 @@ public: void setWaitcnt(MachineInstr *WaitcntIn) { LfWaitcnt = WaitcntIn; } MachineInstr *getWaitcnt() const { return LfWaitcnt; } - void print() { - DEBUG(dbgs() << " iteration " << IterCnt << '\n';); - } + void print() { LLVM_DEBUG(dbgs() << " iteration " << IterCnt << '\n';); } private: // s_waitcnt added at the end of loop footer to stablize wait scores @@ -515,7 +513,7 @@ void BlockWaitcntBrackets::setExpScore(const MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned OpNo, int32_t Val) { RegInterval Interval = getRegInterval(MI, TII, MRI, TRI, OpNo, false); - DEBUG({ + LLVM_DEBUG({ const MachineOperand &Opnd = MI->getOperand(OpNo); assert(TRI->isVGPR(*MRI, Opnd.getReg())); }); @@ -1206,8 +1204,9 @@ void SIInsertWaitcnts::generateWaitcntInstBefore( ScoreBracket = BlockWaitcntBracketsMap[TBB].get(); } ScoreBracket->setRevisitLoop(true); - DEBUG(dbgs() << "set-revisit: Block" - << ContainingLoop->getHeader()->getNumber() << '\n';); + LLVM_DEBUG(dbgs() + << "set-revisit: Block" + << ContainingLoop->getHeader()->getNumber() << '\n';); } } @@ -1242,26 +1241,29 @@ void SIInsertWaitcnts::generateWaitcntInstBefore( if (insertSWaitInst) { if (OldWaitcnt && OldWaitcnt->getOpcode() == AMDGPU::S_WAITCNT) { if (ForceEmitZeroWaitcnts) - DEBUG(dbgs() << "Force emit s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n"); + LLVM_DEBUG( + dbgs() + << "Force emit s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n"); if (IsForceEmitWaitcnt) - DEBUG(dbgs() << "Force emit a s_waitcnt due to debug counter\n"); + LLVM_DEBUG(dbgs() + << "Force emit a s_waitcnt due to debug counter\n"); OldWaitcnt->getOperand(0).setImm(Enc); if (!OldWaitcnt->getParent()) MI.getParent()->insert(MI, OldWaitcnt); - DEBUG(dbgs() << "updateWaitcntInBlock\n" - << "Old Instr: " << MI << '\n' - << "New Instr: " << *OldWaitcnt << '\n'); + LLVM_DEBUG(dbgs() << "updateWaitcntInBlock\n" + << "Old Instr: " << MI << '\n' + << "New Instr: " << *OldWaitcnt << '\n'); } else { auto SWaitInst = BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT)) .addImm(Enc); TrackedWaitcntSet.insert(SWaitInst); - DEBUG(dbgs() << "insertWaitcntInBlock\n" - << "Old Instr: " << MI << '\n' - << "New Instr: " << *SWaitInst << '\n'); + LLVM_DEBUG(dbgs() << "insertWaitcntInBlock\n" + << "Old Instr: " << MI << '\n' + << "New Instr: " << *SWaitInst << '\n'); } } @@ -1670,7 +1672,7 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, BlockWaitcntBrackets *ScoreBrackets = BlockWaitcntBracketsMap[&Block].get(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Block" << Block.getNumber() << " ***"; ScoreBrackets->dump(); }); @@ -1731,7 +1733,7 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, ScoreBrackets->clearWaitcnt(); - DEBUG({ + LLVM_DEBUG({ Inst.print(dbgs()); ScoreBrackets->dump(); }); @@ -1771,7 +1773,7 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, if (ContainingLoop && isLoopBottom(ContainingLoop, &Block)) { LoopWaitcntData *WaitcntData = LoopWaitcntDataMap[ContainingLoop].get(); WaitcntData->print(); - DEBUG(dbgs() << '\n';); + LLVM_DEBUG(dbgs() << '\n';); // The iterative waitcnt insertion algorithm aims for optimal waitcnt // placement and doesn't always guarantee convergence for a loop. Each @@ -1811,7 +1813,7 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, } if (SWaitInst) { - DEBUG({ + LLVM_DEBUG({ SWaitInst->print(dbgs()); dbgs() << "\nAdjusted score board:"; ScoreBrackets->dump(); @@ -1896,8 +1898,8 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { if ((std::count(BlockWaitcntProcessedSet.begin(), BlockWaitcntProcessedSet.end(), &MBB) < Count)) { BlockWaitcntBracketsMap[&MBB]->setRevisitLoop(true); - DEBUG(dbgs() << "set-revisit: Block" - << ContainingLoop->getHeader()->getNumber() << '\n';); + LLVM_DEBUG(dbgs() << "set-revisit: Block" + << ContainingLoop->getHeader()->getNumber() << '\n';); } } @@ -1931,7 +1933,7 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) { } LoopWaitcntData *WaitcntData = LoopWaitcntDataMap[ContainingLoop].get(); WaitcntData->incIterCnt(); - DEBUG(dbgs() << "revisit: Block" << EntryBB->getNumber() << '\n';); + LLVM_DEBUG(dbgs() << "revisit: Block" << EntryBB->getNumber() << '\n';); continue; } else { LoopWaitcntData *WaitcntData = LoopWaitcntDataMap[ContainingLoop].get(); diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index e5304818afb..1ebc45dc9ee 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -553,7 +553,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair( CI.I->eraseFromParent(); CI.Paired->eraseFromParent(); - DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n'); + LLVM_DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n'); return Next; } @@ -631,7 +631,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair( CI.I->eraseFromParent(); CI.Paired->eraseFromParent(); - DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n'); + LLVM_DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n'); return Next; } @@ -950,7 +950,7 @@ bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) { assert(MRI->isSSA() && "Must be run on SSA"); - DEBUG(dbgs() << "Running SILoadStoreOptimizer\n"); + LLVM_DEBUG(dbgs() << "Running SILoadStoreOptimizer\n"); bool Modified = false; diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 0fd4c6bfed9..86f81136bc5 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -1207,7 +1207,7 @@ void SIScheduleBlockCreator::createBlocksForVariant(SISchedulerBlockCreatorVaria NextReservedID = 1; NextNonReservedID = DAGSize + 1; - DEBUG(dbgs() << "Coloring the graph\n"); + LLVM_DEBUG(dbgs() << "Coloring the graph\n"); if (BlockVariant == SISchedulerBlockCreatorVariant::LatenciesGrouped) colorHighLatenciesGroups(); @@ -1264,13 +1264,11 @@ void SIScheduleBlockCreator::createBlocksForVariant(SISchedulerBlockCreatorVaria SIScheduleBlock *Block = CurrentBlocks[i]; Block->finalizeUnits(); } - DEBUG( - dbgs() << "Blocks created:\n\n"; - for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) { - SIScheduleBlock *Block = CurrentBlocks[i]; - Block->printDebug(true); - } - ); + LLVM_DEBUG(dbgs() << "Blocks created:\n\n"; + for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) { + SIScheduleBlock *Block = CurrentBlocks[i]; + Block->printDebug(true); + }); } // Two functions taken from Codegen/MachineScheduler.cpp @@ -1290,7 +1288,7 @@ void SIScheduleBlockCreator::topologicalSort() { unsigned DAGSize = CurrentBlocks.size(); std::vector<int> WorkList; - DEBUG(dbgs() << "Topological Sort\n"); + LLVM_DEBUG(dbgs() << "Topological Sort\n"); WorkList.reserve(DAGSize); TopDownIndex2Block.resize(DAGSize); @@ -1337,11 +1335,11 @@ void SIScheduleBlockCreator::topologicalSort() { void SIScheduleBlockCreator::scheduleInsideBlocks() { unsigned DAGSize = CurrentBlocks.size(); - DEBUG(dbgs() << "\nScheduling Blocks\n\n"); + LLVM_DEBUG(dbgs() << "\nScheduling Blocks\n\n"); // We do schedule a valid scheduling such that a Block corresponds // to a range of instructions. - DEBUG(dbgs() << "First phase: Fast scheduling for Reg Liveness\n"); + LLVM_DEBUG(dbgs() << "First phase: Fast scheduling for Reg Liveness\n"); for (unsigned i = 0, e = DAGSize; i != e; ++i) { SIScheduleBlock *Block = CurrentBlocks[i]; Block->fastSchedule(); @@ -1395,7 +1393,7 @@ void SIScheduleBlockCreator::scheduleInsideBlocks() { Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); } - DEBUG(dbgs() << "Restoring MI Pos\n"); + LLVM_DEBUG(dbgs() << "Restoring MI Pos\n"); // Restore old ordering (which prevents a LIS->handleMove bug). for (unsigned i = PosOld.size(), e = 0; i != e; --i) { MachineBasicBlock::iterator POld = PosOld[i-1]; @@ -1409,12 +1407,10 @@ void SIScheduleBlockCreator::scheduleInsideBlocks() { } } - DEBUG( - for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) { - SIScheduleBlock *Block = CurrentBlocks[i]; - Block->printDebug(true); - } - ); + LLVM_DEBUG(for (unsigned i = 0, e = CurrentBlocks.size(); i != e; ++i) { + SIScheduleBlock *Block = CurrentBlocks[i]; + Block->printDebug(true); + }); } void SIScheduleBlockCreator::fillStats() { @@ -1565,13 +1561,10 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG, blockScheduled(Block); } - DEBUG( - dbgs() << "Block Order:"; - for (SIScheduleBlock* Block : BlocksScheduled) { - dbgs() << ' ' << Block->getID(); - } - dbgs() << '\n'; - ); + LLVM_DEBUG(dbgs() << "Block Order:"; for (SIScheduleBlock *Block + : BlocksScheduled) { + dbgs() << ' ' << Block->getID(); + } dbgs() << '\n';); } bool SIScheduleBlockScheduler::tryCandidateLatency(SIBlockSchedCandidate &Cand, @@ -1634,18 +1627,17 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() { maxVregUsage = VregCurrentUsage; if (SregCurrentUsage > maxSregUsage) maxSregUsage = SregCurrentUsage; - DEBUG( - dbgs() << "Picking New Blocks\n"; - dbgs() << "Available: "; - for (SIScheduleBlock* Block : ReadyBlocks) - dbgs() << Block->getID() << ' '; - dbgs() << "\nCurrent Live:\n"; - for (unsigned Reg : LiveRegs) - dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; - dbgs() << '\n'; - dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n'; - dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n'; - ); + LLVM_DEBUG(dbgs() << "Picking New Blocks\n"; dbgs() << "Available: "; + for (SIScheduleBlock *Block + : ReadyBlocks) dbgs() + << Block->getID() << ' '; + dbgs() << "\nCurrent Live:\n"; + for (unsigned Reg + : LiveRegs) dbgs() + << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; + dbgs() << '\n'; + dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n'; + dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n';); Cand.Block = nullptr; for (std::vector<SIScheduleBlock*>::iterator I = ReadyBlocks.begin(), @@ -1677,20 +1669,18 @@ SIScheduleBlock *SIScheduleBlockScheduler::pickBlock() { if (TryCand.Reason != NoCand) { Cand.setBest(TryCand); Best = I; - DEBUG(dbgs() << "Best Current Choice: " << Cand.Block->getID() << ' ' - << getReasonStr(Cand.Reason) << '\n'); + LLVM_DEBUG(dbgs() << "Best Current Choice: " << Cand.Block->getID() << ' ' + << getReasonStr(Cand.Reason) << '\n'); } } - DEBUG( - dbgs() << "Picking: " << Cand.Block->getID() << '\n'; - dbgs() << "Is a block with high latency instruction: " - << (Cand.IsHighLatency ? "yes\n" : "no\n"); - dbgs() << "Position of last high latency dependency: " - << Cand.LastPosHighLatParentScheduled << '\n'; - dbgs() << "VGPRUsageDiff: " << Cand.VGPRUsageDiff << '\n'; - dbgs() << '\n'; - ); + LLVM_DEBUG(dbgs() << "Picking: " << Cand.Block->getID() << '\n'; + dbgs() << "Is a block with high latency instruction: " + << (Cand.IsHighLatency ? "yes\n" : "no\n"); + dbgs() << "Position of last high latency dependency: " + << Cand.LastPosHighLatParentScheduled << '\n'; + dbgs() << "VGPRUsageDiff: " << Cand.VGPRUsageDiff << '\n'; + dbgs() << '\n';); Block = Cand.Block; ReadyBlocks.erase(Best); @@ -1939,13 +1929,10 @@ void SIScheduleDAGMI::schedule() { SmallVector<SUnit*, 8> TopRoots, BotRoots; SIScheduleBlockResult Best, Temp; - DEBUG(dbgs() << "Preparing Scheduling\n"); + LLVM_DEBUG(dbgs() << "Preparing Scheduling\n"); buildDAGWithRegPressure(); - DEBUG( - for(SUnit& SU : SUnits) - SU.dumpAll(this) - ); + LLVM_DEBUG(for (SUnit &SU : SUnits) SU.dumpAll(this)); topologicalSort(); findRootsAndBiasEdges(TopRoots, BotRoots); @@ -2047,15 +2034,15 @@ void SIScheduleDAGMI::schedule() scheduleMI(SU, true); - DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " - << *SU->getInstr()); + LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " + << *SU->getInstr()); } assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone."); placeDebugValues(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Final schedule for " << printMBBReference(*begin()->getParent()) << " ***\n"; dumpSchedule(); diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index ddf45bbccb9..b68df539771 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -243,11 +243,11 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { // Fold exec = COPY (S_AND_B64 reg, exec) -> exec = S_AND_B64 reg, exec if (CopyToExecInst->getOperand(1).isKill() && isLogicalOpOnExec(*PrepareExecInst) == CopyToExec) { - DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst); + LLVM_DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst); PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC); - DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n'); + LLVM_DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n'); CopyToExecInst->eraseFromParent(); } @@ -257,7 +257,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { if (isLiveOut(MBB, CopyToExec)) { // The copied register is live out and has a second use in another block. - DEBUG(dbgs() << "Exec copy source register is live out\n"); + LLVM_DEBUG(dbgs() << "Exec copy source register is live out\n"); continue; } @@ -269,7 +269,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { = std::next(CopyFromExecInst->getIterator()), JE = I->getIterator(); J != JE; ++J) { if (SaveExecInst && J->readsRegister(AMDGPU::EXEC, TRI)) { - DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n'); + LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n'); // Make sure this is inserted after any VALU ops that may have been // scheduled in between. SaveExecInst = nullptr; @@ -280,8 +280,8 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { if (J->modifiesRegister(CopyToExec, TRI)) { if (SaveExecInst) { - DEBUG(dbgs() << "Multiple instructions modify " - << printReg(CopyToExec, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Multiple instructions modify " + << printReg(CopyToExec, TRI) << '\n'); SaveExecInst = nullptr; break; } @@ -292,10 +292,11 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { if (ReadsCopyFromExec) { SaveExecInst = &*J; - DEBUG(dbgs() << "Found save exec op: " << *SaveExecInst << '\n'); + LLVM_DEBUG(dbgs() << "Found save exec op: " << *SaveExecInst << '\n'); continue; } else { - DEBUG(dbgs() << "Instruction does not read exec copy: " << *J << '\n'); + LLVM_DEBUG(dbgs() + << "Instruction does not read exec copy: " << *J << '\n'); break; } } else if (ReadsCopyFromExec && !SaveExecInst) { @@ -307,8 +308,8 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { // spill %sgpr0_sgpr1 // %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1 // - DEBUG(dbgs() << "Found second use of save inst candidate: " - << *J << '\n'); + LLVM_DEBUG(dbgs() << "Found second use of save inst candidate: " << *J + << '\n'); break; } @@ -321,7 +322,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) { if (!SaveExecInst) continue; - DEBUG(dbgs() << "Insert save exec op: " << *SaveExecInst << '\n'); + LLVM_DEBUG(dbgs() << "Insert save exec op: " << *SaveExecInst << '\n'); MachineOperand &Src0 = SaveExecInst->getOperand(1); MachineOperand &Src1 = SaveExecInst->getOperand(2); diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index b7bb80acb71..c9e3e5696f3 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -143,7 +143,8 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef()) break; - DEBUG(dbgs() << "Removing no effect instruction: " << *I << '\n'); + LLVM_DEBUG(dbgs() + << "Removing no effect instruction: " << *I << '\n'); for (auto &Op : I->operands()) { if (Op.isReg()) @@ -193,7 +194,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { !getOrExecSource(*NextLead, *TII, MRI)) continue; - DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n'); + LLVM_DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n'); auto SaveExec = getOrExecSource(*Lead, *TII, MRI); unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII); @@ -224,7 +225,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { break; } - DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n'); + LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n'); } if (SafeToReplace) { diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 7a56b4d1bd6..6f9d7522872 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -846,7 +846,7 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { void SIPeepholeSDWA::matchSDWAOperands(MachineBasicBlock &MBB) { for (MachineInstr &MI : MBB) { if (auto Operand = matchSDWAOperand(MI)) { - DEBUG(dbgs() << "Match: " << MI << "To: " << *Operand << '\n'); + LLVM_DEBUG(dbgs() << "Match: " << MI << "To: " << *Operand << '\n'); SDWAOperands[&MI] = std::move(Operand); ++NumSDWAPatternsFound; } @@ -901,7 +901,7 @@ bool SIPeepholeSDWA::isConvertibleToSDWA(const MachineInstr &MI, bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, const SDWAOperandsVector &SDWAOperands) { - DEBUG(dbgs() << "Convert instruction:" << MI); + LLVM_DEBUG(dbgs() << "Convert instruction:" << MI); // Convert to sdwa int SDWAOpcode; @@ -1050,7 +1050,7 @@ bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, // Apply all sdwa operand patterns. bool Converted = false; for (auto &Operand : SDWAOperands) { - DEBUG(dbgs() << *SDWAInst << "\nOperand: " << *Operand); + LLVM_DEBUG(dbgs() << *SDWAInst << "\nOperand: " << *Operand); // There should be no intesection between SDWA operands and potential MIs // e.g.: // v_and_b32 v0, 0xff, v1 -> src:v1 sel:BYTE_0 @@ -1071,7 +1071,7 @@ bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, return false; } - DEBUG(dbgs() << "\nInto:" << *SDWAInst << '\n'); + LLVM_DEBUG(dbgs() << "\nInto:" << *SDWAInst << '\n'); ++NumSDWAInstructionsPeepholed; MI.eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 33fd5a30791..3c4c3baf799 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -495,7 +495,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { } // We can shrink this instruction - DEBUG(dbgs() << "Shrinking " << MI); + LLVM_DEBUG(dbgs() << "Shrinking " << MI); MachineInstrBuilder Inst32 = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32)); @@ -539,9 +539,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { MI.eraseFromParent(); foldImmediates(*Inst32, TII, MRI); - DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n'); - - + LLVM_DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n'); } } return false; diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 89e5d56d1e0..7de132e0ed1 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -679,7 +679,8 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg, if (!isEntry && BI.Needs == StateWQM && BI.OutNeeds != StateExact) return; - DEBUG(dbgs() << "\nProcessing block " << printMBBReference(MBB) << ":\n"); + LLVM_DEBUG(dbgs() << "\nProcessing block " << printMBBReference(MBB) + << ":\n"); unsigned SavedWQMReg = 0; unsigned SavedNonWWMReg = 0; @@ -882,7 +883,7 @@ bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) { } } - DEBUG(printInfo()); + LLVM_DEBUG(printInfo()); lowerCopyInstrs(); diff --git a/llvm/lib/Target/ARC/ARCBranchFinalize.cpp b/llvm/lib/Target/ARC/ARCBranchFinalize.cpp index 9341e7bdda4..3b410fa383b 100644 --- a/llvm/lib/Target/ARC/ARCBranchFinalize.cpp +++ b/llvm/lib/Target/ARC/ARCBranchFinalize.cpp @@ -112,7 +112,7 @@ static unsigned getCmpForPseudo(MachineInstr *MI) { } void ARCBranchFinalize::replaceWithBRcc(MachineInstr *MI) const { - DEBUG(dbgs() << "Replacing pseudo branch with BRcc\n"); + LLVM_DEBUG(dbgs() << "Replacing pseudo branch with BRcc\n"); unsigned CC = getCCForBRcc(MI->getOperand(3).getImm()); if (CC != -1U) { BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), @@ -128,8 +128,8 @@ void ARCBranchFinalize::replaceWithBRcc(MachineInstr *MI) const { } void ARCBranchFinalize::replaceWithCmpBcc(MachineInstr *MI) const { - DEBUG(dbgs() << "Branch: " << *MI << "\n"); - DEBUG(dbgs() << "Replacing pseudo branch with Cmp + Bcc\n"); + LLVM_DEBUG(dbgs() << "Branch: " << *MI << "\n"); + LLVM_DEBUG(dbgs() << "Replacing pseudo branch with Cmp + Bcc\n"); BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(getCmpForPseudo(MI))) .addReg(MI->getOperand(1).getReg()) @@ -141,8 +141,8 @@ void ARCBranchFinalize::replaceWithCmpBcc(MachineInstr *MI) const { } bool ARCBranchFinalize::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "Running ARC Branch Finalize on " - << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Running ARC Branch Finalize on " << MF.getName() + << "\n"); std::vector<MachineInstr *> Branches; bool Changed = false; unsigned MaxSize = 0; @@ -156,7 +156,7 @@ bool ARCBranchFinalize::runOnMachineFunction(MachineFunction &MF) { for (auto &MI : MBB) { unsigned Size = TII->getInstSizeInBytes(MI); if (Size > 8 || Size == 0) { - DEBUG(dbgs() << "Unknown (or size 0) size for: " << MI << "\n"); + LLVM_DEBUG(dbgs() << "Unknown (or size 0) size for: " << MI << "\n"); } else { MaxSize += Size; } @@ -172,8 +172,8 @@ bool ARCBranchFinalize::runOnMachineFunction(MachineFunction &MF) { isInt<9>(MaxSize) ? replaceWithBRcc(P.first) : replaceWithCmpBcc(P.first); } - DEBUG(dbgs() << "Estimated function size for " << MF.getName() - << ": " << MaxSize << "\n"); + LLVM_DEBUG(dbgs() << "Estimated function size for " << MF.getName() << ": " + << MaxSize << "\n"); return Changed; } diff --git a/llvm/lib/Target/ARC/ARCFrameLowering.cpp b/llvm/lib/Target/ARC/ARCFrameLowering.cpp index 195a781950b..ca59cb2baaa 100644 --- a/llvm/lib/Target/ARC/ARCFrameLowering.cpp +++ b/llvm/lib/Target/ARC/ARCFrameLowering.cpp @@ -59,8 +59,8 @@ static void generateStackAdjustment(MachineBasicBlock &MBB, Positive = true; } - DEBUG(dbgs() << "Internal: adjust stack by: " << Amount << "," << AbsAmount - << "\n"); + LLVM_DEBUG(dbgs() << "Internal: adjust stack by: " << Amount << "," + << AbsAmount << "\n"); assert((AbsAmount % 4 == 0) && "Stack adjustments must be 4-byte aligned."); if (isUInt<6>(AbsAmount)) @@ -88,8 +88,7 @@ determineLastCalleeSave(const std::vector<CalleeSavedInfo> &CSI) { void ARCFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { - DEBUG(dbgs() << "Determine Callee Saves: " << MF.getName() - << "\n"); + LLVM_DEBUG(dbgs() << "Determine Callee Saves: " << MF.getName() << "\n"); TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); SavedRegs.set(ARC::BLINK); } @@ -115,7 +114,7 @@ void ARCFrameLowering::adjustStackToMatchRecords( /// registers onto the stack, when enough callee saved registers are required. void ARCFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { - DEBUG(dbgs() << "Emit Prologue: " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Emit Prologue: " << MF.getName() << "\n"); auto *AFI = MF.getInfo<ARCFunctionInfo>(); MachineModuleInfo &MMI = MF.getMMI(); MCContext &Context = MMI.getContext(); @@ -133,7 +132,7 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF, unsigned AlreadyAdjusted = 0; if (MF.getFunction().isVarArg()) { // Add in the varargs area here first. - DEBUG(dbgs() << "Varargs\n"); + LLVM_DEBUG(dbgs() << "Varargs\n"); unsigned VarArgsBytes = MFI.getObjectSize(AFI->getVarArgsFrameIndex()); BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) .addReg(ARC::SP) @@ -141,7 +140,7 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF, .addImm(VarArgsBytes); } if (hasFP(MF)) { - DEBUG(dbgs() << "Saving FP\n"); + LLVM_DEBUG(dbgs() << "Saving FP\n"); BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) .addReg(ARC::SP, RegState::Define) .addReg(ARC::FP) @@ -150,7 +149,7 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF, AlreadyAdjusted += 4; } if (UseSaveRestoreFunclet && Last > ARC::R14) { - DEBUG(dbgs() << "Creating store funclet.\n"); + LLVM_DEBUG(dbgs() << "Creating store funclet.\n"); // BL to __save_r13_to_<TRI->getRegAsmName()> StackSlotsUsedByFunclet = Last - ARC::R12; BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); @@ -166,20 +165,20 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF, } // If we haven't saved BLINK, but we need to...do that now. if (MFI.hasCalls() && !SavedBlink) { - DEBUG(dbgs() << "Creating save blink.\n"); + LLVM_DEBUG(dbgs() << "Creating save blink.\n"); BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); AlreadyAdjusted += 4; } if (AFI->MaxCallStackReq > 0) MFI.setStackSize(MFI.getStackSize() + AFI->MaxCallStackReq); // We have already saved some of the stack... - DEBUG(dbgs() << "Adjusting stack by: " - << (MFI.getStackSize() - AlreadyAdjusted) << "\n"); + LLVM_DEBUG(dbgs() << "Adjusting stack by: " + << (MFI.getStackSize() - AlreadyAdjusted) << "\n"); generateStackAdjustment(MBB, MBBI, *ST.getInstrInfo(), dl, -(MFI.getStackSize() - AlreadyAdjusted), ARC::SP); if (hasFP(MF)) { - DEBUG(dbgs() << "Setting FP from SP.\n"); + LLVM_DEBUG(dbgs() << "Setting FP from SP.\n"); BuildMI(MBB, MBBI, dl, TII->get(isUInt<6>(MFI.getStackSize()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm), @@ -235,7 +234,7 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF, /// registers onto the stack, when enough callee saved registers are required. void ARCFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - DEBUG(dbgs() << "Emit Epilogue: " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Emit Epilogue: " << MF.getName() << "\n"); auto *AFI = MF.getInfo<ARCFunctionInfo>(); const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); @@ -304,7 +303,7 @@ void ARCFrameLowering::emitEpilogue(MachineFunction &MF, // Relieve the varargs area if necessary. if (MF.getFunction().isVarArg()) { // Add in the varargs area here first. - DEBUG(dbgs() << "Varargs\n"); + LLVM_DEBUG(dbgs() << "Varargs\n"); unsigned VarArgsBytes = MFI.getObjectSize(AFI->getVarArgsFrameIndex()); BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::ADD_rru6)) .addReg(ARC::SP) @@ -334,16 +333,16 @@ bool ARCFrameLowering::assignCalleeSavedSpillSlots( if (hasFP(MF)) { // Create a fixed slot at for FP int StackObj = MFI.CreateFixedSpillStackObject(4, CurOffset, true); - DEBUG(dbgs() << "Creating fixed object (" << StackObj << ") for FP at " - << CurOffset << "\n"); + LLVM_DEBUG(dbgs() << "Creating fixed object (" << StackObj << ") for FP at " + << CurOffset << "\n"); (void)StackObj; CurOffset -= 4; } if (MFI.hasCalls() || (UseSaveRestoreFunclet && Last > ARC::R14)) { // Create a fixed slot for BLINK. int StackObj = MFI.CreateFixedSpillStackObject(4, CurOffset, true); - DEBUG(dbgs() << "Creating fixed object (" << StackObj << ") for BLINK at " - << CurOffset << "\n"); + LLVM_DEBUG(dbgs() << "Creating fixed object (" << StackObj + << ") for BLINK at " << CurOffset << "\n"); (void)StackObj; CurOffset -= 4; } @@ -366,12 +365,12 @@ bool ARCFrameLowering::assignCalleeSavedSpillSlots( continue; if (I.getFrameIdx() == 0) { I.setFrameIdx(MFI.CreateFixedSpillStackObject(4, CurOffset, true)); - DEBUG(dbgs() << "Creating fixed object (" << I.getFrameIdx() - << ") for other register at " << CurOffset << "\n"); + LLVM_DEBUG(dbgs() << "Creating fixed object (" << I.getFrameIdx() + << ") for other register at " << CurOffset << "\n"); } else { MFI.setObjectOffset(I.getFrameIdx(), CurOffset); - DEBUG(dbgs() << "Updating fixed object (" << I.getFrameIdx() - << ") for other register at " << CurOffset << "\n"); + LLVM_DEBUG(dbgs() << "Updating fixed object (" << I.getFrameIdx() + << ") for other register at " << CurOffset << "\n"); } CurOffset -= 4; } @@ -382,8 +381,8 @@ bool ARCFrameLowering::spillCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { - DEBUG(dbgs() << "Spill callee saved registers: " - << MBB.getParent()->getName() << "\n"); + LLVM_DEBUG(dbgs() << "Spill callee saved registers: " + << MBB.getParent()->getName() << "\n"); // There are routines for saving at least 3 registers (r13 to r15, etc.) unsigned Last = determineLastCalleeSave(CSI); if (UseSaveRestoreFunclet && Last > ARC::R14) { @@ -399,8 +398,8 @@ bool ARCFrameLowering::spillCalleeSavedRegisters( bool ARCFrameLowering::restoreCalleeSavedRegisters( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { - DEBUG(dbgs() << "Restore callee saved registers: " - << MBB.getParent()->getName() << "\n"); + LLVM_DEBUG(dbgs() << "Restore callee saved registers: " + << MBB.getParent()->getName() << "\n"); // There are routines for saving at least 3 registers (r13 to r15, etc.) unsigned Last = determineLastCalleeSave(CSI); if (UseSaveRestoreFunclet && Last > ARC::R14) { @@ -414,16 +413,17 @@ bool ARCFrameLowering::restoreCalleeSavedRegisters( void ARCFrameLowering::processFunctionBeforeFrameFinalized( MachineFunction &MF, RegScavenger *RS) const { const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); - DEBUG(dbgs() << "Process function before frame finalized: " - << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Process function before frame finalized: " + << MF.getName() << "\n"); MachineFrameInfo &MFI = MF.getFrameInfo(); - DEBUG(dbgs() << "Current stack size: " << MFI.getStackSize() << "\n"); + LLVM_DEBUG(dbgs() << "Current stack size: " << MFI.getStackSize() << "\n"); const TargetRegisterClass *RC = &ARC::GPR32RegClass; if (MFI.hasStackObjects()) { int RegScavFI = MFI.CreateStackObject( RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); RS->addScavengingFrameIndex(RegScavFI); - DEBUG(dbgs() << "Created scavenging index RegScavFI=" << RegScavFI << "\n"); + LLVM_DEBUG(dbgs() << "Created scavenging index RegScavFI=" << RegScavFI + << "\n"); } } @@ -440,7 +440,7 @@ static void emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator ARCFrameLowering::eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - DEBUG(dbgs() << "EmitCallFramePseudo: " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "EmitCallFramePseudo: " << MF.getName() << "\n"); const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); MachineInstr &Old = *I; DebugLoc dl = Old.getDebugLoc(); diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp index 5991838a15c..0ec953f341a 100644 --- a/llvm/lib/Target/ARC/ARCISelLowering.cpp +++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp @@ -486,8 +486,8 @@ SDValue ARCTargetLowering::LowerCallArguments( EVT RegVT = VA.getLocVT(); switch (RegVT.getSimpleVT().SimpleTy) { default: { - DEBUG(errs() << "LowerFormalArguments Unhandled argument type: " - << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); + LLVM_DEBUG(errs() << "LowerFormalArguments Unhandled argument type: " + << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); llvm_unreachable("Unhandled LowerFormalArguments type."); } case MVT::i32: diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp index f8d14d243f4..a8084f16893 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp +++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp @@ -298,8 +298,8 @@ void ARCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, "Only support 4-byte stores to stack now."); assert(ARC::GPR32RegClass.hasSubClassEq(RC) && "Only support GPR32 stores to stack now."); - DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI) - << " to FrameIndex=" << FrameIndex << "\n"); + LLVM_DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI) + << " to FrameIndex=" << FrameIndex << "\n"); BuildMI(MBB, I, dl, get(ARC::ST_rs9)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIndex) @@ -325,8 +325,8 @@ void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, "Only support 4-byte loads from stack now."); assert(ARC::GPR32RegClass.hasSubClassEq(RC) && "Only support GPR32 stores to stack now."); - DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI) - << " from FrameIndex=" << FrameIndex << "\n"); + LLVM_DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI) + << " from FrameIndex=" << FrameIndex << "\n"); BuildMI(MBB, I, dl, get(ARC::LD_rs9)) .addReg(DestReg, RegState::Define) .addFrameIndex(FrameIndex) diff --git a/llvm/lib/Target/ARC/ARCRegisterInfo.cpp b/llvm/lib/Target/ARC/ARCRegisterInfo.cpp index cb9f89d3499..38ea3c93a2d 100644 --- a/llvm/lib/Target/ARC/ARCRegisterInfo.cpp +++ b/llvm/lib/Target/ARC/ARCRegisterInfo.cpp @@ -66,9 +66,9 @@ static void ReplaceFrameIndex(MachineBasicBlock::iterator II, MBB.getParent()->getSubtarget().getRegisterInfo(); BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); assert(BaseReg && "Register scavenging failed."); - DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) - << " for FrameReg=" << printReg(FrameReg, TRI) - << "+Offset=" << Offset << "\n"); + LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) + << " for FrameReg=" << printReg(FrameReg, TRI) + << "+Offset=" << Offset << "\n"); (void)TRI; RS->setRegUsed(BaseReg); } @@ -88,7 +88,7 @@ static void ReplaceFrameIndex(MachineBasicBlock::iterator II, assert((Offset % 2 == 0) && "LDH needs 2 byte alignment."); case ARC::LDB_rs9: case ARC::LDB_X_rs9: - DEBUG(dbgs() << "Building LDFI\n"); + LLVM_DEBUG(dbgs() << "Building LDFI\n"); BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg) .addReg(BaseReg, KillState) .addImm(Offset) @@ -99,7 +99,7 @@ static void ReplaceFrameIndex(MachineBasicBlock::iterator II, case ARC::STH_rs9: assert((Offset % 2 == 0) && "STH needs 2 byte alignment."); case ARC::STB_rs9: - DEBUG(dbgs() << "Building STFI\n"); + LLVM_DEBUG(dbgs() << "Building STFI\n"); BuildMI(MBB, II, dl, TII.get(MI.getOpcode())) .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) .addReg(BaseReg, KillState) @@ -107,7 +107,7 @@ static void ReplaceFrameIndex(MachineBasicBlock::iterator II, .addMemOperand(*MI.memoperands_begin()); break; case ARC::GETFI: - DEBUG(dbgs() << "Building GETFI\n"); + LLVM_DEBUG(dbgs() << "Building GETFI\n"); BuildMI(MBB, II, dl, TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm)) .addReg(Reg, RegState::Define) @@ -175,14 +175,14 @@ void ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int StackSize = MF.getFrameInfo().getStackSize(); int LocalFrameSize = MF.getFrameInfo().getLocalFrameSize(); - DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n"); - DEBUG(dbgs() << "<--------->\n"); - DEBUG(dbgs() << MI << "\n"); - DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n"); - DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n"); - DEBUG(dbgs() << "FrameOffset : " << Offset << "\n"); - DEBUG(dbgs() << "StackSize : " << StackSize << "\n"); - DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n"); + LLVM_DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "<--------->\n"); + LLVM_DEBUG(dbgs() << MI << "\n"); + LLVM_DEBUG(dbgs() << "FrameIndex : " << FrameIndex << "\n"); + LLVM_DEBUG(dbgs() << "ObjSize : " << ObjSize << "\n"); + LLVM_DEBUG(dbgs() << "FrameOffset : " << Offset << "\n"); + LLVM_DEBUG(dbgs() << "StackSize : " << StackSize << "\n"); + LLVM_DEBUG(dbgs() << "LocalFrameSize : " << LocalFrameSize << "\n"); (void)LocalFrameSize; // Special handling of DBG_VALUE instructions. @@ -200,8 +200,8 @@ void ARCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // ldb needs no alignment, // ldh needs 2 byte alignment // ld needs 4 byte alignment - DEBUG(dbgs() << "Offset : " << Offset << "\n" - << "<--------->\n"); + LLVM_DEBUG(dbgs() << "Offset : " << Offset << "\n" + << "<--------->\n"); unsigned Reg = MI.getOperand(0).getReg(); assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); diff --git a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp index 3280d5ee6cf..3fc5a033dd5 100644 --- a/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp +++ b/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp @@ -122,7 +122,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 32) { - DEBUG(dbgs() << "Not a GPR32 register."); + LLVM_DEBUG(dbgs() << "Not a GPR32 register."); return MCDisassembler::Fail; } @@ -222,7 +222,7 @@ static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, unsigned SrcC, DstB, LImm; DstB = decodeBField(Insn); if (DstB != 62) { - DEBUG(dbgs() << "Decoding StLImm found non-limm register."); + LLVM_DEBUG(dbgs() << "Decoding StLImm found non-limm register."); return MCDisassembler::Fail; } SrcC = decodeCField(Insn); @@ -237,10 +237,10 @@ static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, const void *Decoder) { unsigned DstA, SrcB, LImm; - DEBUG(dbgs() << "Decoding LdLImm:\n"); + LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n"); SrcB = decodeBField(Insn); if (SrcB != 62) { - DEBUG(dbgs() << "Decoding LdLImm found non-limm register."); + LLVM_DEBUG(dbgs() << "Decoding LdLImm found non-limm register."); return MCDisassembler::Fail; } DstA = decodeAField(Insn); @@ -255,13 +255,13 @@ static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, const void *Decoder) { unsigned DstA, SrcB; - DEBUG(dbgs() << "Decoding LdRLimm\n"); + LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n"); DstA = decodeAField(Insn); DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder); SrcB = decodeBField(Insn); DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder); if (decodeCField(Insn) != 62) { - DEBUG(dbgs() << "Decoding LdRLimm found non-limm register."); + LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register."); return MCDisassembler::Fail; } Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32))); @@ -271,7 +271,7 @@ static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, const void *Decoder) { - DEBUG(dbgs() << "Decoding MOV_S h-register\n"); + LLVM_DEBUG(dbgs() << "Decoding MOV_S h-register\n"); using Field = decltype(Insn); Field h = fieldFromInstruction(Insn, 5, 3) | (fieldFromInstruction(Insn, 0, 2) << 3); @@ -322,10 +322,10 @@ DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, Result = decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI); if (Success == Result) { - DEBUG(dbgs() << "Successfully decoded 64-bit instruction."); + LLVM_DEBUG(dbgs() << "Successfully decoded 64-bit instruction."); return Result; } - DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit."); + LLVM_DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit."); } uint32_t Insn32; if (!readInstruction32(Bytes, Address, Size, Insn32)) { @@ -342,10 +342,12 @@ DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, Result = decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI); if (Success == Result) { - DEBUG(dbgs() << "Successfully decoded 16-bit instruction with limm."); + LLVM_DEBUG( + dbgs() << "Successfully decoded 16-bit instruction with limm."); return Result; } - DEBUG(dbgs() << "Not a 16-bit instruction with limm, try without it."); + LLVM_DEBUG( + dbgs() << "Not a 16-bit instruction with limm, try without it."); } uint32_t Insn16; diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp index 16d5f74d19e..b7f7cb20315 100644 --- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp +++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp @@ -180,7 +180,7 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) { SmallVector<MachineInstr *, 8> Front; DeadInstr.insert(MI); - DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n"); + LLVM_DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n"); Front.push_back(MI); while (Front.size() != 0) { @@ -232,7 +232,7 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) { if (!IsDead) continue; - DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); + LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); DeadInstr.insert(Def); } } @@ -264,7 +264,7 @@ unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) { // Is it a subreg copy of ssub_0? if (EC && EC->isCopy() && EC->getOperand(1).getSubReg() == ARM::ssub_0) { - DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI); + LLVM_DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI); // Find the thing we're subreg copying out of - is it of the same // regclass as DPRMI? (i.e. a DPR or QPR). @@ -272,8 +272,8 @@ unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) { const TargetRegisterClass *TRC = MRI->getRegClass(MI->getOperand(1).getReg()); if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { - DEBUG(dbgs() << "Subreg copy is compatible - returning "); - DEBUG(dbgs() << printReg(FullReg) << "\n"); + LLVM_DEBUG(dbgs() << "Subreg copy is compatible - returning "); + LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n"); eraseInstrWithNoUses(MI); return FullReg; } @@ -387,7 +387,7 @@ void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI, continue; Front.push_back(NewMI); } else { - DEBUG(dbgs() << "Found partial copy" << *MI <<"\n"); + LLVM_DEBUG(dbgs() << "Found partial copy" << *MI << "\n"); Outs.push_back(MI); } } @@ -642,9 +642,8 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) { // to find. MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); - DEBUG(dbgs() << "Replacing operand " - << **I << " with " - << printReg(NewReg) << "\n"); + LLVM_DEBUG(dbgs() << "Replacing operand " << **I << " with " + << printReg(NewReg) << "\n"); (*I)->substVirtReg(NewReg, 0, *TRI); } } @@ -668,7 +667,7 @@ bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) { MRI = &Fn.getRegInfo(); bool Modified = false; - DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n"); + LLVM_DEBUG(dbgs() << "Running on function " << Fn.getName() << "\n"); DeadInstr.clear(); Replacements.clear(); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index efe96f8d1b0..505588f1722 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1469,7 +1469,7 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return false; // All clear, widen the COPY. - DEBUG(dbgs() << "widening: " << MI); + LLVM_DEBUG(dbgs() << "widening: " << MI); MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg @@ -1498,7 +1498,7 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MI.addRegisterKilled(SrcRegS, TRI, true); } - DEBUG(dbgs() << "replaced by: " << MI); + LLVM_DEBUG(dbgs() << "replaced by: " << MI); return true; } diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 4b9a4376adf..43e8b7d66c6 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -838,10 +838,10 @@ bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, auto AFI = MF->getInfo<ARMFunctionInfo>(); auto It = AFI->getCoalescedWeight(MBB); - DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " - << It->second << "\n"); - DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " - << NewRCWeight.RegWeight << "\n"); + LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " + << It->second << "\n"); + LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " + << NewRCWeight.RegWeight << "\n"); // This number is the largest round number that which meets the criteria: // (1) addresses PR18825 diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index 1e3655aac89..de08eb8c698 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -302,7 +302,7 @@ void ARMConstantIslands::verify() { return BBInfo[LHS.getNumber()].postOffset() < BBInfo[RHS.getNumber()].postOffset(); })); - DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n"); + LLVM_DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n"); for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) { CPUser &U = CPUsers[i]; unsigned UserOffset = getUserOffset(U); @@ -310,12 +310,12 @@ void ARMConstantIslands::verify() { // adjustment. if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getMaxDisp()+2, U.NegOk, /* DoDump = */ true)) { - DEBUG(dbgs() << "OK\n"); + LLVM_DEBUG(dbgs() << "OK\n"); continue; } - DEBUG(dbgs() << "Out of range.\n"); + LLVM_DEBUG(dbgs() << "Out of range.\n"); dumpBBs(); - DEBUG(MF->dump()); + LLVM_DEBUG(MF->dump()); llvm_unreachable("Constant pool entry out of range!"); } #endif @@ -324,7 +324,7 @@ void ARMConstantIslands::verify() { #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// print block size and offset information - debugging LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() { - DEBUG({ + LLVM_DEBUG({ for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) { const BasicBlockInfo &BBI = BBInfo[J]; dbgs() << format("%08x %bb.%u\t", BBI.Offset, J) @@ -341,9 +341,9 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { MF = &mf; MCP = mf.getConstantPool(); - DEBUG(dbgs() << "***** ARMConstantIslands: " - << MCP->getConstants().size() << " CP entries, aligned to " - << MCP->getConstantPoolAlignment() << " bytes *****\n"); + LLVM_DEBUG(dbgs() << "***** ARMConstantIslands: " + << MCP->getConstants().size() << " CP entries, aligned to " + << MCP->getConstantPoolAlignment() << " bytes *****\n"); STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget()); TII = STI->getInstrInfo(); @@ -394,7 +394,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { // constant pool users. initializeFunctionInfo(CPEMIs); CPEMIs.clear(); - DEBUG(dumpBBs()); + LLVM_DEBUG(dumpBBs()); // Functions with jump tables need an alignment of 4 because they use the ADR // instruction, which aligns the PC to 4 bytes before adding an offset. @@ -408,7 +408,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { // is no change. unsigned NoCPIters = 0, NoBRIters = 0; while (true) { - DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n'); + LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n'); bool CPChange = false; for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) // For most inputs, it converges in no more than 5 iterations. @@ -417,19 +417,19 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { CPChange |= handleConstantPoolUser(i, NoCPIters >= CPMaxIteration / 2); if (CPChange && ++NoCPIters > CPMaxIteration) report_fatal_error("Constant Island pass failed to converge!"); - DEBUG(dumpBBs()); + LLVM_DEBUG(dumpBBs()); // Clear NewWaterList now. If we split a block for branches, it should // appear as "new water" for the next iteration of constant pool placement. NewWaterList.clear(); - DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n'); + LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n'); bool BRChange = false; for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) BRChange |= fixupImmediateBr(ImmBranches[i]); if (BRChange && ++NoBRIters > 30) report_fatal_error("Branch Fix Up pass failed to converge!"); - DEBUG(dumpBBs()); + LLVM_DEBUG(dumpBBs()); if (!CPChange && !BRChange) break; @@ -465,7 +465,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { } } - DEBUG(dbgs() << '\n'; dumpBBs()); + LLVM_DEBUG(dbgs() << '\n'; dumpBBs()); BBInfo.clear(); WaterList.clear(); @@ -534,10 +534,10 @@ ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) // Add a new CPEntry, but no corresponding CPUser yet. CPEntries.emplace_back(1, CPEntry(CPEMI, i)); ++NumCPEs; - DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " - << Size << ", align = " << Align <<'\n'); + LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " + << Size << ", align = " << Align << '\n'); } - DEBUG(BB->dump()); + LLVM_DEBUG(BB->dump()); } /// Do initial placement of the jump tables. Because Thumb2's TBB and TBH @@ -1071,7 +1071,7 @@ bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, unsigned CPEOffset = getOffsetOf(CPEMI); if (DoDump) { - DEBUG({ + LLVM_DEBUG({ unsigned Block = MI->getParent()->getNumber(); const BasicBlockInfo &BBI = BBInfo[Block]; dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm() @@ -1164,7 +1164,7 @@ int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) { // Check to see if the CPE is already in-range. if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk, true)) { - DEBUG(dbgs() << "In range\n"); + LLVM_DEBUG(dbgs() << "In range\n"); return 1; } @@ -1180,8 +1180,8 @@ int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) { continue; if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(), U.NegOk)) { - DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" - << CPEs[i].CPI << "\n"); + LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" + << CPEs[i].CPI << "\n"); // Point the CPUser node to the replacement U.CPEMI = CPEs[i].CPEMI; // Change the CPI in the instruction operand to refer to the clone. @@ -1266,8 +1266,8 @@ bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset, // This is the least amount of required padding seen so far. BestGrowth = Growth; WaterIter = IP; - DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) - << " Growth=" << Growth << '\n'); + LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) + << " Growth=" << Growth << '\n'); if (CloserWater && WaterBB == U.MI->getParent()) return true; @@ -1310,8 +1310,8 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta; if (isOffsetInRange(UserOffset, CPEOffset, U)) { - DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB) - << format(", expected CPE offset %#x\n", CPEOffset)); + LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB) + << format(", expected CPE offset %#x\n", CPEOffset)); NewMBB = &*++UserMBB->getIterator(); // Add an unconditional branch from UserMBB to fallthrough block. Record // it for branch lengthening; this new branch will not get out of range, @@ -1354,18 +1354,17 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, unsigned KnownBits = UserBBI.internalKnownBits(); unsigned UPad = UnknownPadding(LogAlign, KnownBits); unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad; - DEBUG(dbgs() << format("Split in middle of big block before %#x", - BaseInsertOffset)); + LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x", + BaseInsertOffset)); // The 4 in the following is for the unconditional branch we'll be inserting // (allows for long branch on Thumb1). Alignment of the island is handled // inside isOffsetInRange. BaseInsertOffset -= 4; - DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset) - << " la=" << LogAlign - << " kb=" << KnownBits - << " up=" << UPad << '\n'); + LLVM_DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset) + << " la=" << LogAlign << " kb=" << KnownBits + << " up=" << UPad << '\n'); // This could point off the end of the block if we've already got constant // pool entries following this block; only the last one is in the water list. @@ -1378,7 +1377,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, BaseInsertOffset = std::max(UserBBI.postOffset() - UPad - 8, UserOffset + TII->getInstSizeInBytes(*UserMI) + 1); - DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset)); + LLVM_DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset)); } unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad + CPEMI->getOperand(2).getImm(); @@ -1422,8 +1421,8 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, } // We really must not split an IT block. - DEBUG(unsigned PredReg; - assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL)); + LLVM_DEBUG(unsigned PredReg; assert( + !isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL)); NewMBB = splitBlockBeforeInstr(&*MI); } @@ -1457,7 +1456,7 @@ bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex, MachineBasicBlock *NewMBB; water_iterator IP; if (findAvailableWater(U, UserOffset, IP, CloserWater)) { - DEBUG(dbgs() << "Found water in range\n"); + LLVM_DEBUG(dbgs() << "Found water in range\n"); MachineBasicBlock *WaterBB = *IP; // If the original WaterList entry was "new water" on this iteration, @@ -1470,7 +1469,7 @@ bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex, NewMBB = &*++WaterBB->getIterator(); } else { // No water found. - DEBUG(dbgs() << "No water found\n"); + LLVM_DEBUG(dbgs() << "No water found\n"); createNewWater(CPUserIndex, UserOffset, NewMBB); // splitBlockBeforeInstr adds to WaterList, which is important when it is @@ -1533,8 +1532,9 @@ bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex, break; } - DEBUG(dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI - << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset)); + LLVM_DEBUG( + dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI + << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset)); return true; } @@ -1589,11 +1589,11 @@ bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned BrOffset = getOffsetOf(MI) + PCAdj; unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; - DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) - << " from " << printMBBReference(*MI->getParent()) - << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) - << " to " << DestOffset << " offset " - << int(DestOffset - BrOffset) << "\t" << *MI); + LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) + << " from " << printMBBReference(*MI->getParent()) + << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) + << " to " << DestOffset << " offset " + << int(DestOffset - BrOffset) << "\t" << *MI); if (BrOffset <= DestOffset) { // Branch before the Dest. @@ -1640,7 +1640,7 @@ ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) { HasFarJump = true; ++NumUBrFixed; - DEBUG(dbgs() << " Changed B to long jump " << *MI); + LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI); return true; } @@ -1684,8 +1684,9 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) { // b L1 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB(); if (isBBInRange(MI, NewDest, Br.MaxDisp)) { - DEBUG(dbgs() << " Invert Bcc condition and swap its destination with " - << *BMI); + LLVM_DEBUG( + dbgs() << " Invert Bcc condition and swap its destination with " + << *BMI); BMI->getOperand(0).setMBB(DestBB); MI->getOperand(0).setMBB(NewDest); MI->getOperand(1).setImm(CC); @@ -1711,9 +1712,9 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) { } MachineBasicBlock *NextBB = &*++MBB->getIterator(); - DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) - << " also invert condition and change dest. to " - << printMBBReference(*NextBB) << "\n"); + LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) + << " also invert condition and change dest. to " + << printMBBReference(*NextBB) << "\n"); // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. @@ -1806,7 +1807,7 @@ bool ARMConstantIslands::optimizeThumb2Instructions() { // FIXME: Check if offset is multiple of scale if scale is not 4. if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) { - DEBUG(dbgs() << "Shrink: " << *U.MI); + LLVM_DEBUG(dbgs() << "Shrink: " << *U.MI); U.MI->setDesc(TII->get(NewOpc)); MachineBasicBlock *MBB = U.MI->getParent(); BBInfo[MBB->getNumber()].Size -= 2; @@ -1850,7 +1851,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() { unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale; MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB(); if (isBBInRange(Br.MI, DestBB, MaxOffs)) { - DEBUG(dbgs() << "Shrink branch: " << *Br.MI); + LLVM_DEBUG(dbgs() << "Shrink branch: " << *Br.MI); Br.MI->setDesc(TII->get(NewOpc)); MachineBasicBlock *MBB = Br.MI->getParent(); BBInfo[MBB->getNumber()].Size -= 2; @@ -1894,7 +1895,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() { CmpMI->getOperand(1).getImm() == 0 && isARMLowRegister(Reg)) { MachineBasicBlock *MBB = Br.MI->getParent(); - DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI); + LLVM_DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI); MachineInstr *NewBR = BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc)) .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags()); @@ -2063,7 +2064,7 @@ static void RemoveDeadAddBetweenLEAAndJT(MachineInstr *LEAMI, } } - DEBUG(dbgs() << "Removing Dead Add: " << *RemovableAdd); + LLVM_DEBUG(dbgs() << "Removing Dead Add: " << *RemovableAdd); RemovableAdd->eraseFromParent(); DeadSize += 4; } @@ -2209,7 +2210,7 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() { DeadSize += 4; } - DEBUG(dbgs() << "Shrink JT: " << *MI); + LLVM_DEBUG(dbgs() << "Shrink JT: " << *MI); MachineInstr *CPEMI = User.CPEMI; unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT; if (!isThumb2) @@ -2223,7 +2224,7 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() { .addReg(IdxReg, getKillRegState(IdxRegKill)) .addJumpTableIndex(JTI, JTOP.getTargetFlags()) .addImm(CPEMI->getOperand(0).getImm()); - DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI); unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH; CPEMI->setDesc(TII->get(JTOpc)); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 720070fe650..1b2c845c7b5 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1812,34 +1812,36 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) { if (!MF.getRegInfo().isLiveIn(Reg)) { --EntryRegDeficit; - DEBUG(dbgs() << printReg(Reg, TRI) - << " is unused argument register, EntryRegDeficit = " - << EntryRegDeficit << "\n"); + LLVM_DEBUG(dbgs() + << printReg(Reg, TRI) + << " is unused argument register, EntryRegDeficit = " + << EntryRegDeficit << "\n"); } } // Unused return registers can be clobbered in the epilogue for free. int ExitRegDeficit = AFI->getReturnRegsCount() - 4; - DEBUG(dbgs() << AFI->getReturnRegsCount() - << " return regs used, ExitRegDeficit = " << ExitRegDeficit - << "\n"); + LLVM_DEBUG(dbgs() << AFI->getReturnRegsCount() + << " return regs used, ExitRegDeficit = " + << ExitRegDeficit << "\n"); int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit); - DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n"); + LLVM_DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n"); // r4-r6 can be used in the prologue if they are pushed by the first push // instruction. for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { if (SavedRegs.test(Reg)) { --RegDeficit; - DEBUG(dbgs() << printReg(Reg, TRI) - << " is saved low register, RegDeficit = " << RegDeficit - << "\n"); + LLVM_DEBUG(dbgs() << printReg(Reg, TRI) + << " is saved low register, RegDeficit = " + << RegDeficit << "\n"); } else { AvailableRegs.push_back(Reg); - DEBUG(dbgs() - << printReg(Reg, TRI) - << " is non-saved low register, adding to AvailableRegs\n"); + LLVM_DEBUG( + dbgs() + << printReg(Reg, TRI) + << " is non-saved low register, adding to AvailableRegs\n"); } } @@ -1847,12 +1849,13 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, if (!HasFP) { if (SavedRegs.test(ARM::R7)) { --RegDeficit; - DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = " - << RegDeficit << "\n"); + LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = " + << RegDeficit << "\n"); } else { AvailableRegs.push_back(ARM::R7); - DEBUG(dbgs() - << "%r7 is non-saved low register, adding to AvailableRegs\n"); + LLVM_DEBUG( + dbgs() + << "%r7 is non-saved low register, adding to AvailableRegs\n"); } } @@ -1860,9 +1863,9 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) { if (SavedRegs.test(Reg)) { ++RegDeficit; - DEBUG(dbgs() << printReg(Reg, TRI) - << " is saved high register, RegDeficit = " << RegDeficit - << "\n"); + LLVM_DEBUG(dbgs() << printReg(Reg, TRI) + << " is saved high register, RegDeficit = " + << RegDeficit << "\n"); } } @@ -1874,11 +1877,11 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, MF.getFrameInfo().isReturnAddressTaken())) { if (SavedRegs.test(ARM::LR)) { --RegDeficit; - DEBUG(dbgs() << "%lr is saved register, RegDeficit = " << RegDeficit - << "\n"); + LLVM_DEBUG(dbgs() << "%lr is saved register, RegDeficit = " + << RegDeficit << "\n"); } else { AvailableRegs.push_back(ARM::LR); - DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n"); + LLVM_DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n"); } } @@ -1887,11 +1890,11 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, // instructions. This might not reduce RegDeficit all the way to zero, // because we can only guarantee that r4-r6 are available, but r8-r11 may // need saving. - DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n"); + LLVM_DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n"); for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) { unsigned Reg = AvailableRegs.pop_back_val(); - DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) - << " to make up reg deficit\n"); + LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) + << " to make up reg deficit\n"); SavedRegs.set(Reg); NumGPRSpills++; CS1Spilled = true; @@ -1902,7 +1905,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, if (Reg == ARM::LR) LRSpilled = true; } - DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit << "\n"); + LLVM_DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit + << "\n"); } // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. @@ -1923,7 +1927,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, // If stack and double are 8-byte aligned and we are spilling an odd number // of GPRs, spill one extra callee save GPR so we won't have to pad between // the integer and double callee save areas. - DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n"); + LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n"); unsigned TargetAlign = getStackAlignment(); if (TargetAlign >= 8 && (NumGPRSpills & 1)) { if (CS1Spilled && !UnspilledCS1GPRs.empty()) { @@ -1935,8 +1939,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, (STI.isTargetWindows() && Reg == ARM::R11) || isARMLowRegister(Reg) || Reg == ARM::LR) { SavedRegs.set(Reg); - DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) - << " to make up alignment\n"); + LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) + << " to make up alignment\n"); if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) ExtraCSSpill = true; break; @@ -1945,8 +1949,8 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { unsigned Reg = UnspilledCS2GPRs.front(); SavedRegs.set(Reg); - DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) - << " to make up alignment\n"); + LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI) + << " to make up alignment\n"); if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg)) ExtraCSSpill = true; } diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index fe10705d97f..cdd2890c8b7 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6841,10 +6841,9 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, } // Final sanity check before we try to actually produce a shuffle. - DEBUG( - for (auto Src : Sources) - assert(Src.ShuffleVec.getValueType() == ShuffleVT); - ); + LLVM_DEBUG(for (auto Src + : Sources) + assert(Src.ShuffleVec.getValueType() == ShuffleVT);); // The stars all align, our next step is to produce the mask for the shuffle. SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1); @@ -8091,7 +8090,7 @@ static SDValue LowerFPOWI(SDValue Op, const ARMSubtarget &Subtarget, } SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { - DEBUG(dbgs() << "Lowering node: "; Op.dump()); + LLVM_DEBUG(dbgs() << "Lowering node: "; Op.dump()); switch (Op.getOpcode()) { default: llvm_unreachable("Don't know how to custom lower this!"); case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG); @@ -10539,9 +10538,9 @@ static SDValue PerformSHLSimplify(SDNode *N, // Shift left to compensate for the lshr of C1Int. SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); - DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump(); SHL.dump(); - N->dump()); - DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump()); + LLVM_DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump(); + SHL.dump(); N->dump()); + LLVM_DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump()); DAG.ReplaceAllUsesWith(SDValue(N, 0), Res); return SDValue(N, 0); @@ -14816,7 +14815,7 @@ bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters( HABaseType Base = HA_UNKNOWN; uint64_t Members = 0; bool IsHA = isHomogeneousAggregate(Ty, Base, Members); - DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump()); + LLVM_DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump()); bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy(); return IsHA || IsIntArray; diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index 773b0dead18..c37bd87bfe4 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -154,8 +154,8 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, // we hit another of its uses or its defs. // Copies do not have constraints. if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } return true; @@ -399,12 +399,12 @@ bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize, unsigned ExpectedRegBankID) const { if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) { - DEBUG(dbgs() << "Unexpected size for register"); + LLVM_DEBUG(dbgs() << "Unexpected size for register"); return false; } if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { - DEBUG(dbgs() << "Unexpected register bank for register"); + LLVM_DEBUG(dbgs() << "Unexpected register bank for register"); return false; } @@ -496,13 +496,13 @@ bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I, bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const { if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) { - DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n"); + LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n"); return false; } auto GV = MIB->getOperand(1).getGlobal(); if (GV->isThreadLocal()) { - DEBUG(dbgs() << "TLS variables not supported yet\n"); + LLVM_DEBUG(dbgs() << "TLS variables not supported yet\n"); return false; } @@ -607,7 +607,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, else MIB->setDesc(TII.get(ARM::LDRLIT_ga_abs)); } else { - DEBUG(dbgs() << "Object format not supported yet\n"); + LLVM_DEBUG(dbgs() << "Object format not supported yet\n"); return false; } @@ -691,7 +691,7 @@ bool ARMInstructionSelector::select(MachineInstr &I, LLT DstTy = MRI.getType(I.getOperand(0).getReg()); // FIXME: Smaller destination sizes coming soon! if (DstTy.getSizeInBits() != 32) { - DEBUG(dbgs() << "Unsupported destination size for extension"); + LLVM_DEBUG(dbgs() << "Unsupported destination size for extension"); return false; } @@ -733,7 +733,7 @@ bool ARMInstructionSelector::select(MachineInstr &I, break; } default: - DEBUG(dbgs() << "Unsupported source size for extension"); + LLVM_DEBUG(dbgs() << "Unsupported source size for extension"); return false; } break; @@ -774,12 +774,13 @@ bool ARMInstructionSelector::select(MachineInstr &I, } if (SrcRegBank.getID() != DstRegBank.getID()) { - DEBUG(dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n"); + LLVM_DEBUG( + dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n"); return false; } if (SrcRegBank.getID() != ARM::GPRRegBankID) { - DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n"); + LLVM_DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n"); return false; } @@ -789,21 +790,21 @@ bool ARMInstructionSelector::select(MachineInstr &I, case G_CONSTANT: { if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) { // Non-pointer constants should be handled by TableGen. - DEBUG(dbgs() << "Unsupported constant type\n"); + LLVM_DEBUG(dbgs() << "Unsupported constant type\n"); return false; } auto &Val = I.getOperand(1); if (Val.isCImm()) { if (!Val.getCImm()->isZero()) { - DEBUG(dbgs() << "Unsupported pointer constant value\n"); + LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n"); return false; } Val.ChangeToImmediate(0); } else { assert(Val.isImm() && "Unexpected operand for G_CONSTANT"); if (Val.getImm() != 0) { - DEBUG(dbgs() << "Unsupported pointer constant value\n"); + LLVM_DEBUG(dbgs() << "Unsupported pointer constant value\n"); return false; } } @@ -821,13 +822,15 @@ bool ARMInstructionSelector::select(MachineInstr &I, const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); if (SrcRegBank.getID() != DstRegBank.getID()) { - DEBUG(dbgs() - << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n"); + LLVM_DEBUG( + dbgs() + << "G_INTTOPTR/G_PTRTOINT operands on different register banks\n"); return false; } if (SrcRegBank.getID() != ARM::GPRRegBankID) { - DEBUG(dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n"); + LLVM_DEBUG( + dbgs() << "G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n"); return false; } @@ -848,11 +851,11 @@ bool ARMInstructionSelector::select(MachineInstr &I, unsigned Size = MRI.getType(OpReg).getSizeInBits(); if (Size == 64 && STI.isFPOnlySP()) { - DEBUG(dbgs() << "Subtarget only supports single precision"); + LLVM_DEBUG(dbgs() << "Subtarget only supports single precision"); return false; } if (Size != 32 && Size != 64) { - DEBUG(dbgs() << "Unsupported size for G_FCMP operand"); + LLVM_DEBUG(dbgs() << "Unsupported size for G_FCMP operand"); return false; } @@ -883,7 +886,7 @@ bool ARMInstructionSelector::select(MachineInstr &I, case G_LOAD: { const auto &MemOp = **I.memoperands_begin(); if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) { - DEBUG(dbgs() << "Atomic load/store not supported yet\n"); + LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n"); return false; } @@ -920,7 +923,7 @@ bool ARMInstructionSelector::select(MachineInstr &I, } case G_BRCOND: { if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) { - DEBUG(dbgs() << "Unsupported condition register for G_BRCOND"); + LLVM_DEBUG(dbgs() << "Unsupported condition register for G_BRCOND"); return false; } diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 174ed3e5dd2..901138dbdfd 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -2291,7 +2291,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, MIB.addReg(0); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); MIB.setMemRefs(Op0->mergeMemRefsWith(*Op1)); - DEBUG(dbgs() << "Formed " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n"); ++NumLDRDFormed; } else { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) @@ -2305,7 +2305,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, MIB.addReg(0); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); MIB.setMemRefs(Op0->mergeMemRefsWith(*Op1)); - DEBUG(dbgs() << "Formed " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n"); ++NumSTRDFormed; } MBB->erase(Op0); diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 232337412db..c387b75f122 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -583,9 +583,9 @@ void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, SmallVector<BasicBlock*, 4> ExitingBlocks; L->getExitingBlocks(ExitingBlocks); - DEBUG(dbgs() << "Loop has:\n" - << "Blocks: " << L->getNumBlocks() << "\n" - << "Exit blocks: " << ExitingBlocks.size() << "\n"); + LLVM_DEBUG(dbgs() << "Loop has:\n" + << "Blocks: " << L->getNumBlocks() << "\n" + << "Exit blocks: " << ExitingBlocks.size() << "\n"); // Only allow another exit other than the latch. This acts as an early exit // as it mirrors the profitability calculation of the runtime unroller. @@ -616,7 +616,7 @@ void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, } } - DEBUG(dbgs() << "Cost of loop: " << Cost << "\n"); + LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n"); UP.Partial = true; UP.Runtime = true; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ce6ca46437e..f91397aca22 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -10283,10 +10283,11 @@ ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn, Message.Message = "too many operands for instruction"; } else { Message.Message = "invalid operand for instruction"; - DEBUG(dbgs() << "Missing diagnostic string for operand class " << - getMatchClassName((MatchClassKind)I.getOperandClass()) - << I.getOperandClass() << ", error " << I.getOperandError() - << ", opcode " << MII.getName(I.getOpcode()) << "\n"); + LLVM_DEBUG( + dbgs() << "Missing diagnostic string for operand class " + << getMatchClassName((MatchClassKind)I.getOperandClass()) + << I.getOperandClass() << ", error " << I.getOperandError() + << ", opcode " << MII.getName(I.getOpcode()) << "\n"); } NearMissesOut.emplace_back(Message); break; diff --git a/llvm/lib/Target/ARM/MLxExpansionPass.cpp b/llvm/lib/Target/ARM/MLxExpansionPass.cpp index 153e7b1e219..637e4a44c42 100644 --- a/llvm/lib/Target/ARM/MLxExpansionPass.cpp +++ b/llvm/lib/Target/ARM/MLxExpansionPass.cpp @@ -309,17 +309,17 @@ MLxExpansion::ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI, } MIB.addImm(Pred).addReg(PredReg); - DEBUG({ - dbgs() << "Expanding: " << *MI; - dbgs() << " to:\n"; - MachineBasicBlock::iterator MII = MI; - MII = std::prev(MII); - MachineInstr &MI2 = *MII; - MII = std::prev(MII); - MachineInstr &MI1 = *MII; - dbgs() << " " << MI1; - dbgs() << " " << MI2; - }); + LLVM_DEBUG({ + dbgs() << "Expanding: " << *MI; + dbgs() << " to:\n"; + MachineBasicBlock::iterator MII = MI; + MII = std::prev(MII); + MachineInstr &MI2 = *MII; + MII = std::prev(MII); + MachineInstr &MI1 = *MII; + dbgs() << " " << MI1; + dbgs() << " " << MI2; + }); MI->eraseFromParent(); ++NumExpand; diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 115ba65ff86..abf54ba7e87 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -610,7 +610,8 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, // Transfer MI flags. MIB.setMIFlags(MI->getFlags()); - DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); + LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI + << " to 16-bit: " << *MIB); MBB.erase_instr(MI); ++NumLdSts; @@ -657,7 +658,8 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, // Transfer MI flags. MIB.setMIFlags(MI->getFlags()); - DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); + LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI + << " to 16-bit: " << *MIB); MBB.erase_instr(MI); ++NumNarrows; @@ -826,7 +828,8 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, // Transfer MI flags. MIB.setMIFlags(MI->getFlags()); - DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); + LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI + << " to 16-bit: " << *MIB); MBB.erase_instr(MI); ++Num2Addrs; @@ -933,7 +936,8 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, // Transfer MI flags. MIB.setMIFlags(MI->getFlags()); - DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); + LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI + << " to 16-bit: " << *MIB); MBB.erase_instr(MI); ++NumNarrows; diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp index 91d4e9e6598..b0b23effc6c 100644 --- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -521,7 +521,7 @@ bool AVRDAGToDAGISel::selectMultiplication(llvm::SDNode *N) { void AVRDAGToDAGISel::Select(SDNode *N) { // If we have a custom node, we already have selected! if (N->isMachineOpcode()) { - DEBUG(errs() << "== "; N->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; N->dump(CurDAG); errs() << "\n"); N->setNodeId(-1); return; } diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp index b527ad3e0b1..d57cc098497 100644 --- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp +++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp @@ -482,7 +482,7 @@ bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) { } bool AVRAsmParser::parseOperand(OperandVector &Operands) { - DEBUG(dbgs() << "parseOperand\n"); + LLVM_DEBUG(dbgs() << "parseOperand\n"); switch (getLexer().getKind()) { default: @@ -527,7 +527,7 @@ bool AVRAsmParser::parseOperand(OperandVector &Operands) { OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) { - DEBUG(dbgs() << "parseMemriOperand()\n"); + LLVM_DEBUG(dbgs() << "parseMemriOperand()\n"); SMLoc E, S; MCExpr const *Expression; diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index fdf6423514a..8b9bc08e144 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -190,7 +190,7 @@ void BPFDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); return; } @@ -277,7 +277,7 @@ void BPFDAGToDAGISel::PreprocessLoad(SDNode *Node, if (OP1N->getOpcode() <= ISD::BUILTIN_OP_END || OP1N->getNumOperands() == 0) return; - DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n'); const GlobalAddressSDNode *GADN = dyn_cast<GlobalAddressSDNode>(OP1N->getOperand(0).getNode()); @@ -287,7 +287,7 @@ void BPFDAGToDAGISel::PreprocessLoad(SDNode *Node, getConstantFieldValue(GADN, CDN->getZExtValue(), size, new_val.c); } else if (LDAddrNode->getOpcode() > ISD::BUILTIN_OP_END && LDAddrNode->getNumOperands() > 0) { - DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n'); SDValue OP1 = LDAddrNode->getOperand(0); if (const GlobalAddressSDNode *GADN = @@ -310,8 +310,8 @@ void BPFDAGToDAGISel::PreprocessLoad(SDNode *Node, val = new_val.d; } - DEBUG(dbgs() << "Replacing load of size " << size << " with constant " << val - << '\n'); + LLVM_DEBUG(dbgs() << "Replacing load of size " << size << " with constant " + << val << '\n'); SDValue NVal = CurDAG->getConstant(val, DL, MVT::i64); // After replacement, the current node is dead, we need to @@ -427,8 +427,8 @@ bool BPFDAGToDAGISel::fillGenericConstant(const DataLayout &DL, if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { uint64_t val = CI->getZExtValue(); - DEBUG(dbgs() << "Byte array at offset " << Offset << " with value " << val - << '\n'); + LLVM_DEBUG(dbgs() << "Byte array at offset " << Offset << " with value " + << val << '\n'); if (Size > 8 || (Size & (Size - 1))) return false; @@ -517,8 +517,9 @@ void BPFDAGToDAGISel::PreprocessCopyToReg(SDNode *Node) { break; } - DEBUG(dbgs() << "Find Load Value to VReg " - << TargetRegisterInfo::virtReg2Index(RegN->getReg()) << '\n'); + LLVM_DEBUG(dbgs() << "Find Load Value to VReg " + << TargetRegisterInfo::virtReg2Index(RegN->getReg()) + << '\n'); load_to_vreg_[RegN->getReg()] = mem_load_op; } @@ -544,8 +545,8 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, (IntNo == Intrinsic::bpf_load_word && MaskV == 0xFFFFFFFF))) return; - DEBUG(dbgs() << "Remove the redundant AND operation in: "; Node->dump(); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Remove the redundant AND operation in: "; + Node->dump(); dbgs() << '\n'); I--; CurDAG->ReplaceAllUsesWith(SDValue(Node, 0), BaseV); @@ -579,7 +580,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg())) return; unsigned AndOpReg = RegN->getReg(); - DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n'); + LLVM_DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n'); // Examine the PHI insns in the MachineBasicBlock to found out the // definitions of this virtual register. At this stage (DAG2DAG @@ -610,7 +611,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, // Trace each incoming definition, e.g., (%0, %bb.1) and (%1, %bb.3) // The AND operation can be removed if both %0 in %bb.1 and %1 in // %bb.3 are defined with a load matching the MaskN. - DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n'); unsigned PrevReg = -1; for (unsigned i = 0; i < MII->getNumOperands(); ++i) { const MachineOperand &MOP = MII->getOperand(i); @@ -626,8 +627,8 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, } } - DEBUG(dbgs() << "Remove the redundant AND operation in: "; Node->dump(); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Remove the redundant AND operation in: "; Node->dump(); + dbgs() << '\n'); I--; CurDAG->ReplaceAllUsesWith(SDValue(Node, 0), BaseV); diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp index 09cc6b31ad8..9e984d0facf 100644 --- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp @@ -72,15 +72,15 @@ void BPFMIPeephole::initialize(MachineFunction &MFParm) { MF = &MFParm; MRI = &MF->getRegInfo(); TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo(); - DEBUG(dbgs() << "*** BPF MachineSSA peephole pass ***\n\n"); + LLVM_DEBUG(dbgs() << "*** BPF MachineSSA peephole pass ***\n\n"); } bool BPFMIPeephole::isMovFrom32Def(MachineInstr *MovMI) { MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg()); - DEBUG(dbgs() << " Def of Mov Src:"); - DEBUG(DefInsn->dump()); + LLVM_DEBUG(dbgs() << " Def of Mov Src:"); + LLVM_DEBUG(DefInsn->dump()); if (!DefInsn) return false; @@ -111,7 +111,7 @@ bool BPFMIPeephole::isMovFrom32Def(MachineInstr *MovMI) return false; } - DEBUG(dbgs() << " One ZExt elim sequence identified.\n"); + LLVM_DEBUG(dbgs() << " One ZExt elim sequence identified.\n"); return true; } @@ -139,8 +139,8 @@ bool BPFMIPeephole::eliminateZExtSeq(void) { unsigned ShfReg = MI.getOperand(1).getReg(); MachineInstr *SllMI = MRI->getVRegDef(ShfReg); - DEBUG(dbgs() << "Starting SRL found:"); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Starting SRL found:"); + LLVM_DEBUG(MI.dump()); if (!SllMI || SllMI->isPHI() || @@ -148,8 +148,8 @@ bool BPFMIPeephole::eliminateZExtSeq(void) { SllMI->getOperand(2).getImm() != 32) continue; - DEBUG(dbgs() << " SLL found:"); - DEBUG(SllMI->dump()); + LLVM_DEBUG(dbgs() << " SLL found:"); + LLVM_DEBUG(SllMI->dump()); MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg()); if (!MovMI || @@ -157,12 +157,13 @@ bool BPFMIPeephole::eliminateZExtSeq(void) { MovMI->getOpcode() != BPF::MOV_32_64) continue; - DEBUG(dbgs() << " Type cast Mov found:"); - DEBUG(MovMI->dump()); + LLVM_DEBUG(dbgs() << " Type cast Mov found:"); + LLVM_DEBUG(MovMI->dump()); unsigned SubReg = MovMI->getOperand(1).getReg(); if (!isMovFrom32Def(MovMI)) { - DEBUG(dbgs() << " One ZExt elim sequence failed qualifying elim.\n"); + LLVM_DEBUG(dbgs() + << " One ZExt elim sequence failed qualifying elim.\n"); continue; } @@ -228,7 +229,7 @@ public: void BPFMIPreEmitPeephole::initialize(MachineFunction &MFParm) { MF = &MFParm; TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo(); - DEBUG(dbgs() << "*** BPF PreEmit peephole pass ***\n\n"); + LLVM_DEBUG(dbgs() << "*** BPF PreEmit peephole pass ***\n\n"); } bool BPFMIPreEmitPeephole::eliminateRedundantMov(void) { @@ -239,8 +240,8 @@ bool BPFMIPreEmitPeephole::eliminateRedundantMov(void) { for (MachineInstr &MI : MBB) { // If the previous instruction was marked for elimination, remove it now. if (ToErase) { - DEBUG(dbgs() << " Redundant Mov Eliminated:"); - DEBUG(ToErase->dump()); + LLVM_DEBUG(dbgs() << " Redundant Mov Eliminated:"); + LLVM_DEBUG(ToErase->dump()); ToErase->eraseFromParent(); ToErase = nullptr; } diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 1d15a272d7d..577513bd3c9 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -462,9 +462,9 @@ void HexagonOperand::print(raw_ostream &OS) const { } bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { - DEBUG(dbgs() << "Bundle:"); - DEBUG(MCB.dump_pretty(dbgs())); - DEBUG(dbgs() << "--\n"); + LLVM_DEBUG(dbgs() << "Bundle:"); + LLVM_DEBUG(MCB.dump_pretty(dbgs())); + LLVM_DEBUG(dbgs() << "--\n"); MCB.setLoc(IDLoc); // Check the bundle for errors. @@ -557,9 +557,9 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, canonicalizeImmediates(MCI); result = processInstruction(MCI, InstOperands, IDLoc); - DEBUG(dbgs() << "Insn:"); - DEBUG(MCI.dump_pretty(dbgs())); - DEBUG(dbgs() << "\n\n"); + LLVM_DEBUG(dbgs() << "Insn:"); + LLVM_DEBUG(MCI.dump_pretty(dbgs())); + LLVM_DEBUG(dbgs() << "\n\n"); MCI.setLoc(IDLoc); } @@ -1296,9 +1296,9 @@ unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, return Match_Success; } - DEBUG(dbgs() << "Unmatched Operand:"); - DEBUG(Op->dump()); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Unmatched Operand:"); + LLVM_DEBUG(Op->dump()); + LLVM_DEBUG(dbgs() << "\n"); return Match_InvalidOperand; } diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 849bba987c3..4791b067aa8 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -2450,7 +2450,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI, if (Len == RW) return false; - DEBUG({ + LLVM_DEBUG({ dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) << ", MI: " << *MI; dbgs() << "Cell: " << RC << '\n'; @@ -2644,7 +2644,7 @@ bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) { const HexagonEvaluator HE(HRI, MRI, HII, MF); BitTracker BT(HE, MF); - DEBUG(BT.trace(true)); + LLVM_DEBUG(BT.trace(true)); BT.run(); MachineBasicBlock &Entry = MF.front(); @@ -2975,7 +2975,8 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB, } bool HexagonLoopRescheduling::processLoop(LoopCand &C) { - DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n"); + LLVM_DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) + << "\n"); std::vector<PhiInfo> Phis; for (auto &I : *C.LB) { if (!I.isPHI()) @@ -2999,7 +3000,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { Phis.push_back(PhiInfo(I, *C.LB)); } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Phis: {"; for (auto &I : Phis) { dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" @@ -3120,7 +3121,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { Groups.push_back(G); } - DEBUG({ + LLVM_DEBUG({ for (unsigned i = 0, n = Groups.size(); i < n; ++i) { InstrGroup &G = Groups[i]; dbgs() << "Group[" << i << "] inp: " @@ -3188,7 +3189,7 @@ bool HexagonLoopRescheduling::runOnMachineFunction(MachineFunction &MF) { MRI = &MF.getRegInfo(); const HexagonEvaluator HE(*HRI, *MRI, *HII, MF); BitTracker BT(HE, MF); - DEBUG(BT.trace(true)); + LLVM_DEBUG(BT.trace(true)); BT.run(); BTP = &BT; diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp index 2fb30dfbc1c..48a4505458a 100644 --- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -422,10 +422,10 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeLiveMap( InstrIndexMap &IndexMap) { RegToRangeMap LiveMap; - DEBUG(dbgs() << __func__ << ": index map\n" << IndexMap << '\n'); + LLVM_DEBUG(dbgs() << __func__ << ": index map\n" << IndexMap << '\n'); computeInitialLiveRanges(IndexMap, LiveMap); - DEBUG(dbgs() << __func__ << ": live map\n" - << PrintRangeMap(LiveMap, TRI) << '\n'); + LLVM_DEBUG(dbgs() << __func__ << ": live map\n" + << PrintRangeMap(LiveMap, TRI) << '\n'); return LiveMap; } @@ -486,8 +486,8 @@ HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeDeadMap( if (TargetRegisterInfo::isVirtualRegister(P.first.Reg)) addDeadRanges(P.first); - DEBUG(dbgs() << __func__ << ": dead map\n" - << PrintRangeMap(DeadMap, TRI) << '\n'); + LLVM_DEBUG(dbgs() << __func__ << ": dead map\n" + << PrintRangeMap(DeadMap, TRI) << '\n'); return DeadMap; } diff --git a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp index 3e6420c671f..2fa7888dd02 100644 --- a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -90,7 +90,7 @@ FunctionPass *llvm::createHexagonBranchRelaxation() { } bool HexagonBranchRelaxation::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "****** Hexagon Branch Relaxation ******\n"); + LLVM_DEBUG(dbgs() << "****** Hexagon Branch Relaxation ******\n"); auto &HST = MF.getSubtarget<HexagonSubtarget>(); HII = HST.getInstrInfo(); @@ -200,14 +200,14 @@ bool HexagonBranchRelaxation::reGenerateBranch(MachineFunction &MF, for (auto &MI : B) { if (!MI.isBranch() || !isJumpOutOfRange(MI, BlockToInstOffset)) continue; - DEBUG(dbgs() << "Long distance jump. isExtendable(" - << HII->isExtendable(MI) << ") isConstExtended(" - << HII->isConstExtended(MI) << ") " << MI); + LLVM_DEBUG(dbgs() << "Long distance jump. isExtendable(" + << HII->isExtendable(MI) << ") isConstExtended(" + << HII->isConstExtended(MI) << ") " << MI); // Since we have not merged HW loops relaxation into // this code (yet), soften our approach for the moment. if (!HII->isExtendable(MI) && !HII->isExtended(MI)) { - DEBUG(dbgs() << "\tUnderimplemented relax branch instruction.\n"); + LLVM_DEBUG(dbgs() << "\tUnderimplemented relax branch instruction.\n"); } else { // Find which operand is expandable. int ExtOpNum = HII->getCExtOpNum(MI); diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp index 53803b85db8..073f3e56aaf 100644 --- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -342,7 +342,7 @@ bool HexagonCommonGEP::isHandledGepForm(GetElementPtrInst *GepI) { void HexagonCommonGEP::processGepInst(GetElementPtrInst *GepI, ValueToNodeMap &NM) { - DEBUG(dbgs() << "Visiting GEP: " << *GepI << '\n'); + LLVM_DEBUG(dbgs() << "Visiting GEP: " << *GepI << '\n'); GepNode *N = new (*Mem) GepNode; Value *PtrOp = GepI->getPointerOperand(); uint32_t InBounds = GepI->isInBounds() ? GepNode::InBounds : 0; @@ -426,7 +426,7 @@ void HexagonCommonGEP::collect() { } } - DEBUG(dbgs() << "Gep nodes after initial collection:\n" << Nodes); + LLVM_DEBUG(dbgs() << "Gep nodes after initial collection:\n" << Nodes); } static void invert_find_roots(const NodeVect &Nodes, NodeChildrenMap &NCM, @@ -575,7 +575,7 @@ void HexagonCommonGEP::common() { } } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Gep node equality:\n"; for (NodePairSet::iterator I = Eq.begin(), E = Eq.end(); I != E; ++I) dbgs() << "{ " << I->first << ", " << I->second << " }\n"; @@ -642,7 +642,7 @@ void HexagonCommonGEP::common() { N->Parent = Rep; } - DEBUG(dbgs() << "Gep nodes after commoning:\n" << Nodes); + LLVM_DEBUG(dbgs() << "Gep nodes after commoning:\n" << Nodes); // Finally, erase the nodes that are no longer used. NodeSet Erase; @@ -662,35 +662,35 @@ void HexagonCommonGEP::common() { NodeVect::iterator NewE = remove_if(Nodes, in_set(Erase)); Nodes.resize(std::distance(Nodes.begin(), NewE)); - DEBUG(dbgs() << "Gep nodes after post-commoning cleanup:\n" << Nodes); + LLVM_DEBUG(dbgs() << "Gep nodes after post-commoning cleanup:\n" << Nodes); } template <typename T> static BasicBlock *nearest_common_dominator(DominatorTree *DT, T &Blocks) { - DEBUG({ - dbgs() << "NCD of {"; - for (typename T::iterator I = Blocks.begin(), E = Blocks.end(); - I != E; ++I) { - if (!*I) - continue; - BasicBlock *B = cast<BasicBlock>(*I); - dbgs() << ' ' << B->getName(); - } - dbgs() << " }\n"; - }); + LLVM_DEBUG({ + dbgs() << "NCD of {"; + for (typename T::iterator I = Blocks.begin(), E = Blocks.end(); I != E; + ++I) { + if (!*I) + continue; + BasicBlock *B = cast<BasicBlock>(*I); + dbgs() << ' ' << B->getName(); + } + dbgs() << " }\n"; + }); - // Allow null basic blocks in Blocks. In such cases, return nullptr. - typename T::iterator I = Blocks.begin(), E = Blocks.end(); - if (I == E || !*I) + // Allow null basic blocks in Blocks. In such cases, return nullptr. + typename T::iterator I = Blocks.begin(), E = Blocks.end(); + if (I == E || !*I) + return nullptr; + BasicBlock *Dom = cast<BasicBlock>(*I); + while (++I != E) { + BasicBlock *B = cast_or_null<BasicBlock>(*I); + Dom = B ? DT->findNearestCommonDominator(Dom, B) : nullptr; + if (!Dom) return nullptr; - BasicBlock *Dom = cast<BasicBlock>(*I); - while (++I != E) { - BasicBlock *B = cast_or_null<BasicBlock>(*I); - Dom = B ? DT->findNearestCommonDominator(Dom, B) : nullptr; - if (!Dom) - return nullptr; } - DEBUG(dbgs() << "computed:" << Dom->getName() << '\n'); + LLVM_DEBUG(dbgs() << "computed:" << Dom->getName() << '\n'); return Dom; } @@ -753,7 +753,7 @@ static bool is_empty(const BasicBlock *B) { BasicBlock *HexagonCommonGEP::recalculatePlacement(GepNode *Node, NodeChildrenMap &NCM, NodeToValueMap &Loc) { - DEBUG(dbgs() << "Loc for node:" << Node << '\n'); + LLVM_DEBUG(dbgs() << "Loc for node:" << Node << '\n'); // Recalculate the placement for Node, assuming that the locations of // its children in Loc are valid. // Return nullptr if there is no valid placement for Node (for example, it @@ -820,7 +820,7 @@ BasicBlock *HexagonCommonGEP::recalculatePlacement(GepNode *Node, BasicBlock *HexagonCommonGEP::recalculatePlacementRec(GepNode *Node, NodeChildrenMap &NCM, NodeToValueMap &Loc) { - DEBUG(dbgs() << "LocRec begin for node:" << Node << '\n'); + LLVM_DEBUG(dbgs() << "LocRec begin for node:" << Node << '\n'); // Recalculate the placement of Node, after recursively recalculating the // placements of all its children. NodeChildrenMap::iterator CF = NCM.find(Node); @@ -830,7 +830,7 @@ BasicBlock *HexagonCommonGEP::recalculatePlacementRec(GepNode *Node, recalculatePlacementRec(*I, NCM, Loc); } BasicBlock *LB = recalculatePlacement(Node, NCM, Loc); - DEBUG(dbgs() << "LocRec end for node:" << Node << '\n'); + LLVM_DEBUG(dbgs() << "LocRec end for node:" << Node << '\n'); return LB; } @@ -952,8 +952,8 @@ namespace { void HexagonCommonGEP::separateChainForNode(GepNode *Node, Use *U, NodeToValueMap &Loc) { User *R = U->getUser(); - DEBUG(dbgs() << "Separating chain for node (" << Node << ") user: " - << *R << '\n'); + LLVM_DEBUG(dbgs() << "Separating chain for node (" << Node << ") user: " << *R + << '\n'); BasicBlock *PB = cast<Instruction>(R)->getParent(); GepNode *N = Node; @@ -996,7 +996,7 @@ void HexagonCommonGEP::separateChainForNode(GepNode *Node, Use *U, // Should at least have U in NewUs. NewNode->Flags |= GepNode::Used; - DEBUG(dbgs() << "new node: " << NewNode << " " << *NewNode << '\n'); + LLVM_DEBUG(dbgs() << "new node: " << NewNode << " " << *NewNode << '\n'); assert(!NewUs.empty()); Uses[NewNode] = NewUs; } @@ -1007,7 +1007,7 @@ void HexagonCommonGEP::separateConstantChains(GepNode *Node, NodeSet Ns; nodes_for_root(Node, NCM, Ns); - DEBUG(dbgs() << "Separating constant chains for node: " << Node << '\n'); + LLVM_DEBUG(dbgs() << "Separating constant chains for node: " << Node << '\n'); // Collect all used nodes together with the uses from loads and stores, // where the GEP node could be folded into the load/store instruction. NodeToUsesMap FNs; // Foldable nodes. @@ -1044,7 +1044,7 @@ void HexagonCommonGEP::separateConstantChains(GepNode *Node, FNs.insert(std::make_pair(N, LSs)); } - DEBUG(dbgs() << "Nodes with foldable users:\n" << FNs); + LLVM_DEBUG(dbgs() << "Nodes with foldable users:\n" << FNs); for (NodeToUsesMap::iterator I = FNs.begin(), E = FNs.end(); I != E; ++I) { GepNode *N = I->first; @@ -1066,32 +1066,33 @@ void HexagonCommonGEP::computeNodePlacement(NodeToValueMap &Loc) { for (NodeVect::iterator I = Roots.begin(), E = Roots.end(); I != E; ++I) recalculatePlacementRec(*I, NCM, Loc); - DEBUG(dbgs() << "Initial node placement:\n" << LocationAsBlock(Loc)); + LLVM_DEBUG(dbgs() << "Initial node placement:\n" << LocationAsBlock(Loc)); if (OptEnableInv) { for (NodeVect::iterator I = Roots.begin(), E = Roots.end(); I != E; ++I) adjustForInvariance(*I, NCM, Loc); - DEBUG(dbgs() << "Node placement after adjustment for invariance:\n" - << LocationAsBlock(Loc)); + LLVM_DEBUG(dbgs() << "Node placement after adjustment for invariance:\n" + << LocationAsBlock(Loc)); } if (OptEnableConst) { for (NodeVect::iterator I = Roots.begin(), E = Roots.end(); I != E; ++I) separateConstantChains(*I, NCM, Loc); } - DEBUG(dbgs() << "Node use information:\n" << Uses); + LLVM_DEBUG(dbgs() << "Node use information:\n" << Uses); // At the moment, there is no further refinement of the initial placement. // Such a refinement could include splitting the nodes if they are placed // too far from some of its users. - DEBUG(dbgs() << "Final node placement:\n" << LocationAsBlock(Loc)); + LLVM_DEBUG(dbgs() << "Final node placement:\n" << LocationAsBlock(Loc)); } Value *HexagonCommonGEP::fabricateGEP(NodeVect &NA, BasicBlock::iterator At, BasicBlock *LocB) { - DEBUG(dbgs() << "Fabricating GEP in " << LocB->getName() - << " for nodes:\n" << NA); + LLVM_DEBUG(dbgs() << "Fabricating GEP in " << LocB->getName() + << " for nodes:\n" + << NA); unsigned Num = NA.size(); GepNode *RN = NA[0]; assert((RN->Flags & GepNode::Root) && "Creating GEP for non-root"); @@ -1128,7 +1129,7 @@ Value *HexagonCommonGEP::fabricateGEP(NodeVect &NA, BasicBlock::iterator At, Type *ElTy = cast<PointerType>(InpTy->getScalarType())->getElementType(); NewInst = GetElementPtrInst::Create(ElTy, Input, A, "cgep", &*At); NewInst->setIsInBounds(RN->Flags & GepNode::InBounds); - DEBUG(dbgs() << "new GEP: " << *NewInst << '\n'); + LLVM_DEBUG(dbgs() << "new GEP: " << *NewInst << '\n'); Input = NewInst; } while (nax <= Num); @@ -1161,7 +1162,7 @@ void HexagonCommonGEP::getAllUsersForNode(GepNode *Node, ValueVect &Values, } void HexagonCommonGEP::materialize(NodeToValueMap &Loc) { - DEBUG(dbgs() << "Nodes before materialization:\n" << Nodes << '\n'); + LLVM_DEBUG(dbgs() << "Nodes before materialization:\n" << Nodes << '\n'); NodeChildrenMap NCM; NodeVect Roots; // Compute the inversion again, since computing placement could alter diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index a2adc43bc48..8b024fad4f8 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1258,7 +1258,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, if (!ED.IsDef) continue; ExtValue EV(ED); - DEBUG(dbgs() << " =" << I << ". " << EV << " " << ED << '\n'); + LLVM_DEBUG(dbgs() << " =" << I << ". " << EV << " " << ED << '\n'); assert(ED.Rd.Reg != 0); Ranges[I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset); // A2_tfrsi is a special case: it will be replaced with A2_addi, which @@ -1278,7 +1278,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, if (ED.IsDef) continue; ExtValue EV(ED); - DEBUG(dbgs() << " " << I << ". " << EV << " " << ED << '\n'); + LLVM_DEBUG(dbgs() << " " << I << ". " << EV << " " << ED << '\n'); OffsetRange Dev = getOffsetRange(ED); Ranges[I-Begin].intersect(Dev.shift(EV.Offset)); } @@ -1290,7 +1290,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, for (unsigned I = Begin; I != End; ++I) RangeMap[Ranges[I-Begin]].insert(I); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Ranges\n"; for (unsigned I = Begin; I != End; ++I) dbgs() << " " << I << ". " << Ranges[I-Begin] << '\n'; @@ -1384,7 +1384,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, } } - DEBUG(dbgs() << "IMap (before fixup) = " << PrintIMap(IMap, *HRI)); + LLVM_DEBUG(dbgs() << "IMap (before fixup) = " << PrintIMap(IMap, *HRI)); // There is some ambiguity in what initializer should be used, if the // descriptor's subexpression is non-trivial: it can be the entire @@ -1454,7 +1454,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, } } - DEBUG(dbgs() << "IMap (after fixup) = " << PrintIMap(IMap, *HRI)); + LLVM_DEBUG(dbgs() << "IMap (after fixup) = " << PrintIMap(IMap, *HRI)); } void HCE::calculatePlacement(const ExtenderInit &ExtI, const IndexList &Refs, @@ -1557,9 +1557,9 @@ HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) { assert(InitI); (void)InitI; - DEBUG(dbgs() << "Inserted def in bb#" << MBB.getNumber() - << " for initializer: " << PrintInit(ExtI, *HRI) - << "\n " << *InitI); + LLVM_DEBUG(dbgs() << "Inserted def in bb#" << MBB.getNumber() + << " for initializer: " << PrintInit(ExtI, *HRI) << "\n " + << *InitI); return { DefR, 0 }; } @@ -1812,8 +1812,8 @@ bool HCE::replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI) { ExtValue EV(ED); int32_t Diff = EV.Offset - DefV.Offset; const MachineInstr &MI = *ED.UseMI; - DEBUG(dbgs() << __func__ << " Idx:" << Idx << " ExtR:" - << PrintRegister(ExtR, *HRI) << " Diff:" << Diff << '\n'); + LLVM_DEBUG(dbgs() << __func__ << " Idx:" << Idx << " ExtR:" + << PrintRegister(ExtR, *HRI) << " Diff:" << Diff << '\n'); // These two addressing modes must be converted into indexed forms // regardless of what the initializer looks like. @@ -1919,7 +1919,7 @@ const MachineOperand &HCE::getStoredValueOp(const MachineInstr &MI) const { bool HCE::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr)); + LLVM_DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr)); HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); @@ -1934,7 +1934,7 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) { }); bool Changed = false; - DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n"); + LLVM_DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n"); for (unsigned I = 0, E = Extenders.size(); I != E; ) { unsigned B = I; const ExtRoot &T = Extenders[B].getOp(); @@ -1946,7 +1946,7 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) { Changed |= replaceExtenders(IMap); } - DEBUG({ + LLVM_DEBUG({ if (Changed) MF.print(dbgs() << "After " << getPassName() << '\n', nullptr); else diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 730cfafae42..8f22a71dc1f 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -617,7 +617,7 @@ void MachineConstPropagator::CellMap::print(raw_ostream &os, void MachineConstPropagator::visitPHI(const MachineInstr &PN) { const MachineBasicBlock *MB = PN.getParent(); unsigned MBN = MB->getNumber(); - DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN); + LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN); const MachineOperand &MD = PN.getOperand(0); Register DefR(MD); @@ -642,8 +642,8 @@ Bottomize: const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB(); unsigned PBN = PB->getNumber(); if (!EdgeExec.count(CFGEdge(PBN, MBN))) { - DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" - << printMBBReference(*MB) << " not executable\n"); + LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" + << printMBBReference(*MB) << " not executable\n"); continue; } const MachineOperand &SO = PN.getOperand(i); @@ -658,8 +658,9 @@ Bottomize: LatticeCell SrcC; bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); - DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": " - << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n'); + LLVM_DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": " + << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC + << '\n'); Changed |= Eval ? DefC.meet(SrcC) : DefC.setBottom(); Cells.update(DefR.Reg, DefC); @@ -671,11 +672,11 @@ Bottomize: } void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) { - DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent()) - << "): " << MI); + LLVM_DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent()) + << "): " << MI); CellMap Outputs; bool Eval = MCE.evaluate(MI, Cells, Outputs); - DEBUG({ + LLVM_DEBUG({ if (Eval) { dbgs() << " outputs:"; for (auto &I : Outputs) @@ -728,8 +729,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { while (It != End) { const MachineInstr &MI = *It; InstrExec.insert(&MI); - DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(" - << printMBBReference(B) << "): " << MI); + LLVM_DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(" + << printMBBReference(B) << "): " << MI); // Do not evaluate subsequent branches if the evaluation of any of the // previous branches failed. Keep iterating over the branches only // to mark them as executable. @@ -763,23 +764,23 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { // last one set "FallsThru", then add an edge to the layout successor // to the targets. Targets.clear(); - DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG " - "successors\n"); + LLVM_DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG " + "successors\n"); for (const MachineBasicBlock *SB : B.successors()) Targets.insert(SB); } for (const MachineBasicBlock *TB : Targets) { unsigned TBN = TB->getNumber(); - DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " - << printMBBReference(*TB) << "\n"); + LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " + << printMBBReference(*TB) << "\n"); FlowQ.push(CFGEdge(MBN, TBN)); } } void MachineConstPropagator::visitUsesOf(unsigned Reg) { - DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI) - << Cells.get(Reg) << '\n'); + LLVM_DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI) + << Cells.get(Reg) << '\n'); for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { // Do not process non-executable instructions. They can become exceutable // later (via a flow-edge in the work queue). In such case, the instruc- @@ -870,10 +871,10 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { CFGEdge Edge = FlowQ.front(); FlowQ.pop(); - DEBUG(dbgs() << "Picked edge " - << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" - << printMBBReference(*MF.getBlockNumbered(Edge.second)) - << '\n'); + LLVM_DEBUG( + dbgs() << "Picked edge " + << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" + << printMBBReference(*MF.getBlockNumbered(Edge.second)) << '\n'); if (Edge.first != EntryNum) if (EdgeExec.count(Edge)) continue; @@ -927,7 +928,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { } } // while (FlowQ) - DEBUG({ + LLVM_DEBUG({ dbgs() << "Cells after propagation:\n"; Cells.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n"; @@ -1042,7 +1043,7 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) { // This is the constant propagation algorithm as described by Wegman-Zadeck. // Most of the terminology comes from there. bool MachineConstPropagator::run(MachineFunction &MF) { - DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr)); + LLVM_DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr)); MRI = &MF.getRegInfo(); @@ -1054,7 +1055,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) { propagate(MF); bool Changed = rewrite(MF); - DEBUG({ + LLVM_DEBUG({ dbgs() << "End of MachineConstPropagator (Changed=" << Changed << ")\n"; if (Changed) MF.print(dbgs(), nullptr); @@ -2778,7 +2779,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, AllDefs = false; // Some diagnostics. - // DEBUG({...}) gets confused with all this code as an argument. + // LLVM_DEBUG({...}) gets confused with all this code as an argument. #ifndef NDEBUG bool Debugging = DebugFlag && isCurrentDebugType(DEBUG_TYPE); if (Debugging) { @@ -2923,7 +2924,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, ChangedNum++; } - DEBUG({ + LLVM_DEBUG({ if (!NewInstrs.empty()) { MachineFunction &MF = *MI.getParent()->getParent(); dbgs() << "In function: " << MF.getName() << "\n"; @@ -3090,7 +3091,7 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, MO.setIsKill(false); } - DEBUG({ + LLVM_DEBUG({ if (NewMI) { dbgs() << "Rewrite: for " << MI; if (NewMI != &MI) @@ -3130,7 +3131,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI, if (BrI.getOpcode() == Hexagon::J2_jump) return false; - DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI); + LLVM_DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI); bool Rewritten = false; if (NumTargets > 0) { assert(!FallsThru && "This should have been checked before"); diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index f3d24739da4..fccde96d8a3 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -649,7 +649,7 @@ void HexagonCopyToCombine::emitConst64(MachineBasicBlock::iterator &InsertPt, unsigned DoubleDestReg, MachineOperand &HiOperand, MachineOperand &LoOperand) { - DEBUG(dbgs() << "Found a CONST64\n"); + LLVM_DEBUG(dbgs() << "Found a CONST64\n"); DebugLoc DL = InsertPt->getDebugLoc(); MachineBasicBlock *BB = InsertPt->getParent(); diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index bbd06ff747e..557e6384be6 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -238,7 +238,8 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const { bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, MachineLoop *L, FlowPattern &FP) { - DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n"); + LLVM_DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) + << "\n"); // Interested only in conditional branches, no .new, no new-value, etc. // Check the terminators directly, it's easier than handling all responses @@ -325,13 +326,13 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, } // Don't try to predicate loop preheaders. if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) { - DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB) - << " is a loop preheader. Skipping.\n"); + LLVM_DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB) + << " is a loop preheader. Skipping.\n"); return false; } FP = FlowPattern(B, PredR, TB, FB, JB); - DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n"); return true; } @@ -551,8 +552,9 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { }; unsigned Spare = 0; unsigned TotalIn = TotalCount(FP.TrueB, Spare) + TotalCount(FP.FalseB, Spare); - DEBUG(dbgs() << "Total number of instructions to be predicated/speculated: " - << TotalIn << ", spare room: " << Spare << "\n"); + LLVM_DEBUG( + dbgs() << "Total number of instructions to be predicated/speculated: " + << TotalIn << ", spare room: " << Spare << "\n"); if (TotalIn >= SizeLimit+Spare) return false; @@ -579,12 +581,13 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { PredDefs += countPredicateDefs(SB); } } - DEBUG(dbgs() << "Total number of extra muxes from converted phis: " - << TotalPh << "\n"); + LLVM_DEBUG(dbgs() << "Total number of extra muxes from converted phis: " + << TotalPh << "\n"); if (TotalIn+TotalPh >= SizeLimit+Spare) return false; - DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs << "\n"); + LLVM_DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs + << "\n"); if (PredDefs > 4) return false; @@ -625,11 +628,11 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B, return Changed; if (!isValid(FP)) { - DEBUG(dbgs() << "Conversion is not valid\n"); + LLVM_DEBUG(dbgs() << "Conversion is not valid\n"); return Changed; } if (!isProfitable(FP)) { - DEBUG(dbgs() << "Conversion is not profitable\n"); + LLVM_DEBUG(dbgs() << "Conversion is not profitable\n"); return Changed; } @@ -640,8 +643,9 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B, bool HexagonEarlyIfConversion::visitLoop(MachineLoop *L) { MachineBasicBlock *HB = L ? L->getHeader() : nullptr; - DEBUG((L ? dbgs() << "Visiting loop H:" << PrintMB(HB) - : dbgs() << "Visiting function") << "\n"); + LLVM_DEBUG((L ? dbgs() << "Visiting loop H:" << PrintMB(HB) + : dbgs() << "Visiting function") + << "\n"); bool Changed = false; if (L) { for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) @@ -758,7 +762,7 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB, void HexagonEarlyIfConversion::predicateBlockNB(MachineBasicBlock *ToB, MachineBasicBlock::iterator At, MachineBasicBlock *FromB, unsigned PredR, bool IfTrue) { - DEBUG(dbgs() << "Predicating block " << PrintMB(FromB) << "\n"); + LLVM_DEBUG(dbgs() << "Predicating block " << PrintMB(FromB) << "\n"); MachineBasicBlock::iterator End = FromB->getFirstTerminator(); MachineBasicBlock::iterator I, NextI; @@ -950,7 +954,7 @@ void HexagonEarlyIfConversion::convert(const FlowPattern &FP) { } void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) { - DEBUG(dbgs() << "Removing block " << PrintMB(B) << "\n"); + LLVM_DEBUG(dbgs() << "Removing block " << PrintMB(B) << "\n"); // Transfer the immediate dominator information from B to its descendants. MachineDomTreeNode *N = MDT->getNode(B); @@ -980,7 +984,7 @@ void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) { } void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) { - DEBUG(dbgs() << "Removing phi nodes from block " << PrintMB(B) << "\n"); + LLVM_DEBUG(dbgs() << "Removing phi nodes from block " << PrintMB(B) << "\n"); MachineBasicBlock::iterator I, NextI, NonPHI = B->getFirstNonPHI(); for (I = B->begin(); I != NonPHI; I = NextI) { NextI = std::next(I); @@ -1007,8 +1011,8 @@ void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) { void HexagonEarlyIfConversion::mergeBlocks(MachineBasicBlock *PredB, MachineBasicBlock *SuccB) { - DEBUG(dbgs() << "Merging blocks " << PrintMB(PredB) << " and " - << PrintMB(SuccB) << "\n"); + LLVM_DEBUG(dbgs() << "Merging blocks " << PrintMB(PredB) << " and " + << PrintMB(SuccB) << "\n"); bool TermOk = hasUncondBranch(SuccB); eliminatePhis(SuccB); HII->removeBranch(*PredB); diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 06caa2feffa..d3222a63ead 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -650,7 +650,7 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, .add(SrcOp); } - DEBUG(dbgs() << "created an initial copy: " << *MIB); + LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB); return &*MIB; } @@ -663,8 +663,8 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, return false; TfrCounter++; } - DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": " - << MI); + LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) + << ": " << MI); MachineOperand &MD = MI.getOperand(0); // Definition MachineOperand &MP = MI.getOperand(1); // Predicate register assert(MD.isDef()); @@ -941,8 +941,8 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, unsigned Opc = TfrI.getOpcode(); (void)Opc; assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf); - DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") - << ": " << TfrI); + LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") + << ": " << TfrI); MachineOperand &MD = TfrI.getOperand(0); MachineOperand &MP = TfrI.getOperand(1); @@ -963,7 +963,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, if (!DefI || !isPredicable(DefI)) return false; - DEBUG(dbgs() << "Source def: " << *DefI); + LLVM_DEBUG(dbgs() << "Source def: " << *DefI); // Collect the information about registers defined and used between the // DefI and the TfrI. @@ -1048,8 +1048,8 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, if (!canMoveMemTo(*DefI, TfrI, true)) CanDown = false; - DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") - << ", can move down: " << (CanDown ? "yes\n" : "no\n")); + LLVM_DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") + << ", can move down: " << (CanDown ? "yes\n" : "no\n")); MachineBasicBlock::iterator PastDefIt = std::next(DefIt); if (CanUp) predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs); @@ -1144,10 +1144,10 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { return false; bool Overlap = L1.overlaps(L2); - DEBUG(dbgs() << "compatible registers: (" - << (Overlap ? "overlap" : "disjoint") << ")\n " - << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " - << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); + LLVM_DEBUG(dbgs() << "compatible registers: (" + << (Overlap ? "overlap" : "disjoint") << ")\n " + << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " + << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); if (R1.Sub || R2.Sub) return false; if (Overlap) @@ -1180,7 +1180,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { LIS->removeInterval(R2.Reg); updateKillFlags(R1.Reg); - DEBUG(dbgs() << "coalesced: " << L1 << "\n"); + LLVM_DEBUG(dbgs() << "coalesced: " << L1 << "\n"); L1.verify(); return true; @@ -1261,8 +1261,8 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { LIS = &getAnalysis<LiveIntervals>(); MRI = &MF.getRegInfo(); - DEBUG(LIS->print(dbgs() << "Before expand-condsets\n", - MF.getFunction().getParent())); + LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n", + MF.getFunction().getParent())); bool Changed = false; std::set<unsigned> CoalUpd, PredUpd; @@ -1289,8 +1289,8 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { if (!CoalUpd.count(Op.getReg())) KillUpd.insert(Op.getReg()); updateLiveness(KillUpd, false, true, false); - DEBUG(LIS->print(dbgs() << "After coalescing\n", - MF.getFunction().getParent())); + LLVM_DEBUG( + LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent())); // First, simply split all muxes into a pair of conditional transfers // and update the live intervals to reflect the new arrangement. The @@ -1306,8 +1306,8 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { // predication, and after splitting they are difficult to recalculate // (because of predicated defs), so make sure they are left untouched. // Predication does not use live intervals. - DEBUG(LIS->print(dbgs() << "After splitting\n", - MF.getFunction().getParent())); + LLVM_DEBUG( + LIS->print(dbgs() << "After splitting\n", MF.getFunction().getParent())); // Traverse all blocks and collapse predicable instructions feeding // conditional transfers into predicated instructions. @@ -1315,13 +1315,13 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { // cases that were not created in the previous step. for (auto &B : MF) Changed |= predicateInBlock(B, PredUpd); - DEBUG(LIS->print(dbgs() << "After predicating\n", - MF.getFunction().getParent())); + LLVM_DEBUG(LIS->print(dbgs() << "After predicating\n", + MF.getFunction().getParent())); PredUpd.insert(CoalUpd.begin(), CoalUpd.end()); updateLiveness(PredUpd, true, true, true); - DEBUG({ + LLVM_DEBUG({ if (Changed) LIS->print(dbgs() << "After expand-condsets\n", MF.getFunction().getParent()); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 4b3e11ed3fd..97b02e2b34c 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -442,7 +442,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, if (needsStackFrame(I, CSR, HRI)) SFBlocks.push_back(&I); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Blocks needing SF: {"; for (auto &B : SFBlocks) dbgs() << " " << printMBBReference(*B); @@ -465,7 +465,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, if (!PDomB) break; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Computed dom block: "; if (DomB) dbgs() << printMBBReference(*DomB); @@ -483,11 +483,11 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, // Make sure that DomB dominates PDomB and PDomB post-dominates DomB. if (!MDT.dominates(DomB, PDomB)) { - DEBUG(dbgs() << "Dom block does not dominate pdom block\n"); + LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n"); return; } if (!MPT.dominates(PDomB, DomB)) { - DEBUG(dbgs() << "PDom block does not post-dominate dom block\n"); + LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n"); return; } @@ -1396,7 +1396,7 @@ static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const { - DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n'); MachineFrameInfo &MFI = MF.getFrameInfo(); BitVector SRegs(Hexagon::NUM_TARGET_REGS); @@ -1406,15 +1406,16 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // (1) For each callee-saved register, add that register and all of its // sub-registers to SRegs. - DEBUG(dbgs() << "Initial CS registers: {"); + LLVM_DEBUG(dbgs() << "Initial CS registers: {"); for (unsigned i = 0, n = CSI.size(); i < n; ++i) { unsigned R = CSI[i].getReg(); - DEBUG(dbgs() << ' ' << printReg(R, TRI)); + LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI)); for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = true; } - DEBUG(dbgs() << " }\n"); - DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << " }\n"); + LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // (2) For each reserved register, remove that register and all of its // sub- and super-registers from SRegs. @@ -1424,8 +1425,10 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = false; } - DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); dbgs() << "\n"); - DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); + dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // (3) Collect all registers that have at least one sub-register in SRegs, // and also have no sub-registers that are reserved. These will be the can- @@ -1446,11 +1449,13 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, break; } } - DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); + dbgs() << "\n"); // (4) Include all super-registers found in (3) into SRegs. SRegs |= TmpSup; - DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // (5) For each register R in SRegs, if any super-register of R is in SRegs, // remove R from SRegs. @@ -1463,7 +1468,8 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, break; } } - DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // Now, for each register that has a fixed stack slot, create the stack // object for it. @@ -1501,7 +1507,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, SRegs[R] = false; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "CS information: {"; for (unsigned i = 0, n = CSI.size(); i < n; ++i) { int FI = CSI[i].getFrameIdx(); @@ -2021,8 +2027,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto P = BlockIndexes.insert( std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B))); auto &IndexMap = P.first->second; - DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n" - << IndexMap << '\n'); + LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n" + << IndexMap << '\n'); for (auto &In : B) { int LFI, SFI; @@ -2129,7 +2135,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, } } - DEBUG({ + LLVM_DEBUG({ for (auto &P : FIRangeMap) { dbgs() << "fi#" << P.first; if (BadFIs.count(P.first)) @@ -2168,7 +2174,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, } } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Block-to-FI map (* -- live-on-exit):\n"; for (auto &P : BlockFIMap) { auto &FIs = P.second; @@ -2195,16 +2201,16 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, HexagonBlockRanges::InstrIndexMap &IM = F->second; HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM); HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM); - DEBUG(dbgs() << printMBBReference(B) << " dead map\n" - << HexagonBlockRanges::PrintRangeMap(DM, HRI)); + LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n" + << HexagonBlockRanges::PrintRangeMap(DM, HRI)); for (auto FI : BlockFIMap[&B]) { if (BadFIs.count(FI)) continue; - DEBUG(dbgs() << "Working on fi#" << FI << '\n'); + LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n'); HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; for (auto &Range : RL) { - DEBUG(dbgs() << "--Examining range:" << RL << '\n'); + LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n'); if (!IndexType::isInstr(Range.start()) || !IndexType::isInstr(Range.end())) continue; @@ -2219,7 +2225,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); // The this-> is needed to unconfuse MSVC. unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC); - DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n'); + LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) + << '\n'); if (FoundR == 0) continue; #ifndef NDEBUG diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index 9288ed03d4d..c0d2de90467 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -222,13 +222,12 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { } void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { - DEBUG(dbgs() << __func__ << ": " - << printReg(Reg.R, TRI, Reg.S) << "\n"); + LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); using use_iterator = MachineRegisterInfo::use_iterator; use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); if (I == E) { - DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); + LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); MachineInstr *DefI = MRI->getVRegDef(Reg.R); DefI->eraseFromParent(); return; @@ -250,7 +249,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { if (F != G2P.end()) return F->second; - DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI)); + LLVM_DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI)); MachineInstr *DefI = MRI->getVRegDef(Reg.R); assert(DefI); unsigned Opc = DefI->getOpcode(); @@ -258,7 +257,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); Register PR = DefI->getOperand(1); G2P.insert(std::make_pair(Reg, PR)); - DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); + LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); return PR; } @@ -274,7 +273,8 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR) .addReg(Reg.R, 0, Reg.S); G2P.insert(std::make_pair(Reg, Register(NewPR))); - DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) << '\n'); + LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) + << '\n'); return Register(NewPR); } @@ -364,7 +364,7 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) { } bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { - DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI); + LLVM_DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI); unsigned Opc = MI->getOpcode(); assert(isConvertibleToPredForm(MI)); @@ -426,7 +426,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { Register Pred = getPredRegFor(GPR); MIB.addReg(Pred.R, 0, Pred.S); } - DEBUG(dbgs() << "generated: " << *MIB); + LLVM_DEBUG(dbgs() << "generated: " << *MIB); // Generate a copy-out: NewGPR = NewPR, and replace all uses of OutR // with NewGPR. @@ -449,7 +449,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { } bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { - DEBUG(dbgs() << __func__ << "\n"); + LLVM_DEBUG(dbgs() << __func__ << "\n"); const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; bool Changed = false; VectOfInst Erase; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index e3d5825b269..0e33976a58a 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -376,7 +376,7 @@ FunctionPass *llvm::createHexagonHardwareLoops() { } bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n"); + LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n"); if (skipFunction(MF.getFunction())) return false; @@ -1012,14 +1012,15 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI, bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const { const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks(); - DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); + LLVM_DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { MachineBasicBlock *MBB = Blocks[i]; for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) { const MachineInstr *MI = &*MII; if (isInvalidLoopOperation(MI, IsInnerHWLoop)) { - DEBUG(dbgs()<< "\nCannot convert to hw_loop due to:"; MI->dump();); + LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:"; + MI->dump();); return true; } } @@ -1084,7 +1085,7 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) { SmallVector<MachineInstr*, 1> DeadPhis; if (isDead(MI, DeadPhis)) { - DEBUG(dbgs() << "HW looping will remove: " << *MI); + LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI); // It is possible that some DBG_VALUE instructions refer to this // instruction. Examine each def operand for such references; @@ -1238,7 +1239,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L, LoopStart = TopBlock; // Convert the loop to a hardware loop. - DEBUG(dbgs() << "Change to hardware loop at "; L->dump()); + LLVM_DEBUG(dbgs() << "Change to hardware loop at "; L->dump()); DebugLoc DL; if (InsertPos != Preheader->end()) DL = InsertPos->getDebugLoc(); @@ -1368,7 +1369,7 @@ bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, LoopFeederMap &LoopFeederPhi) const { if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) { const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks(); - DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); + LLVM_DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); // Ignore all BBs that form Loop. for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { MachineBasicBlock *MBB = Blocks[i]; @@ -1769,16 +1770,16 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { for (unsigned i = 1, n = PredDef->getNumOperands(); i < n; ++i) { MachineOperand &MO = PredDef->getOperand(i); if (MO.isReg() && MO.getReg() == RB.first) { - DEBUG(dbgs() << "\n DefMI(" << i << ") = " - << *(MRI->getVRegDef(I->first))); + LLVM_DEBUG(dbgs() << "\n DefMI(" << i + << ") = " << *(MRI->getVRegDef(I->first))); if (IndI) return false; IndI = MRI->getVRegDef(I->first); IndMO = &MO; } else if (MO.isReg()) { - DEBUG(dbgs() << "\n DefMI(" << i << ") = " - << *(MRI->getVRegDef(MO.getReg()))); + LLVM_DEBUG(dbgs() << "\n DefMI(" << i + << ") = " << *(MRI->getVRegDef(MO.getReg()))); if (nonIndI) return false; diff --git a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp index 8ac333f4f01..44f1f554c66 100644 --- a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define DEBUG_TYPE "post-RA-sched" void HexagonHazardRecognizer::Reset() { - DEBUG(dbgs() << "Reset hazard recognizer\n"); + LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n"); Resources->clearResources(); PacketNum = 0; UsesDotCur = nullptr; @@ -43,7 +43,7 @@ HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { return NoHazard; if (!Resources->canReserveResources(*MI)) { - DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI); + LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI); HazardType RetVal = Hazard; if (TII->mayBeNewStore(*MI)) { // Make sure the register to be stored is defined by an instruction in the @@ -59,14 +59,16 @@ HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { MI->getDebugLoc()); if (Resources->canReserveResources(*NewMI)) RetVal = NoHazard; - DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) << "\n"); + LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) + << "\n"); MF->DeleteMachineInstr(NewMI); } return RetVal; } if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) { - DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " << *MI); + LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " + << *MI); return Hazard; } @@ -74,7 +76,7 @@ HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { } void HexagonHazardRecognizer::AdvanceCycle() { - DEBUG(dbgs() << "Advance cycle, clear state\n"); + LLVM_DEBUG(dbgs() << "Advance cycle, clear state\n"); Resources->clearResources(); if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) { UsesDotCur = nullptr; @@ -132,7 +134,7 @@ void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { } else Resources->reserveResources(*MI); - DEBUG(dbgs() << " Add instruction " << *MI); + LLVM_DEBUG(dbgs() << " Add instruction " << *MI); // When scheduling a dot cur instruction, check if there is an instruction // that can use the dot cur in the same packet. If so, we'll attempt to diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index e639d13bd2b..20e8dcdb06f 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1892,15 +1892,15 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { RootHeights[N] = std::max(getHeight(N->getOperand(0).getNode()), getHeight(N->getOperand(1).getNode())) + 1; - DEBUG(dbgs() << "--> No need to balance root (Weight=" << Weight - << " Height=" << RootHeights[N] << "): "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "--> No need to balance root (Weight=" << Weight + << " Height=" << RootHeights[N] << "): "); + LLVM_DEBUG(N->dump(CurDAG)); return SDValue(N, 0); } - DEBUG(dbgs() << "** Balancing root node: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "** Balancing root node: "); + LLVM_DEBUG(N->dump(CurDAG)); unsigned NOpcode = N->getOpcode(); @@ -1948,7 +1948,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // Whoops, this node was RAUWd by one of the balanceSubTree calls we // made. Our worklist isn't up to date anymore. // Restart the whole process. - DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); + LLVM_DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); return balanceSubTree(N, TopLevel); } @@ -2019,15 +2019,15 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { } } - DEBUG(dbgs() << "--> Current height=" << NodeHeights[SDValue(N, 0)] - << " weight=" << CurrentWeight << " imbalanced=" - << Imbalanced << "\n"); + LLVM_DEBUG(dbgs() << "--> Current height=" << NodeHeights[SDValue(N, 0)] + << " weight=" << CurrentWeight + << " imbalanced=" << Imbalanced << "\n"); // Transform MUL(x, C * 2^Y) + SHL(z, Y) -> SHL(ADD(MUL(x, C), z), Y) // This factors out a shift in order to match memw(a<<Y+b). if (CanFactorize && (willShiftRightEliminate(Mul1.Value, MaxPowerOf2) || willShiftRightEliminate(Mul2.Value, MaxPowerOf2))) { - DEBUG(dbgs() << "--> Found common factor for two MUL children!\n"); + LLVM_DEBUG(dbgs() << "--> Found common factor for two MUL children!\n"); int Weight = Mul1.Weight + Mul2.Weight; int Height = std::max(NodeHeights[Mul1.Value], NodeHeights[Mul2.Value]) + 1; SDValue Mul1Factored = factorOutPowerOf2(Mul1.Value, MaxPowerOf2); @@ -2061,9 +2061,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { if (getUsesInFunction(GANode->getGlobal()) == 1 && Offset->hasOneUse() && getTargetLowering()->isOffsetFoldingLegal(GANode)) { - DEBUG(dbgs() << "--> Combining GA and offset (" << Offset->getSExtValue() - << "): "); - DEBUG(GANode->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "--> Combining GA and offset (" + << Offset->getSExtValue() << "): "); + LLVM_DEBUG(GANode->dump(CurDAG)); SDValue NewTGA = CurDAG->getTargetGlobalAddress(GANode->getGlobal(), SDLoc(GA.Value), @@ -2107,7 +2107,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // If this is the top level and we haven't factored out a shift, we should try // to move a constant to the bottom to match addressing modes like memw(rX+C) if (TopLevel && !CanFactorize && Leaves.hasConst()) { - DEBUG(dbgs() << "--> Pushing constant to tip of tree."); + LLVM_DEBUG(dbgs() << "--> Pushing constant to tip of tree."); Leaves.pushToBottom(Leaves.pop()); } @@ -2134,7 +2134,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // Make sure that none of these nodes have been RAUW'd if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || (RootWeights.count(V1.getNode()) && RootWeights[V1.getNode()] == -2)) { - DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); + LLVM_DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); return balanceSubTree(N, TopLevel); } @@ -2168,9 +2168,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { int Weight = V0Weight + V1Weight; Leaves.push(WeightedLeaf(NewNode, Weight, L0.InsertionOrder)); - DEBUG(dbgs() << "--> Built new node (Weight=" << Weight << ",Height=" - << Height << "):\n"); - DEBUG(NewNode.dump()); + LLVM_DEBUG(dbgs() << "--> Built new node (Weight=" << Weight + << ",Height=" << Height << "):\n"); + LLVM_DEBUG(NewNode.dump()); } assert(Leaves.size() == 1); @@ -2194,15 +2194,15 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { } if (N != NewRoot.getNode()) { - DEBUG(dbgs() << "--> Root is now: "); - DEBUG(NewRoot.dump()); + LLVM_DEBUG(dbgs() << "--> Root is now: "); + LLVM_DEBUG(NewRoot.dump()); // Replace all uses of old root by new root CurDAG->ReplaceAllUsesWith(N, NewRoot.getNode()); // Mark that we have RAUW'd N RootWeights[N] = -2; } else { - DEBUG(dbgs() << "--> Root unchanged.\n"); + LLVM_DEBUG(dbgs() << "--> Root unchanged.\n"); } RootWeights[NewRoot.getNode()] = Leaves.top().Weight; @@ -2225,8 +2225,8 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { if (RootWeights.count(BasePtr.getNode())) continue; - DEBUG(dbgs() << "** Rebalancing address calculation in node: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "** Rebalancing address calculation in node: "); + LLVM_DEBUG(N->dump(CurDAG)); // FindRoots SmallVector<SDNode *, 4> Worklist; @@ -2266,8 +2266,8 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), NewBasePtr, N->getOperand(3)); - DEBUG(dbgs() << "--> Final node: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "--> Final node: "); + LLVM_DEBUG(N->dump(CurDAG)); } CurDAG->RemoveDeadNodes(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index be036b3ddb3..fbe8f16bd98 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -359,9 +359,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, break; } } - DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n" - : "Argument must be passed on stack. " - "Not eligible for Tail Call\n")); + LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n" + : "Argument must be passed on stack. " + "Not eligible for Tail Call\n")); } // Get a count of how many bytes are to be pushed on the stack. unsigned NumBytes = CCInfo.getNextStackOffset(); @@ -433,7 +433,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } if (NeedsArgAlign && Subtarget.hasV60TOps()) { - DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); + LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); LargestAlignSeen = std::max(LargestAlignSeen, VecAlign); MFI.ensureMaxAlignment(LargestAlignSeen); @@ -670,7 +670,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, if (A == 0) A = HFI.getStackAlignment(); - DEBUG({ + LLVM_DEBUG({ dbgs () << __func__ << " Align: " << A << " Size: "; Size.getNode()->dump(&DAG); dbgs() << "\n"; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1ec1ce01336..4086c6cfb81 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -430,7 +430,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, // Delete the J2_jump if it's equivalent to a fall-through. if (AllowModify && JumpToBlock && MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { - DEBUG(dbgs() << "\nErasing the jump to successor block\n";); + LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";); I->eraseFromParent(); I = MBB.instr_end(); if (I == MBB.instr_begin()) @@ -499,8 +499,8 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, Cond.push_back(LastInst->getOperand(1)); return false; } - DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) - << " with one jump\n";); + LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) + << " with one jump\n";); // Otherwise, don't know what this is. return true; } @@ -547,8 +547,8 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, FBB = LastInst->getOperand(0).getMBB(); return false; } - DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) - << " with two jumps";); + LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) + << " with two jumps";); // Otherwise, can't handle this. return true; } @@ -557,7 +557,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); - DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB)); + LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB)); MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { @@ -629,7 +629,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset) // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset) unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); - DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB);); + LLVM_DEBUG(dbgs() << "\nInserting NVJump for " + << printMBBReference(MBB);); if (Cond[2].isReg()) { unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). @@ -1501,7 +1502,7 @@ bool HexagonInstrInfo::PredicateInstruction( MachineInstr &MI, ArrayRef<MachineOperand> Cond) const { if (Cond.empty() || isNewValueJump(Cond[0].getImm()) || isEndLoopN(Cond[0].getImm())) { - DEBUG(dbgs() << "\nCannot predicate:"; MI.dump();); + LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump();); return false; } int Opc = MI.getOpcode(); @@ -2251,13 +2252,13 @@ bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, bool isLate = isLateResultInstr(LRMI); bool isEarly = isEarlySourceInstr(ESMI); - DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- ")); - DEBUG(LRMI.dump()); - DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- ")); - DEBUG(ESMI.dump()); + LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- ")); + LLVM_DEBUG(LRMI.dump()); + LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- ")); + LLVM_DEBUG(ESMI.dump()); if (isLate && isEarly) { - DEBUG(dbgs() << "++Is Late Result feeding Early Source\n"); + LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n"); return true; } @@ -4174,7 +4175,7 @@ bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond, return false; assert(Cond.size() == 2); if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) { - DEBUG(dbgs() << "No predregs for new-value jumps/endloop"); + LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop"); return false; } PredReg = Cond[1].getReg(); @@ -4276,9 +4277,9 @@ void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const { bool HexagonInstrInfo::invertAndChangeJumpTarget( MachineInstr &MI, MachineBasicBlock *NewTarget) const { - DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to " - << printMBBReference(*NewTarget); - MI.dump();); + LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to " + << printMBBReference(*NewTarget); + MI.dump();); assert(MI.isBranch()); unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); int TargetPos = MI.getNumOperands() - 1; @@ -4306,8 +4307,9 @@ void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const { for (unsigned insn = TargetOpcode::GENERIC_OP_END+1; insn < Hexagon::INSTRUCTION_LIST_END; ++insn) { NewMI = BuildMI(B, I, DL, get(insn)); - DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) << - " Class: " << NewMI->getDesc().getSchedClass()); + LLVM_DEBUG(dbgs() << "\n" + << getName(NewMI->getOpcode()) + << " Class: " << NewMI->getDesc().getSchedClass()); NewMI->eraseFromParent(); } /* --- The code above is used to generate complete set of Hexagon Insn --- */ @@ -4317,7 +4319,7 @@ void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const { // p -> NotP // NotP -> P bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const { - DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump()); + LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump()); MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode()))); return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index d0bc2ed83a7..8b22d35cf9c 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -1758,15 +1758,15 @@ void PolynomialMultiplyRecognize::setupPostSimplifier(Simplifier &S) { } bool PolynomialMultiplyRecognize::recognize() { - DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n" - << *CurLoop << '\n'); + LLVM_DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n" + << *CurLoop << '\n'); // Restrictions: // - The loop must consist of a single block. // - The iteration count must be known at compile-time. // - The loop must have an induction variable starting from 0, and // incremented in each iteration of the loop. BasicBlock *LoopB = CurLoop->getHeader(); - DEBUG(dbgs() << "Loop header:\n" << *LoopB); + LLVM_DEBUG(dbgs() << "Loop header:\n" << *LoopB); if (LoopB != CurLoop->getLoopLatch()) return false; @@ -1788,7 +1788,8 @@ bool PolynomialMultiplyRecognize::recognize() { ParsedValues PV; Simplifier PreSimp; PV.IterCount = IterCount; - DEBUG(dbgs() << "Loop IV: " << *CIV << "\nIterCount: " << IterCount << '\n'); + LLVM_DEBUG(dbgs() << "Loop IV: " << *CIV << "\nIterCount: " << IterCount + << '\n'); setupPreSimplifier(PreSimp); @@ -1815,7 +1816,7 @@ bool PolynomialMultiplyRecognize::recognize() { Simplifier::Context C(SI); Value *T = PreSimp.simplify(C); SelectInst *SelI = (T && isa<SelectInst>(T)) ? cast<SelectInst>(T) : SI; - DEBUG(dbgs() << "scanSelect(pre-scan): " << PE(C, SelI) << '\n'); + LLVM_DEBUG(dbgs() << "scanSelect(pre-scan): " << PE(C, SelI) << '\n'); if (scanSelect(SelI, LoopB, EntryB, CIV, PV, true)) { FoundPreScan = true; if (SelI != SI) { @@ -1828,7 +1829,7 @@ bool PolynomialMultiplyRecognize::recognize() { } if (!FoundPreScan) { - DEBUG(dbgs() << "Have not found candidates for pmpy\n"); + LLVM_DEBUG(dbgs() << "Have not found candidates for pmpy\n"); return false; } @@ -1868,14 +1869,14 @@ bool PolynomialMultiplyRecognize::recognize() { SelectInst *SelI = dyn_cast<SelectInst>(&In); if (!SelI) continue; - DEBUG(dbgs() << "scanSelect: " << *SelI << '\n'); + LLVM_DEBUG(dbgs() << "scanSelect: " << *SelI << '\n'); FoundScan = scanSelect(SelI, LoopB, EntryB, CIV, PV, false); if (FoundScan) break; } assert(FoundScan); - DEBUG({ + LLVM_DEBUG({ StringRef PP = (PV.M ? "(P+M)" : "P"); if (!PV.Inv) dbgs() << "Found pmpy idiom: R = " << PP << ".Q\n"; @@ -2287,10 +2288,11 @@ CleanupAndExit: NewCall->setDebugLoc(DLoc); - DEBUG(dbgs() << " Formed " << (Overlap ? "memmove: " : "memcpy: ") - << *NewCall << "\n" - << " from load ptr=" << *LoadEv << " at: " << *LI << "\n" - << " from store ptr=" << *StoreEv << " at: " << *SI << "\n"); + LLVM_DEBUG(dbgs() << " Formed " << (Overlap ? "memmove: " : "memcpy: ") + << *NewCall << "\n" + << " from load ptr=" << *LoadEv << " at: " << *LI << "\n" + << " from store ptr=" << *StoreEv << " at: " << *SI + << "\n"); return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 4376a30fdd9..74c550ce822 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -172,11 +172,11 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { Packet.push_back(SU); #ifndef NDEBUG - DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n"); + LLVM_DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n"); for (unsigned i = 0, e = Packet.size(); i != e; ++i) { - DEBUG(dbgs() << "\t[" << i << "] SU("); - DEBUG(dbgs() << Packet[i]->NodeNum << ")\t"); - DEBUG(Packet[i]->getInstr()->dump()); + LLVM_DEBUG(dbgs() << "\t[" << i << "] SU("); + LLVM_DEBUG(dbgs() << Packet[i]->NodeNum << ")\t"); + LLVM_DEBUG(Packet[i]->getInstr()->dump()); } #endif @@ -187,10 +187,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { /// after setting up the current scheduling region. [RegionBegin, RegionEnd) /// only includes instructions that have DAG nodes, not scheduling boundaries. void VLIWMachineScheduler::schedule() { - DEBUG(dbgs() << "********** MI Converging Scheduling VLIW " - << printMBBReference(*BB) << " " << BB->getName() << " in_func " - << BB->getParent()->getName() << " at loop depth " - << MLI->getLoopDepth(BB) << " \n"); + LLVM_DEBUG(dbgs() << "********** MI Converging Scheduling VLIW " + << printMBBReference(*BB) << " " << BB->getName() + << " in_func " << BB->getParent()->getName() + << " at loop depth " << MLI->getLoopDepth(BB) << " \n"); buildDAGWithRegPressure(); @@ -205,24 +205,25 @@ void VLIWMachineScheduler::schedule() { // Initialize the strategy before modifying the DAG. SchedImpl->initialize(this); - DEBUG(unsigned maxH = 0; - for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - if (SUnits[su].getHeight() > maxH) - maxH = SUnits[su].getHeight(); - dbgs() << "Max Height " << maxH << "\n";); - DEBUG(unsigned maxD = 0; - for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - if (SUnits[su].getDepth() > maxD) - maxD = SUnits[su].getDepth(); - dbgs() << "Max Depth " << maxD << "\n";); - DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - SUnits[su].dumpAll(this)); + LLVM_DEBUG(unsigned maxH = 0; + for (unsigned su = 0, e = SUnits.size(); su != e; + ++su) if (SUnits[su].getHeight() > maxH) maxH = + SUnits[su].getHeight(); + dbgs() << "Max Height " << maxH << "\n";); + LLVM_DEBUG(unsigned maxD = 0; + for (unsigned su = 0, e = SUnits.size(); su != e; + ++su) if (SUnits[su].getDepth() > maxD) maxD = + SUnits[su].getDepth(); + dbgs() << "Max Depth " << maxD << "\n";); + LLVM_DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su] + .dumpAll(this)); initQueues(TopRoots, BotRoots); bool IsTopNode = false; while (true) { - DEBUG(dbgs() << "** VLIWMachineScheduler::schedule picking next node\n"); + LLVM_DEBUG( + dbgs() << "** VLIWMachineScheduler::schedule picking next node\n"); SUnit *SU = SchedImpl->pickNode(IsTopNode); if (!SU) break; @@ -240,7 +241,7 @@ void VLIWMachineScheduler::schedule() { placeDebugValues(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Final schedule for " << printMBBReference(*begin()->getParent()) << " ***\n"; dumpSchedule(); @@ -379,8 +380,8 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle() { } CheckPending = true; - DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle " - << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle " + << CurrCycle << '\n'); } /// Move the boundary of scheduled code by one SUnit. @@ -404,12 +405,12 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode(SUnit *SU) { // TODO: Check if this SU must end a dispatch group. IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); if (startNewCycle) { - DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n'); bumpCycle(); } else - DEBUG(dbgs() << "*** IssueCount " << IssueCount - << " at cycle " << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** IssueCount " << IssueCount << " at cycle " + << CurrCycle << '\n'); } /// Release pending ready nodes in to the available queue. This makes them @@ -582,22 +583,23 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (!SU || SU->isScheduled) return ResCount; - DEBUG(if (verbose) dbgs() << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); + LLVM_DEBUG(if (verbose) dbgs() + << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); // Forced priority is high. if (SU->isScheduleHigh) { ResCount += PriorityOne; - DEBUG(dbgs() << "H|"); + LLVM_DEBUG(dbgs() << "H|"); } unsigned IsAvailableAmt = 0; // Critical path first. if (Q.getID() == TopQID) { if (Top.isLatencyBound(SU)) { - DEBUG(if (verbose) dbgs() << "LB|"); + LLVM_DEBUG(if (verbose) dbgs() << "LB|"); ResCount += (SU->getHeight() * ScaleTwo); } - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "h" << std::setw(3) << SU->getHeight() << "|"; dbgs() << dbgstr.str(); @@ -608,16 +610,16 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (Top.ResourceModel->isResourceAvailable(SU, true)) { IsAvailableAmt = (PriorityTwo + PriorityThree); ResCount += IsAvailableAmt; - DEBUG(if (verbose) dbgs() << "A|"); + LLVM_DEBUG(if (verbose) dbgs() << "A|"); } else - DEBUG(if (verbose) dbgs() << " |"); + LLVM_DEBUG(if (verbose) dbgs() << " |"); } else { if (Bot.isLatencyBound(SU)) { - DEBUG(if (verbose) dbgs() << "LB|"); + LLVM_DEBUG(if (verbose) dbgs() << "LB|"); ResCount += (SU->getDepth() * ScaleTwo); } - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "d" << std::setw(3) << SU->getDepth() << "|"; dbgs() << dbgstr.str(); @@ -628,9 +630,9 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (Bot.ResourceModel->isResourceAvailable(SU, false)) { IsAvailableAmt = (PriorityTwo + PriorityThree); ResCount += IsAvailableAmt; - DEBUG(if (verbose) dbgs() << "A|"); + LLVM_DEBUG(if (verbose) dbgs() << "A|"); } else - DEBUG(if (verbose) dbgs() << " |"); + LLVM_DEBUG(if (verbose) dbgs() << " |"); } unsigned NumNodesBlocking = 0; @@ -652,7 +654,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, } ResCount += (NumNodesBlocking * ScaleTwo); - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "blk " << std::setw(2) << NumNodesBlocking << ")|"; dbgs() << dbgstr.str(); @@ -674,10 +676,10 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, (Delta.Excess.getUnitInc() || Delta.CriticalMax.getUnitInc() || Delta.CurrentMax.getUnitInc())) ResCount -= IsAvailableAmt; - DEBUG(if (verbose) { - dbgs() << "RP " << Delta.Excess.getUnitInc() << "/" - << Delta.CriticalMax.getUnitInc() <<"/" - << Delta.CurrentMax.getUnitInc() << ")|"; + LLVM_DEBUG(if (verbose) { + dbgs() << "RP " << Delta.Excess.getUnitInc() << "/" + << Delta.CriticalMax.getUnitInc() << "/" + << Delta.CurrentMax.getUnitInc() << ")|"; }); } @@ -689,11 +691,11 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (Q.getID() == TopQID && Top.ResourceModel->isResourceAvailable(SU, true)) { ResCount += PriorityTwo; - DEBUG(if (verbose) dbgs() << "C|"); + LLVM_DEBUG(if (verbose) dbgs() << "C|"); } else if (Q.getID() == BotQID && Bot.ResourceModel->isResourceAvailable(SU, false)) { ResCount += PriorityTwo; - DEBUG(if (verbose) dbgs() << "C|"); + LLVM_DEBUG(if (verbose) dbgs() << "C|"); } } @@ -705,7 +707,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, PI.getLatency() == 0 && Top.ResourceModel->isInPacket(PI.getSUnit())) { ResCount += PriorityThree; - DEBUG(if (verbose) dbgs() << "Z|"); + LLVM_DEBUG(if (verbose) dbgs() << "Z|"); } } } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { @@ -714,7 +716,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, SI.getLatency() == 0 && Bot.ResourceModel->isInPacket(SI.getSUnit())) { ResCount += PriorityThree; - DEBUG(if (verbose) dbgs() << "Z|"); + LLVM_DEBUG(if (verbose) dbgs() << "Z|"); } } } @@ -730,7 +732,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (PI.getLatency() > 0 && Top.ResourceModel->isInPacket(PI.getSUnit())) { ResCount -= PriorityOne; - DEBUG(if (verbose) dbgs() << "D|"); + LLVM_DEBUG(if (verbose) dbgs() << "D|"); } } } else { @@ -738,13 +740,13 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (SI.getLatency() > 0 && Bot.ResourceModel->isInPacket(SI.getSUnit())) { ResCount -= PriorityOne; - DEBUG(if (verbose) dbgs() << "D|"); + LLVM_DEBUG(if (verbose) dbgs() << "D|"); } } } } - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "Total " << std::setw(4) << ResCount << ")"; dbgs() << dbgstr.str(); @@ -762,9 +764,9 @@ ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler:: pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate) { ReadyQueue &Q = Zone.Available; - DEBUG(if (SchedDebugVerboseLevel > 1) - readyQueueVerboseDump(RPTracker, Candidate, Q); - else Q.dump();); + LLVM_DEBUG(if (SchedDebugVerboseLevel > 1) + readyQueueVerboseDump(RPTracker, Candidate, Q); + else Q.dump();); // getMaxPressureDelta temporarily modifies the tracker. RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker); @@ -781,7 +783,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, // Initialize the candidate if needed. if (!Candidate.SU) { - DEBUG(traceCandidate("DCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("DCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -794,7 +796,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, if (CurrentCost < 0 && Candidate.SCost < 0) { if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { - DEBUG(traceCandidate("NCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("NCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -805,7 +807,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, // Best cost. if (CurrentCost > Candidate.SCost) { - DEBUG(traceCandidate("CCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("CCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -818,7 +820,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, unsigned CandWeak = getWeakLeft(Candidate.SU, (Q.getID() == TopQID)); if (CurrWeak != CandWeak) { if (CurrWeak < CandWeak) { - DEBUG(traceCandidate("WCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("WCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -837,7 +839,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, CandSize = Candidate.SU->Preds.size(); } if (CurrSize > CandSize) { - DEBUG(traceCandidate("SPCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("SPCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -855,7 +857,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, if (UseNewerCandidate && CurrentCost == Candidate.SCost) { if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { - DEBUG(traceCandidate("TCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("TCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -877,12 +879,12 @@ SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) { // Schedule as far as possible in the direction of no choice. This is most // efficient, but also provides the best heuristics for CriticalPSets. if (SUnit *SU = Bot.pickOnlyChoice()) { - DEBUG(dbgs() << "Picked only Bottom\n"); + LLVM_DEBUG(dbgs() << "Picked only Bottom\n"); IsTopNode = false; return SU; } if (SUnit *SU = Top.pickOnlyChoice()) { - DEBUG(dbgs() << "Picked only Top\n"); + LLVM_DEBUG(dbgs() << "Picked only Top\n"); IsTopNode = true; return SU; } @@ -900,7 +902,7 @@ SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) { // increase pressure for one of the excess PSets, then schedule in that // direction first to provide more freedom in the other direction. if (BotResult == SingleExcess || BotResult == SingleCritical) { - DEBUG(dbgs() << "Prefered Bottom Node\n"); + LLVM_DEBUG(dbgs() << "Prefered Bottom Node\n"); IsTopNode = false; return BotCand.SU; } @@ -911,29 +913,29 @@ SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) { assert(TopResult != NoCand && "failed to find the first candidate"); if (TopResult == SingleExcess || TopResult == SingleCritical) { - DEBUG(dbgs() << "Prefered Top Node\n"); + LLVM_DEBUG(dbgs() << "Prefered Top Node\n"); IsTopNode = true; return TopCand.SU; } // If either Q has a single candidate that minimizes pressure above the // original region's pressure pick it. if (BotResult == SingleMax) { - DEBUG(dbgs() << "Prefered Bottom Node SingleMax\n"); + LLVM_DEBUG(dbgs() << "Prefered Bottom Node SingleMax\n"); IsTopNode = false; return BotCand.SU; } if (TopResult == SingleMax) { - DEBUG(dbgs() << "Prefered Top Node SingleMax\n"); + LLVM_DEBUG(dbgs() << "Prefered Top Node SingleMax\n"); IsTopNode = true; return TopCand.SU; } if (TopCand.SCost > BotCand.SCost) { - DEBUG(dbgs() << "Prefered Top Node Cost\n"); + LLVM_DEBUG(dbgs() << "Prefered Top Node Cost\n"); IsTopNode = true; return TopCand.SU; } // Otherwise prefer the bottom candidate in node order. - DEBUG(dbgs() << "Prefered Bottom in Node order\n"); + LLVM_DEBUG(dbgs() << "Prefered Bottom in Node order\n"); IsTopNode = false; return BotCand.SU; } @@ -976,11 +978,11 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) { if (SU->isBottomReady()) Bot.removeReady(SU); - DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom") - << " Scheduling instruction in cycle " - << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " (" << - reportPackets() << ")\n"; - SU->dump(DAG)); + LLVM_DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom") + << " Scheduling instruction in cycle " + << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " (" + << reportPackets() << ")\n"; + SU->dump(DAG)); return SU; } diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 3dace168284..9ba964a0aad 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -448,8 +448,8 @@ bool HexagonNewValueJump::isNewValueJumpCandidate( } bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" - << "********** Function: " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" + << "********** Function: " << MF.getName() << "\n"); if (skipFunction(MF.getFunction())) return false; @@ -474,9 +474,10 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { MBBb != MBBe; ++MBBb) { MachineBasicBlock *MBB = &*MBBb; - DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n"); - DEBUG(MBB->dump()); - DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); + LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n"); + LLVM_DEBUG(MBB->dump()); + LLVM_DEBUG(dbgs() << "\n" + << "********** dumping instr bottom up **********\n"); bool foundJump = false; bool foundCompare = false; bool invertPredicate = false; @@ -501,7 +502,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) break; - DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt || MI.getOpcode() == Hexagon::J2_jumptpt || diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 6d9c7820ac8..29c044b3b72 100644 --- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -217,7 +217,7 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, NodeSet Visited, Defs; const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs); if (!P.second) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Unable to collect all reaching defs for use ***\n" << PrintNode<UseNode*>(UN, *DFG) << '\n' << "The program's complexity may exceed the limits.\n"; @@ -226,7 +226,7 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, } const auto &ReachingDefs = P.first; if (ReachingDefs.size() > 1) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Multiple Reaching Defs found!!! ***\n"; for (auto DI : ReachingDefs) { NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI); @@ -244,15 +244,15 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, NodeList &UNodeList) { for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) { - DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG) - << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[DefNode]: " + << Print<NodeAddr<DefNode *>>(DA, *DFG) << "\n"); RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG)); auto UseSet = LV->getAllReachedUses(DR, DA); for (auto UI : UseSet) { NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI); - DEBUG({ + LLVM_DEBUG({ NodeAddr<StmtNode *> TempIA = UA.Addr->getOwner(*DFG); dbgs() << "\t\t\t[Reached Use]: " << Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n"; @@ -262,8 +262,8 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG); NodeId id = PA.Id; const Liveness::RefMap &phiUse = LV->getRealUses(id); - DEBUG(dbgs() << "\t\t\t\tphi real Uses" - << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); + LLVM_DEBUG(dbgs() << "\t\t\t\tphi real Uses" + << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); if (!phiUse.empty()) { for (auto I : phiUse) { if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) @@ -306,7 +306,8 @@ bool HexagonOptAddrMode::isSafeToExtLR(NodeAddr<StmtNode *> SN, NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(LRExtRR, IA); if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) || AA.Addr->getReachingDef() != LRExtRegRD) { - DEBUG(dbgs() << "isSafeToExtLR: Returning false; another reaching def\n"); + LLVM_DEBUG( + dbgs() << "isSafeToExtLR: Returning false; another reaching def\n"); return false; } @@ -396,8 +397,8 @@ bool HexagonOptAddrMode::processAddUses(NodeAddr<StmtNode *> AddSN, NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG); MachineInstr *UseMI = OwnerN.Addr->getCode(); - DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber() - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber() + << ">]: " << *UseMI << "\n"); Changed |= updateAddUses(AddMI, UseMI); } @@ -451,7 +452,7 @@ bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR, } else if (MI.getOpcode() == Hexagon::S2_addasl_rrri) { NodeList AddaslUseList; - DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n"); + LLVM_DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n"); getAllRealUses(SN, AddaslUseList); // Process phi nodes. if (allValidCandidates(SN, AddaslUseList) && @@ -515,8 +516,8 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, } else Changed = false; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -526,8 +527,8 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 4; Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } if (Changed) @@ -568,8 +569,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, OpStart = 3; } Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -578,8 +579,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 3; Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } if (Changed) for (unsigned i = OpStart; i < OpEnd; ++i) @@ -602,7 +603,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, unsigned ImmOpNum) { NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n"); + LLVM_DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n"); NodeList UNodeList; getAllRealUses(SA, UNodeList); @@ -613,11 +614,11 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, "Can't transform this 'AddAsl' instruction!"); NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG) - << "\n"); + LLVM_DEBUG(dbgs() << "[InstrNode]: " + << Print<NodeAddr<InstrNode *>>(UseIA, *DFG) << "\n"); MachineInstr *UseMI = UseIA.Addr->getCode(); - DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) + << ">]: " << *UseMI << "\n"); const MCInstrDesc &UseMID = UseMI->getDesc(); assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset); @@ -695,9 +696,9 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { !MI->getOperand(2).isImm() || HII->isConstExtended(*MI))) continue; - DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) << "]: " - << *MI << "\n\t[InstrNode]: " - << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n'); + LLVM_DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) + << "]: " << *MI << "\n\t[InstrNode]: " + << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n'); NodeList UNodeList; getAllRealUses(SA, UNodeList); @@ -733,8 +734,9 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { bool KeepTfr = false; - DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() << "\n"); - DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n"); + LLVM_DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() + << "\n"); + LLVM_DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n"); for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) { NodeAddr<UseNode *> UseN = *I; assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) && @@ -742,8 +744,8 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG); MachineInstr *UseMI = OwnerN.Addr->getCode(); - DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) + << ">]: " << *UseMI << "\n"); int UseMOnum = -1; unsigned NumOperands = UseMI->getNumOperands(); @@ -793,8 +795,8 @@ bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) { Deleted.clear(); NodeAddr<FuncNode *> FA = DFG->getFunc(); - DEBUG(dbgs() << "==== [RefMap#]=====:\n " - << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n"); + LLVM_DEBUG(dbgs() << "==== [RefMap#]=====:\n " + << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n"); for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG)) Changed |= processBlock(BA); diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index 386e6cbad1f..e018785f24d 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -246,7 +246,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) { if (FixedRegs[x]) continue; unsigned R = TargetRegisterInfo::index2VirtReg(x); - DEBUG(dbgs() << printReg(R, TRI) << " ~~"); + LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~"); USet &Asc = AssocMap[R]; for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end(); U != Z; ++U) { @@ -269,13 +269,13 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) { unsigned u = TargetRegisterInfo::virtReg2Index(T); if (FixedRegs[u]) continue; - DEBUG(dbgs() << ' ' << printReg(T, TRI)); + LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI)); Asc.insert(T); // Make it symmetric. AssocMap[T].insert(R); } } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } UUMap R2P; @@ -468,7 +468,7 @@ bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM) if (FixedNum > 0 && LoopPhiNum > 0) TotalP -= 20*LoopPhiNum; - DEBUG(dbgs() << "Partition profit: " << TotalP << '\n'); + LLVM_DEBUG(dbgs() << "Partition profit: " << TotalP << '\n'); if (SplitAll) return true; return TotalP > 0; @@ -563,7 +563,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L, Rs.insert(CmpR1); Rs.insert(CmpR2); - DEBUG({ + LLVM_DEBUG({ dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: "; dump_partition(dbgs(), Rs, *TRI); dbgs() << '\n'; @@ -996,7 +996,7 @@ bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI, const UUPairMap &PairMap) { using namespace Hexagon; - DEBUG(dbgs() << "Splitting: " << *MI); + LLVM_DEBUG(dbgs() << "Splitting: " << *MI); bool Split = false; unsigned Opc = MI->getOpcode(); @@ -1130,8 +1130,8 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) { const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass; bool Changed = false; - DEBUG(dbgs() << "Splitting partition: "; dump_partition(dbgs(), Part, *TRI); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Splitting partition: "; + dump_partition(dbgs(), Part, *TRI); dbgs() << '\n'); UUPairMap PairMap; @@ -1148,8 +1148,9 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) { unsigned LoR = MRI->createVirtualRegister(IntRC); unsigned HiR = MRI->createVirtualRegister(IntRC); - DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> " - << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> " + << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) + << '\n'); PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR))); } @@ -1189,8 +1190,8 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(dbgs() << "Splitting double registers in function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Splitting double registers in function: " + << MF.getName() << '\n'); auto &ST = MF.getSubtarget<HexagonSubtarget>(); TRI = ST.getRegisterInfo(); @@ -1204,7 +1205,7 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) { collectIndRegs(IRM); partitionRegisters(P2Rs); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Register partitioning: (partition #0 is fixed)\n"; for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) { dbgs() << '#' << I->first << " -> "; @@ -1222,7 +1223,8 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) { if (Limit >= 0 && Counter >= Limit) break; USet &Part = I->second; - DEBUG(dbgs() << "Calculating profit for partition #" << I->first << '\n'); + LLVM_DEBUG(dbgs() << "Calculating profit for partition #" << I->first + << '\n'); if (!isProfitable(Part, IRM)) continue; Counter++; diff --git a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp index 0f058106e32..991af047387 100644 --- a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -474,7 +474,7 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG, // from OG was (in the order in which they appeared in the basic block). // (The ordering in OG does not have to match the order in the basic block.) bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Replacing:\n"; for (auto I : OG) dbgs() << " " << *I; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index ea86c9c42f4..e771f383dff 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -74,7 +74,7 @@ static cl::opt<bool> if (TraceGVPlacement) { \ TRACE_TO(errs(), X); \ } else { \ - DEBUG(TRACE_TO(dbgs(), X)); \ + LLVM_DEBUG(TRACE_TO(dbgs(), X)); \ } \ } while (false) #endif @@ -200,11 +200,11 @@ MCSection *HexagonTargetObjectFile::getExplicitSectionGlobal( bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const { // Only global variables, not functions. - DEBUG(dbgs() << "Checking if value is in small-data, -G" - << SmallDataThreshold << ": \"" << GO->getName() << "\": "); + LLVM_DEBUG(dbgs() << "Checking if value is in small-data, -G" + << SmallDataThreshold << ": \"" << GO->getName() << "\": "); const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GO); if (!GVar) { - DEBUG(dbgs() << "no, not a global variable\n"); + LLVM_DEBUG(dbgs() << "no, not a global variable\n"); return false; } @@ -213,19 +213,19 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, // small data or not. This is how we can support mixing -G0/-G8 in LTO. if (GVar->hasSection()) { bool IsSmall = isSmallDataSection(GVar->getSection()); - DEBUG(dbgs() << (IsSmall ? "yes" : "no") << ", has section: " - << GVar->getSection() << '\n'); + LLVM_DEBUG(dbgs() << (IsSmall ? "yes" : "no") + << ", has section: " << GVar->getSection() << '\n'); return IsSmall; } if (GVar->isConstant()) { - DEBUG(dbgs() << "no, is a constant\n"); + LLVM_DEBUG(dbgs() << "no, is a constant\n"); return false; } bool IsLocal = GVar->hasLocalLinkage(); if (!StaticsInSData && IsLocal) { - DEBUG(dbgs() << "no, is static\n"); + LLVM_DEBUG(dbgs() << "no, is static\n"); return false; } @@ -234,7 +234,7 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, GType = PT->getElementType(); if (isa<ArrayType>(GType)) { - DEBUG(dbgs() << "no, is an array\n"); + LLVM_DEBUG(dbgs() << "no, is an array\n"); return false; } @@ -244,22 +244,22 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, // these objects end up in the sdata, the references will still be valid. if (StructType *ST = dyn_cast<StructType>(GType)) { if (ST->isOpaque()) { - DEBUG(dbgs() << "no, has opaque type\n"); + LLVM_DEBUG(dbgs() << "no, has opaque type\n"); return false; } } unsigned Size = GVar->getParent()->getDataLayout().getTypeAllocSize(GType); if (Size == 0) { - DEBUG(dbgs() << "no, has size 0\n"); + LLVM_DEBUG(dbgs() << "no, has size 0\n"); return false; } if (Size > SmallDataThreshold) { - DEBUG(dbgs() << "no, size exceeds sdata threshold: " << Size << '\n'); + LLVM_DEBUG(dbgs() << "no, size exceeds sdata threshold: " << Size << '\n'); return false; } - DEBUG(dbgs() << "yes\n"); + LLVM_DEBUG(dbgs() << "yes\n"); return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 2ae48e3d68f..e44c7237a7e 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -375,7 +375,7 @@ bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI, void HexagonPacketizerList::cleanUpDotCur() { MachineInstr *MI = nullptr; for (auto BI : CurrentPacketMIs) { - DEBUG(dbgs() << "Cleanup packet has "; BI->dump();); + LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump();); if (HII->isDotCurInst(*BI)) { MI = BI; continue; @@ -390,7 +390,7 @@ void HexagonPacketizerList::cleanUpDotCur() { return; // We did not find a use of the CUR, so de-cur it. MI->setDesc(HII->get(HII->getNonDotCurOp(*MI))); - DEBUG(dbgs() << "Demoted CUR "; MI->dump();); + LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump();); } // Check to see if an instruction can be dot cur. @@ -414,11 +414,10 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI, return false; // Make sure candidate instruction uses cur. - DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; - MI.dump(); - dbgs() << "in packet\n";); + LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump(); + dbgs() << "in packet\n";); MachineInstr &MJ = *MII; - DEBUG({ + LLVM_DEBUG({ dbgs() << "Checking CUR against "; MJ.dump(); }); @@ -433,12 +432,12 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI, // Check for existing uses of a vector register within the packet which // would be affected by converting a vector load into .cur formt. for (auto BI : CurrentPacketMIs) { - DEBUG(dbgs() << "packet has "; BI->dump();); + LLVM_DEBUG(dbgs() << "packet has "; BI->dump();); if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo())) return false; } - DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump();); + LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump();); // We can convert the opcode into a .cur. return true; } @@ -1762,7 +1761,7 @@ void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, bool memShufDisabled = getmemShufDisabled(); if (memShufDisabled && !foundLSInPacket()) { setmemShufDisabled(false); - DEBUG(dbgs() << " Not added to NoShufPacket\n"); + LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n"); } memShufDisabled = getmemShufDisabled(); @@ -1781,7 +1780,7 @@ void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, CurrentPacketMIs.clear(); ResourceTracker->clearResources(); - DEBUG(dbgs() << "End packet\n"); + LLVM_DEBUG(dbgs() << "End packet\n"); } bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) { diff --git a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp index e94c2483751..9d1073346c7 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp @@ -364,17 +364,18 @@ bool HexagonVectorLoopCarriedReuse::canReplace(Instruction *I) { if (II && (II->getIntrinsicID() == Intrinsic::hexagon_V6_hi || II->getIntrinsicID() == Intrinsic::hexagon_V6_lo)) { - DEBUG(dbgs() << "Not considering for reuse: " << *II << "\n"); + LLVM_DEBUG(dbgs() << "Not considering for reuse: " << *II << "\n"); return false; } return true; } void HexagonVectorLoopCarriedReuse::findValueToReuse() { for (auto *D : Dependences) { - DEBUG(dbgs() << "Processing dependence " << *(D->front()) << "\n"); + LLVM_DEBUG(dbgs() << "Processing dependence " << *(D->front()) << "\n"); if (D->iterations() > HexagonVLCRIterationLim) { - DEBUG(dbgs() << - ".. Skipping because number of iterations > than the limit\n"); + LLVM_DEBUG( + dbgs() + << ".. Skipping because number of iterations > than the limit\n"); continue; } @@ -382,7 +383,8 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { Instruction *BEInst = D->back(); int Iters = D->iterations(); BasicBlock *BB = PN->getParent(); - DEBUG(dbgs() << "Checking if any uses of " << *PN << " can be reused\n"); + LLVM_DEBUG(dbgs() << "Checking if any uses of " << *PN + << " can be reused\n"); SmallVector<Instruction *, 4> PNUsers; for (auto UI = PN->use_begin(), E = PN->use_end(); UI != E; ++UI) { @@ -392,7 +394,8 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { if (User->getParent() != BB) continue; if (ReplacedInsts.count(User)) { - DEBUG(dbgs() << *User << " has already been replaced. Skipping...\n"); + LLVM_DEBUG(dbgs() << *User + << " has already been replaced. Skipping...\n"); continue; } if (isa<PHINode>(User)) @@ -404,7 +407,7 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { PNUsers.push_back(User); } - DEBUG(dbgs() << PNUsers.size() << " use(s) of the PHI in the block\n"); + LLVM_DEBUG(dbgs() << PNUsers.size() << " use(s) of the PHI in the block\n"); // For each interesting use I of PN, find an Instruction BEUser that // performs the same operation as I on BEInst and whose other operands, @@ -440,7 +443,7 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { } } if (BEUser) { - DEBUG(dbgs() << "Found Value for reuse.\n"); + LLVM_DEBUG(dbgs() << "Found Value for reuse.\n"); ReuseCandidate.Inst2Replace = I; ReuseCandidate.BackedgeInst = BEUser; return; @@ -461,7 +464,7 @@ Value *HexagonVectorLoopCarriedReuse::findValueInBlock(Value *Op, } void HexagonVectorLoopCarriedReuse::reuseValue() { - DEBUG(dbgs() << ReuseCandidate); + LLVM_DEBUG(dbgs() << ReuseCandidate); Instruction *Inst2Replace = ReuseCandidate.Inst2Replace; Instruction *BEInst = ReuseCandidate.BackedgeInst; int NumOperands = Inst2Replace->getNumOperands(); @@ -486,7 +489,7 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { } } - DEBUG(dbgs() << "reuseValue is making the following changes\n"); + LLVM_DEBUG(dbgs() << "reuseValue is making the following changes\n"); SmallVector<Instruction *, 4> InstsInPreheader; for (int i = 0; i < Iterations; ++i) { @@ -507,8 +510,8 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { InstsInPreheader.push_back(InstInPreheader); InstInPreheader->setName(Inst2Replace->getName() + ".hexagon.vlcr"); InstInPreheader->insertBefore(LoopPH->getTerminator()); - DEBUG(dbgs() << "Added " << *InstInPreheader << " to " << LoopPH->getName() - << "\n"); + LLVM_DEBUG(dbgs() << "Added " << *InstInPreheader << " to " + << LoopPH->getName() << "\n"); } BasicBlock *BB = BEInst->getParent(); IRBuilder<> IRB(BB); @@ -520,7 +523,8 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { NewPhi = IRB.CreatePHI(InstInPreheader->getType(), 2); NewPhi->addIncoming(InstInPreheader, LoopPH); NewPhi->addIncoming(BEVal, BB); - DEBUG(dbgs() << "Adding " << *NewPhi << " to " << BB->getName() << "\n"); + LLVM_DEBUG(dbgs() << "Adding " << *NewPhi << " to " << BB->getName() + << "\n"); BEVal = NewPhi; } // We are in LCSSA form. So, a value defined inside the Loop is used only @@ -539,7 +543,7 @@ bool HexagonVectorLoopCarriedReuse::doVLCR() { bool Changed = false; bool Continue; - DEBUG(dbgs() << "Working on Loop: " << *CurLoop->getHeader() << "\n"); + LLVM_DEBUG(dbgs() << "Working on Loop: " << *CurLoop->getHeader() << "\n"); do { // Reset datastructures. Dependences.clear(); @@ -626,10 +630,9 @@ void HexagonVectorLoopCarriedReuse::findLoopCarriedDeps() { else delete D; } - DEBUG(dbgs() << "Found " << Dependences.size() << " dependences\n"); - DEBUG(for (size_t i = 0; i < Dependences.size(); ++i) { - dbgs() << *Dependences[i] << "\n"; - }); + LLVM_DEBUG(dbgs() << "Found " << Dependences.size() << " dependences\n"); + LLVM_DEBUG(for (size_t i = 0; i < Dependences.size(); + ++i) { dbgs() << *Dependences[i] << "\n"; }); } Pass *llvm::createHexagonVectorLoopCarriedReusePass() { diff --git a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp index ddd668b2cb1..18d2f2f4acd 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -144,14 +144,15 @@ bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) { unsigned Reg = 0; if (getInstrVecReg(*MII, Reg)) { VecPrintList.push_back((&*MII)); - DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump()); + LLVM_DEBUG(dbgs() << "Found vector reg inside bundle \n"; + MII->dump()); } } } else { unsigned Reg = 0; if (getInstrVecReg(MI, Reg)) { VecPrintList.push_back(&MI); - DEBUG(dbgs() << "Found vector reg \n"; MI.dump()); + LLVM_DEBUG(dbgs() << "Found vector reg \n"; MI.dump()); } } } @@ -163,33 +164,33 @@ bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) { for (auto *I : VecPrintList) { DebugLoc DL = I->getDebugLoc(); MachineBasicBlock *MBB = I->getParent(); - DEBUG(dbgs() << "Evaluating V MI\n"; I->dump()); + LLVM_DEBUG(dbgs() << "Evaluating V MI\n"; I->dump()); unsigned Reg = 0; if (!getInstrVecReg(*I, Reg)) llvm_unreachable("Need a vector reg"); MachineBasicBlock::instr_iterator MII = I->getIterator(); if (I->isInsideBundle()) { - DEBUG(dbgs() << "add to end of bundle\n"; I->dump()); + LLVM_DEBUG(dbgs() << "add to end of bundle\n"; I->dump()); while (MBB->instr_end() != MII && MII->isInsideBundle()) MII++; } else { - DEBUG(dbgs() << "add after instruction\n"; I->dump()); + LLVM_DEBUG(dbgs() << "add after instruction\n"; I->dump()); MII++; } if (MBB->instr_end() == MII) continue; if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { - DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n'); + LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); addAsmInstr(MBB, Reg, MII, DL, QII, Fn); } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { - DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n'); + LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, MII, DL, QII, Fn); addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, MII, DL, QII, Fn); } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { - DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n'); + LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); addAsmInstr(MBB, Reg, MII, DL, QII, Fn); } else llvm_unreachable("Bad Vector reg"); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index fe54c19370b..584f35e0051 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -510,17 +510,15 @@ public: break; } - DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" << - (unsigned)Kind << ")\n"); - DEBUG(uint32_t OldData = 0; - for (unsigned i = 0; i < NumBytes; i++) - OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); - dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << - ": AValue=0x"; dbgs().write_hex(FixupValue) << - ": Offset=" << Offset << - ": Size=" << Data.size() << - ": OInst=0x"; dbgs().write_hex(OldData) << - ": Reloc=0x"; dbgs().write_hex(Reloc);); + LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" + << (unsigned)Kind << ")\n"); + LLVM_DEBUG( + uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |= + (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); + dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x"; + dbgs().write_hex(FixupValue) + << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x"; + dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc);); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. The Value has been "split up" into the @@ -530,10 +528,10 @@ public: InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc } - DEBUG(uint32_t NewData = 0; - for (unsigned i = 0; i < NumBytes; i++) - NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); - dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); + LLVM_DEBUG(uint32_t NewData = 0; + for (unsigned i = 0; i < NumBytes; i++) NewData |= + (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); + dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); } bool isInstRelaxable(MCInst const &HMI) const { @@ -689,8 +687,9 @@ public: ParseEnd = 0x0000c000; // End of packet parse-bits. while(Count % HEXAGON_INSTR_SIZE) { - DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << - Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); + LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" + << Count % HEXAGON_INSTR_SIZE << "/" + << HEXAGON_INSTR_SIZE << "\n"); --Count; OW->write8(0); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 91500d909a1..555386b8464 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -372,7 +372,7 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, MCInst &HMB = const_cast<MCInst &>(MI); assert(HexagonMCInstrInfo::isBundle(HMB)); - DEBUG(dbgs() << "Encoding bundle\n";); + LLVM_DEBUG(dbgs() << "Encoding bundle\n";); State.Addend = 0; State.Extended = false; State.Bundle = &MI; @@ -415,8 +415,8 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, // in the first place! assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && "pseudo-instruction found"); - DEBUG(dbgs() << "Encoding insn `" - << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); + LLVM_DEBUG(dbgs() << "Encoding insn `" + << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); Binary = getBinaryCodeForInstr(MI, Fixups, STI); unsigned Opc = MI.getOpcode(); @@ -424,8 +424,8 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, // Check for unimplemented instructions. Immediate extenders // are encoded as zero, so they need to be accounted for. if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) { - DEBUG(dbgs() << "Unimplemented inst `" - << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); + LLVM_DEBUG(dbgs() << "Unimplemented inst `" + << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); llvm_unreachable("Unimplemented Instruction"); } Binary |= Parse; @@ -630,13 +630,12 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, unsigned Opc = MCID.getOpcode(); unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); - DEBUG(dbgs() << "----------------------------------------\n" - << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) - << "\nOpcode: " << Opc - << "\nRelocation bits: " << FixupWidth - << "\nAddend: " << State.Addend - << "\nVariant: " << unsigned(VarKind) - << "\n----------------------------------------\n"); + LLVM_DEBUG(dbgs() << "----------------------------------------\n" + << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) + << "\nOpcode: " << Opc << "\nRelocation bits: " + << FixupWidth << "\nAddend: " << State.Addend + << "\nVariant: " << unsigned(VarKind) + << "\n----------------------------------------\n"); // Pick the applicable fixup kind for the symbol. // Handle special cases first, the rest will be looked up in the tables. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp index 127c97e342d..3eaef9ac741 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp @@ -205,7 +205,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, switch (L.getOpcode()) { default: - DEBUG(dbgs() << "Possible compound ignored\n"); + LLVM_DEBUG(dbgs() << "Possible compound ignored\n"); return CompoundInsn; case Hexagon::A2_tfrsi: @@ -233,7 +233,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpeq: - DEBUG(dbgs() << "CX: C2_cmpeq\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpeq\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -246,7 +246,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgt: - DEBUG(dbgs() << "CX: C2_cmpgt\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgt\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -259,7 +259,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgtu: - DEBUG(dbgs() << "CX: C2_cmpgtu\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgtu\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -272,7 +272,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpeqi: - DEBUG(dbgs() << "CX: C2_cmpeqi\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpeqi\n"); Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); (void)Success; assert(Success); @@ -290,7 +290,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgti: - DEBUG(dbgs() << "CX: C2_cmpgti\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgti\n"); Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); (void)Success; assert(Success); @@ -308,7 +308,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgtui: - DEBUG(dbgs() << "CX: C2_cmpgtui\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgtui\n"); Rs = L.getOperand(1); compoundOpcode = cmpgtuiBitOpcode[getCompoundOp(R)]; CompoundInsn = new (Context) MCInst; @@ -319,7 +319,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::S2_tstbit_i: - DEBUG(dbgs() << "CX: S2_tstbit_i\n"); + LLVM_DEBUG(dbgs() << "CX: S2_tstbit_i\n"); Rs = L.getOperand(1); compoundOpcode = tstBitOpcode[getCompoundOp(R)]; CompoundInsn = new (Context) MCInst; @@ -372,14 +372,14 @@ static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, BExtended = true; continue; } - DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," - << Inst->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," + << Inst->getOpcode() << "\n"); if (isOrderedCompoundPair(*Inst, BExtended, *JumpInst, JExtended)) { MCInst *CompoundInsn = getCompoundInsn(Context, *Inst, *JumpInst); if (CompoundInsn) { - DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," - << JumpInst->getOpcode() << " Compounds to " - << CompoundInsn->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," + << JumpInst->getOpcode() << " Compounds to " + << CompoundInsn->getOpcode() << "\n"); J->setInst(CompoundInsn); MCI.erase(B); return true; @@ -422,7 +422,7 @@ void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo co if (StartedValid && !llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI)) { - DEBUG(dbgs() << "Found ERROR\n"); + LLVM_DEBUG(dbgs() << "Found ERROR\n"); MCI = OriginalBundle; } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index fd064416fd9..b208a366812 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -1045,8 +1045,8 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, bool bisReversable = true; if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) && isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) { - DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j - << "\n"); + LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j + << "\n"); bisReversable = false; } if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf @@ -1066,14 +1066,14 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, // Save off pairs for duplex checking. duplexToTry.push_back(DuplexCandidate(j, k, iClass)); - DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); continue; } else { - DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } // Try reverse. @@ -1091,13 +1091,15 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, // Save off pairs for duplex checking. duplexToTry.push_back(DuplexCandidate(k, j, iClass)); - DEBUG(dbgs() << "adding pair:" << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() + << "adding pair:" << k << "," << j << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } else { - DEBUG(dbgs() << "skipping pair: " << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() + << "skipping pair: " << k << "," << j << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 7bd54fdfa3d..4281144acae 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -38,7 +38,8 @@ void HexagonMCShuffler::init(MCInst &MCB) { // Copy the bundle for the shuffling. for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { MCInst &MI = *const_cast<MCInst *>(I.getInst()); - DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) << '\n'); + LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) + << '\n'); assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); if (!HexagonMCInstrInfo::isImmext(MI)) { @@ -98,7 +99,7 @@ bool HexagonMCShuffler::reshuffleTo(MCInst &MCB) { copyTo(MCB); return true; } - DEBUG(MCB.dump()); + LLVM_DEBUG(MCB.dump()); return false; } @@ -119,10 +120,10 @@ bool llvm::HexagonMCShuffle(MCContext &Context, bool Fatal, // * %d7 = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); + LLVM_DEBUG(dbgs() << "Skipping empty bundle"); return false; } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); + LLVM_DEBUG(dbgs() << "Skipping stand-alone insn"); return false; } @@ -144,10 +145,10 @@ llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, // * %d7 = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); + LLVM_DEBUG(dbgs() << "Skipping empty bundle"); return false; } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); + LLVM_DEBUG(dbgs() << "Skipping stand-alone insn"); return false; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 7709a0f6162..59f3caa6af9 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -641,14 +641,14 @@ bool HexagonShuffler::shuffle() { } for (iterator ISJ = begin(); ISJ != end(); ++ISJ) - DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { + LLVM_DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { dbgs() << '/'; dbgs().write_hex(ISJ->CVI.getUnits()) << '|'; dbgs() << ISJ->CVI.getLanes(); } dbgs() << ':' << HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode(); - dbgs() << '\n'); - DEBUG(dbgs() << '\n'); + dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); return Ok; } diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp index 19dcc7d00e3..5081cfbe492 100644 --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -275,7 +275,7 @@ void LanaiDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); return; } diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 33455137acc..22fcf473d0c 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -484,8 +484,8 @@ SDValue LanaiTargetLowering::LowerCCCArguments( break; } default: - DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: " - << RegVT.getEVTString() << "\n"); + LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: " + << RegVT.getEVTString() << "\n"); llvm_unreachable("unhandled argument type"); } } else { diff --git a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp index 87c320aa76a..2b349540554 100644 --- a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp +++ b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -138,15 +138,15 @@ bool MSP430BSel::expandBranches(OffsetVector &BlockOffsets) { continue; } - DEBUG(dbgs() << " Found a branch that needs expanding, " - << printMBBReference(*DestBB) << ", Distance " - << BranchDistance << "\n"); + LLVM_DEBUG(dbgs() << " Found a branch that needs expanding, " + << printMBBReference(*DestBB) << ", Distance " + << BranchDistance << "\n"); // If JCC is not the last instruction we need to split the MBB. if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) { - DEBUG(dbgs() << " Found a basic block that needs to be split, " - << printMBBReference(*MBB) << "\n"); + LLVM_DEBUG(dbgs() << " Found a basic block that needs to be split, " + << printMBBReference(*MBB) << "\n"); // Create a new basic block. MachineBasicBlock *NewBB = @@ -229,7 +229,7 @@ bool MSP430BSel::runOnMachineFunction(MachineFunction &mf) { if (!BranchSelectEnabled) return false; - DEBUG(dbgs() << "\n********** " << getPassName() << " **********\n"); + LLVM_DEBUG(dbgs() << "\n********** " << getPassName() << " **********\n"); // BlockOffsets - Contains the distance from the beginning of the function to // the beginning of each basic block. diff --git a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 05b3bf70eef..005f5f44a63 100644 --- a/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -180,7 +180,7 @@ bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) } bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) { - DEBUG(errs() << "MatchAddress: "; AM.dump()); + LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump()); switch (N.getOpcode()) { default: break; @@ -384,9 +384,7 @@ void MSP430DAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; - Node->dump(CurDAG); - errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); Node->setNodeId(-1); return; } diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b3cfc869f29..4e28d910ecb 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1496,7 +1496,7 @@ public: static std::unique_ptr<MipsOperand> createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { - DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n"); + LLVM_DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n"); return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser); } @@ -5698,7 +5698,7 @@ unsigned MipsAsmParser::getReg(int RC, int RegNo) { bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { MCAsmParser &Parser = getParser(); - DEBUG(dbgs() << "parseOperand\n"); + LLVM_DEBUG(dbgs() << "parseOperand\n"); // Check if the current operand has a custom associated parser, if so, try to // custom parse the operand, or fallback to the general approach. @@ -5711,7 +5711,7 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { if (ResTy == MatchOperand_ParseFail) return true; - DEBUG(dbgs() << ".. Generic Parser\n"); + LLVM_DEBUG(dbgs() << ".. Generic Parser\n"); switch (getLexer().getKind()) { case AsmToken::Dollar: { @@ -5741,7 +5741,7 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { return false; } default: { - DEBUG(dbgs() << ".. generic integer expression\n"); + LLVM_DEBUG(dbgs() << ".. generic integer expression\n"); const MCExpr *Expr; SMLoc S = Parser.getTok().getLoc(); // Start location of the operand. @@ -5814,7 +5814,7 @@ bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { OperandMatchResultTy MipsAsmParser::parseMemOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); - DEBUG(dbgs() << "parseMemOperand\n"); + LLVM_DEBUG(dbgs() << "parseMemOperand\n"); const MCExpr *IdVal = nullptr; SMLoc S; bool isParenExpr = false; @@ -6044,13 +6044,13 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { auto Token = Parser.getLexer().peekTok(false); if (Token.is(AsmToken::Identifier)) { - DEBUG(dbgs() << ".. identifier\n"); + LLVM_DEBUG(dbgs() << ".. identifier\n"); StringRef Identifier = Token.getIdentifier(); OperandMatchResultTy ResTy = matchAnyRegisterNameWithoutDollar(Operands, Identifier, S); return ResTy; } else if (Token.is(AsmToken::Integer)) { - DEBUG(dbgs() << ".. integer\n"); + LLVM_DEBUG(dbgs() << ".. integer\n"); int64_t RegNum = Token.getIntVal(); if (RegNum < 0 || RegNum > 31) { // Show the error, but treat invalid register @@ -6064,7 +6064,7 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { return MatchOperand_Success; } - DEBUG(dbgs() << Parser.getTok().getKind() << "\n"); + LLVM_DEBUG(dbgs() << Parser.getTok().getKind() << "\n"); return MatchOperand_NoMatch; } @@ -6072,22 +6072,22 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { OperandMatchResultTy MipsAsmParser::parseAnyRegister(OperandVector &Operands) { MCAsmParser &Parser = getParser(); - DEBUG(dbgs() << "parseAnyRegister\n"); + LLVM_DEBUG(dbgs() << "parseAnyRegister\n"); auto Token = Parser.getTok(); SMLoc S = Token.getLoc(); if (Token.isNot(AsmToken::Dollar)) { - DEBUG(dbgs() << ".. !$ -> try sym aliasing\n"); + LLVM_DEBUG(dbgs() << ".. !$ -> try sym aliasing\n"); if (Token.is(AsmToken::Identifier)) { if (searchSymbolAlias(Operands)) return MatchOperand_Success; } - DEBUG(dbgs() << ".. !symalias -> NoMatch\n"); + LLVM_DEBUG(dbgs() << ".. !symalias -> NoMatch\n"); return MatchOperand_NoMatch; } - DEBUG(dbgs() << ".. $\n"); + LLVM_DEBUG(dbgs() << ".. $\n"); OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar(Operands, S); if (ResTy == MatchOperand_Success) { @@ -6100,7 +6100,7 @@ MipsAsmParser::parseAnyRegister(OperandVector &Operands) { OperandMatchResultTy MipsAsmParser::parseJumpTarget(OperandVector &Operands) { MCAsmParser &Parser = getParser(); - DEBUG(dbgs() << "parseJumpTarget\n"); + LLVM_DEBUG(dbgs() << "parseJumpTarget\n"); SMLoc S = getLexer().getLoc(); @@ -6344,7 +6344,7 @@ bool MipsAsmParser::parseBracketSuffix(StringRef Name, bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { MCAsmParser &Parser = getParser(); - DEBUG(dbgs() << "ParseInstruction\n"); + LLVM_DEBUG(dbgs() << "ParseInstruction\n"); // We have reached first instruction, module directive are now forbidden. getTargetStreamer().forbidModuleDirective(); diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index f7d80b40c3f..4cbfca4c643 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1225,7 +1225,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, return MCDisassembler::Fail; if (hasMips32r6()) { - DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); + LLVM_DEBUG( + dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); // Calling the auto-generated decoder function for microMIPS32R6 // 16-bit instructions. Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, @@ -1236,7 +1237,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } } - DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); + LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); // Calling the auto-generated decoder function for microMIPS 16-bit // instructions. Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, @@ -1251,7 +1252,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, return MCDisassembler::Fail; if (hasMips32r6()) { - DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); + LLVM_DEBUG( + dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, this, STI); @@ -1261,7 +1263,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } } - DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); + LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, this, STI); @@ -1271,7 +1273,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (isFP64()) { - DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); + LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { @@ -1300,7 +1302,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, Size = 4; if (hasCOP3()) { - DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); + LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1308,7 +1310,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (hasMips32r6() && isGP64()) { - DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); + LLVM_DEBUG( + dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1316,7 +1319,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (hasMips32r6() && isPTR64()) { - DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + LLVM_DEBUG( + dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1324,7 +1328,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (hasMips32r6()) { - DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1332,7 +1336,8 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (hasMips2() && isPTR64()) { - DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + LLVM_DEBUG( + dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1340,7 +1345,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (hasCnMips()) { - DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); + LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1348,7 +1353,7 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (isGP64()) { - DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); + LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) @@ -1356,14 +1361,15 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } if (isFP64()) { - DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); + LLVM_DEBUG( + dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) return Result; } - DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); + LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index 94a196e0c00..fbc64426c9d 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -116,15 +116,15 @@ static InputIt find_best(InputIt First, InputIt Last, UnaryPredicate Predicate, for (InputIt I = First; I != Last; ++I) { unsigned Matched = Predicate(*I); if (Matched != FindBest_NoMatch) { - DEBUG(dbgs() << std::distance(First, I) << " is a match ("; - I->print(dbgs()); dbgs() << ")\n"); + LLVM_DEBUG(dbgs() << std::distance(First, I) << " is a match ("; + I->print(dbgs()); dbgs() << ")\n"); if (Best == Last || BetterThan(*I, *Best)) { - DEBUG(dbgs() << ".. and it beats the last one\n"); + LLVM_DEBUG(dbgs() << ".. and it beats the last one\n"); Best = I; } } if (Matched == FindBest_PerfectMatch) { - DEBUG(dbgs() << ".. and it is unbeatable\n"); + LLVM_DEBUG(dbgs() << ".. and it is unbeatable\n"); break; } } @@ -444,7 +444,7 @@ void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm, std::list<MipsRelocationEntry> Sorted; std::list<ELFRelocationEntry> Remainder; - DEBUG(dumpRelocs("R: ", Relocs)); + LLVM_DEBUG(dumpRelocs("R: ", Relocs)); // Separate the movable relocations (AHL relocations using the high bits) from // the immobile relocations (everything else). This does not preserve high/low @@ -455,7 +455,7 @@ void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm, }); for (auto &R : Remainder) { - DEBUG(dbgs() << "Matching: " << R << "\n"); + LLVM_DEBUG(dbgs() << "Matching: " << R << "\n"); unsigned MatchingType = getMatchingLoType(R); assert(MatchingType != ELF::R_MIPS_NONE && @@ -490,7 +490,7 @@ void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm, Sorted.insert(InsertionPoint, R)->Matched = true; } - DEBUG(dumpRelocs("S: ", Sorted)); + LLVM_DEBUG(dumpRelocs("S: ", Sorted)); assert(Relocs.size() == Sorted.size() && "Some relocs were not consumed"); diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp index f2e014084e4..301a6c7dcd6 100644 --- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp +++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp @@ -444,12 +444,12 @@ bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI, enum OperandTransfer OpTransfer = Entry.TransferOperands(); - DEBUG(dbgs() << "Converting 32-bit: " << *MI); + LLVM_DEBUG(dbgs() << "Converting 32-bit: " << *MI); ++NumReduced; if (OpTransfer == OT_OperandsAll) { MI->setDesc(MipsII->get(Entry.NarrowOpc())); - DEBUG(dbgs() << " to 16-bit: " << *MI); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MI); return true; } else { MachineBasicBlock &MBB = *MI->getParent(); @@ -484,7 +484,7 @@ bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI, // Transfer MI flags. MIB.setMIFlags(MI->getFlags()); - DEBUG(dbgs() << " to 16-bit: " << *MIB); + LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB); MBB.erase_instr(MI); return true; } diff --git a/llvm/lib/Target/Mips/Mips16HardFloat.cpp b/llvm/lib/Target/Mips/Mips16HardFloat.cpp index 682ea5c4ed7..c310d9491af 100644 --- a/llvm/lib/Target/Mips/Mips16HardFloat.cpp +++ b/llvm/lib/Target/Mips/Mips16HardFloat.cpp @@ -482,11 +482,11 @@ static void createFPFnStub(Function *F, Module *M, FPParamVariant PV, // remove the use-soft-float attribute static void removeUseSoftFloat(Function &F) { AttrBuilder B; - DEBUG(errs() << "removing -use-soft-float\n"); + LLVM_DEBUG(errs() << "removing -use-soft-float\n"); B.addAttribute("use-soft-float", "false"); F.removeAttributes(AttributeList::FunctionIndex, B); if (F.hasFnAttribute("use-soft-float")) { - DEBUG(errs() << "still has -use-soft-float\n"); + LLVM_DEBUG(errs() << "still has -use-soft-float\n"); } F.addAttributes(AttributeList::FunctionIndex, B); } @@ -510,7 +510,7 @@ static void removeUseSoftFloat(Function &F) { bool Mips16HardFloat::runOnModule(Module &M) { auto &TM = static_cast<const MipsTargetMachine &>( getAnalysis<TargetPassConfig>().getTM<TargetMachine>()); - DEBUG(errs() << "Run on Module Mips16HardFloat\n"); + LLVM_DEBUG(errs() << "Run on Module Mips16HardFloat\n"); bool Modified = false; for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) { if (F->hasFnAttribute("nomips16") && diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp index ff95f3c7228..751afd5ed36 100644 --- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -127,8 +127,8 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, Offset = SPOffset + (int64_t)StackSize; Offset += MI.getOperand(OpNo + 1).getImm(); - - DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); + LLVM_DEBUG(errs() << "Offset : " << Offset << "\n" + << "<--------->\n"); if (!MI.isDebugValue() && !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) { diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 5ee816be373..9eb13a68e56 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -443,13 +443,15 @@ bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) { MF = &mf; MCP = mf.getConstantPool(); STI = &static_cast<const MipsSubtarget &>(mf.getSubtarget()); - DEBUG(dbgs() << "constant island machine function " << "\n"); + LLVM_DEBUG(dbgs() << "constant island machine function " + << "\n"); if (!STI->inMips16Mode() || !MipsSubtarget::useConstantIslands()) { return false; } TII = (const Mips16InstrInfo *)STI->getInstrInfo(); MFI = MF->getInfo<MipsFunctionInfo>(); - DEBUG(dbgs() << "constant island processing " << "\n"); + LLVM_DEBUG(dbgs() << "constant island processing " + << "\n"); // // will need to make predermination if there is any constants we need to // put in constant islands. TBD. @@ -480,7 +482,7 @@ bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) { // constant pool users. initializeFunctionInfo(CPEMIs); CPEMIs.clear(); - DEBUG(dumpBBs()); + LLVM_DEBUG(dumpBBs()); /// Remove dead constant pool entries. MadeChange |= removeUnusedCPEntries(); @@ -490,31 +492,31 @@ bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) { unsigned NoCPIters = 0, NoBRIters = 0; (void)NoBRIters; while (true) { - DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n'); + LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n'); bool CPChange = false; for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) CPChange |= handleConstantPoolUser(i); if (CPChange && ++NoCPIters > 30) report_fatal_error("Constant Island pass failed to converge!"); - DEBUG(dumpBBs()); + LLVM_DEBUG(dumpBBs()); // Clear NewWaterList now. If we split a block for branches, it should // appear as "new water" for the next iteration of constant pool placement. NewWaterList.clear(); - DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n'); + LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n'); bool BRChange = false; for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) BRChange |= fixupImmediateBr(ImmBranches[i]); if (BRChange && ++NoBRIters > 30) report_fatal_error("Branch Fix Up pass failed to converge!"); - DEBUG(dumpBBs()); + LLVM_DEBUG(dumpBBs()); if (!CPChange && !BRChange) break; MadeChange = true; } - DEBUG(dbgs() << '\n'; dumpBBs()); + LLVM_DEBUG(dbgs() << '\n'; dumpBBs()); BBInfo.clear(); WaterList.clear(); @@ -581,10 +583,10 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { // Add a new CPEntry, but no corresponding CPUser yet. CPEntries.emplace_back(1, CPEntry(CPEMI, i)); ++NumCPEs; - DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " - << Size << ", align = " << Align <<'\n'); + LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " + << Size << ", align = " << Align << '\n'); } - DEBUG(BB->dump()); + LLVM_DEBUG(BB->dump()); } /// BBHasFallthrough - Return true if the specified basic block can fallthrough @@ -987,7 +989,7 @@ bool MipsConstantIslands::isCPEntryInRange unsigned CPEOffset = getOffsetOf(CPEMI); if (DoDump) { - DEBUG({ + LLVM_DEBUG({ unsigned Block = MI->getParent()->getNumber(); const BasicBlockInfo &BBI = BBInfo[Block]; dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm() @@ -1060,7 +1062,7 @@ int MipsConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) // Check to see if the CPE is already in-range. if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk, true)) { - DEBUG(dbgs() << "In range\n"); + LLVM_DEBUG(dbgs() << "In range\n"); return 1; } @@ -1076,8 +1078,8 @@ int MipsConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) continue; if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(), U.NegOk)) { - DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" - << CPEs[i].CPI << "\n"); + LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" + << CPEs[i].CPI << "\n"); // Point the CPUser node to the replacement U.CPEMI = CPEs[i].CPEMI; // Change the CPI in the instruction operand to refer to the clone. @@ -1114,7 +1116,7 @@ int MipsConstantIslands::findLongFormInRangeCPEntry if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getLongFormMaxDisp(), U.NegOk, true)) { - DEBUG(dbgs() << "In range\n"); + LLVM_DEBUG(dbgs() << "In range\n"); UserMI->setDesc(TII->get(U.getLongFormOpcode())); U.setMaxDisp(U.getLongFormMaxDisp()); return 2; // instruction is longer length now @@ -1132,8 +1134,8 @@ int MipsConstantIslands::findLongFormInRangeCPEntry continue; if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getLongFormMaxDisp(), U.NegOk)) { - DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" - << CPEs[i].CPI << "\n"); + LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" + << CPEs[i].CPI << "\n"); // Point the CPUser node to the replacement U.CPEMI = CPEs[i].CPEMI; // Change the CPI in the instruction operand to refer to the clone. @@ -1198,8 +1200,8 @@ bool MipsConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset, // This is the least amount of required padding seen so far. BestGrowth = Growth; WaterIter = IP; - DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) - << " Growth=" << Growth << '\n'); + LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) + << " Growth=" << Growth << '\n'); // Keep looking unless it is perfect. if (BestGrowth == 0) @@ -1237,8 +1239,8 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta; if (isOffsetInRange(UserOffset, CPEOffset, U)) { - DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB) - << format(", expected CPE offset %#x\n", CPEOffset)); + LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB) + << format(", expected CPE offset %#x\n", CPEOffset)); NewMBB = &*++UserMBB->getIterator(); // Add an unconditional branch from UserMBB to fallthrough block. Record // it for branch lengthening; this new branch will not get out of range, @@ -1264,16 +1266,16 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, unsigned LogAlign = MF->getAlignment(); assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry"); unsigned BaseInsertOffset = UserOffset + U.getMaxDisp(); - DEBUG(dbgs() << format("Split in middle of big block before %#x", - BaseInsertOffset)); + LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x", + BaseInsertOffset)); // The 4 in the following is for the unconditional branch we'll be inserting // Alignment of the island is handled // inside isOffsetInRange. BaseInsertOffset -= 4; - DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset) - << " la=" << LogAlign << '\n'); + LLVM_DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset) + << " la=" << LogAlign << '\n'); // This could point off the end of the block if we've already got constant // pool entries following this block; only the last one is in the water list. @@ -1281,7 +1283,7 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, // long unconditional). if (BaseInsertOffset + 8 >= UserBBI.postOffset()) { BaseInsertOffset = UserBBI.postOffset() - 8; - DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset)); + LLVM_DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset)); } unsigned EndInsertOffset = BaseInsertOffset + 4 + CPEMI->getOperand(2).getImm(); @@ -1337,7 +1339,7 @@ bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) { MachineBasicBlock *NewMBB; water_iterator IP; if (findAvailableWater(U, UserOffset, IP)) { - DEBUG(dbgs() << "Found water in range\n"); + LLVM_DEBUG(dbgs() << "Found water in range\n"); MachineBasicBlock *WaterBB = *IP; // If the original WaterList entry was "new water" on this iteration, @@ -1356,7 +1358,7 @@ bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) { result = findLongFormInRangeCPEntry(U, UserOffset); if (result != 0) return true; } - DEBUG(dbgs() << "No water found\n"); + LLVM_DEBUG(dbgs() << "No water found\n"); createNewWater(CPUserIndex, UserOffset, NewMBB); // splitBlockBeforeInstr adds to WaterList, which is important when it is @@ -1415,8 +1417,9 @@ bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) { break; } - DEBUG(dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI - << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset)); + LLVM_DEBUG( + dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI + << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset)); return true; } @@ -1471,11 +1474,11 @@ bool MipsConstantIslands::isBBInRange unsigned BrOffset = getOffsetOf(MI) + PCAdj; unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; - DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) - << " from " << printMBBReference(*MI->getParent()) - << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) - << " to " << DestOffset << " offset " - << int(DestOffset - BrOffset) << "\t" << *MI); + LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) + << " from " << printMBBReference(*MI->getParent()) + << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) + << " to " << DestOffset << " offset " + << int(DestOffset - BrOffset) << "\t" << *MI); if (BrOffset <= DestOffset) { // Branch before the Dest. @@ -1540,7 +1543,7 @@ MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) { HasFarJump = true; ++NumUBrFixed; - DEBUG(dbgs() << " Changed B to long jump " << *MI); + LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI); return true; } @@ -1595,8 +1598,9 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { MachineBasicBlock *NewDest = BMI->getOperand(BMITargetOperand).getMBB(); if (isBBInRange(MI, NewDest, Br.MaxDisp)) { - DEBUG(dbgs() << " Invert Bcc condition and swap its destination with " - << *BMI); + LLVM_DEBUG( + dbgs() << " Invert Bcc condition and swap its destination with " + << *BMI); MI->setDesc(TII->get(OppositeBranchOpcode)); BMI->getOperand(BMITargetOperand).setMBB(DestBB); MI->getOperand(TargetOperand).setMBB(NewDest); @@ -1616,9 +1620,9 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { } MachineBasicBlock *NextBB = &*++MBB->getIterator(); - DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) - << " also invert condition and change dest. to " - << printMBBReference(*NextBB) << "\n"); + LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) + << " also invert condition and change dest. to " + << printMBBReference(*NextBB) << "\n"); // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. @@ -1654,19 +1658,19 @@ void MipsConstantIslands::prescanForConstants() { switch(I->getDesc().getOpcode()) { case Mips::LwConstant32: { PrescannedForConstants = true; - DEBUG(dbgs() << "constant island constant " << *I << "\n"); + LLVM_DEBUG(dbgs() << "constant island constant " << *I << "\n"); J = I->getNumOperands(); - DEBUG(dbgs() << "num operands " << J << "\n"); + LLVM_DEBUG(dbgs() << "num operands " << J << "\n"); MachineOperand& Literal = I->getOperand(1); if (Literal.isImm()) { int64_t V = Literal.getImm(); - DEBUG(dbgs() << "literal " << V << "\n"); + LLVM_DEBUG(dbgs() << "literal " << V << "\n"); Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext()); const Constant *C = ConstantInt::get(Int32Ty, V); unsigned index = MCP->getConstantPoolIndex(C, 4); I->getOperand(2).ChangeToImmediate(index); - DEBUG(dbgs() << "constant island constant " << *I << "\n"); + LLVM_DEBUG(dbgs() << "constant island constant " << *I << "\n"); I->setDesc(TII->get(Mips::LwRxPcTcp16)); I->RemoveOperand(1); I->RemoveOperand(1); diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 7685555a1e7..4b460551539 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -1001,11 +1001,12 @@ bool MipsFastISel::selectFPExt(const Instruction *I) { bool MipsFastISel::selectSelect(const Instruction *I) { assert(isa<SelectInst>(I) && "Expected a select instruction."); - DEBUG(dbgs() << "selectSelect\n"); + LLVM_DEBUG(dbgs() << "selectSelect\n"); MVT VT; if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) { - DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n"); + LLVM_DEBUG( + dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n"); return false; } @@ -1288,22 +1289,22 @@ bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, } bool MipsFastISel::fastLowerArguments() { - DEBUG(dbgs() << "fastLowerArguments\n"); + LLVM_DEBUG(dbgs() << "fastLowerArguments\n"); if (!FuncInfo.CanLowerReturn) { - DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n"); + LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n"); return false; } const Function *F = FuncInfo.Fn; if (F->isVarArg()) { - DEBUG(dbgs() << ".. gave up (varargs)\n"); + LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n"); return false; } CallingConv::ID CC = F->getCallingConv(); if (CC != CallingConv::C) { - DEBUG(dbgs() << ".. gave up (calling convention is not C)\n"); + LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n"); return false; } @@ -1329,21 +1330,21 @@ bool MipsFastISel::fastLowerArguments() { if (FormalArg.hasAttribute(Attribute::InReg) || FormalArg.hasAttribute(Attribute::StructRet) || FormalArg.hasAttribute(Attribute::ByVal)) { - DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n"); + LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n"); return false; } Type *ArgTy = FormalArg.getType(); if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) { - DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n"); + LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n"); return false; } EVT ArgVT = TLI.getValueType(DL, ArgTy); - DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": " - << ArgVT.getEVTString() << "\n"); + LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": " + << ArgVT.getEVTString() << "\n"); if (!ArgVT.isSimple()) { - DEBUG(dbgs() << ".. .. gave up (not a simple type)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n"); return false; } @@ -1355,16 +1356,16 @@ bool MipsFastISel::fastLowerArguments() { !FormalArg.hasAttribute(Attribute::ZExt)) { // It must be any extend, this shouldn't happen for clang-generated IR // so just fall back on SelectionDAG. - DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n"); return false; } if (NextGPR32 == GPR32ArgRegs.end()) { - DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n"); return false; } - DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n"); + LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n"); Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); // Allocating any GPR32 prohibits further use of floating point arguments. @@ -1375,16 +1376,16 @@ bool MipsFastISel::fastLowerArguments() { case MVT::i32: if (FormalArg.hasAttribute(Attribute::ZExt)) { // The O32 ABI does not permit a zero-extended i32. - DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n"); return false; } if (NextGPR32 == GPR32ArgRegs.end()) { - DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n"); return false; } - DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n"); + LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n"); Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); // Allocating any GPR32 prohibits further use of floating point arguments. @@ -1394,14 +1395,14 @@ bool MipsFastISel::fastLowerArguments() { case MVT::f32: if (UnsupportedFPMode) { - DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n"); return false; } if (NextFGR32 == FGR32ArgRegs.end()) { - DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n"); return false; } - DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n"); + LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n"); Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++); // Allocating an FGR32 also allocates the super-register AFGR64, and // ABI rules require us to skip the corresponding GPR32. @@ -1413,14 +1414,14 @@ bool MipsFastISel::fastLowerArguments() { case MVT::f64: if (UnsupportedFPMode) { - DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n"); return false; } if (NextAFGR64 == AFGR64ArgRegs.end()) { - DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n"); return false; } - DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n"); + LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n"); Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); // Allocating an FGR32 also allocates the super-register AFGR64, and // ABI rules require us to skip the corresponding GPR32 pair. @@ -1433,7 +1434,7 @@ bool MipsFastISel::fastLowerArguments() { break; default: - DEBUG(dbgs() << ".. .. gave up (unknown type)\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n"); return false; } } @@ -1648,7 +1649,7 @@ bool MipsFastISel::selectRet(const Instruction *I) { const Function &F = *I->getParent()->getParent(); const ReturnInst *Ret = cast<ReturnInst>(I); - DEBUG(dbgs() << "selectRet\n"); + LLVM_DEBUG(dbgs() << "selectRet\n"); if (!FuncInfo.CanLowerReturn) return false; @@ -1712,7 +1713,7 @@ bool MipsFastISel::selectRet(const Instruction *I) { // Do not handle FGR64 returns for now. if (RVVT == MVT::f64 && UnsupportedFPMode) { - DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n"); + LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n"); return false; } diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 8a56df2df6a..7e843512f6e 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -217,7 +217,7 @@ void MipsDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); Node->setNodeId(-1); return; } diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index 56c442a9ee2..a07940b5538 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -83,8 +83,8 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterClass *RC = &Mips::GPR32RegClass; if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } return true; diff --git a/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp index ceacaa49838..0be5abca03f 100644 --- a/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp @@ -42,7 +42,7 @@ namespace { } bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { - DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n"); + LLVM_DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n"); auto &TPC = getAnalysis<TargetPassConfig>(); auto &TM = TPC.getTM<MipsTargetMachine>(); TM.resetSubtarget(&MF); diff --git a/llvm/lib/Target/Mips/MipsOs16.cpp b/llvm/lib/Target/Mips/MipsOs16.cpp index 7ee45c28a7d..4edcb3132ad 100644 --- a/llvm/lib/Target/Mips/MipsOs16.cpp +++ b/llvm/lib/Target/Mips/MipsOs16.cpp @@ -96,7 +96,8 @@ static bool needsFP(Function &F) { ; } if (const CallInst *CI = dyn_cast<CallInst>(I)) { - DEBUG(dbgs() << "Working on call" << "\n"); + LLVM_DEBUG(dbgs() << "Working on call" + << "\n"); Function &F_ = *CI->getCalledFunction(); if (needsFPFromSig(F_)) return true; @@ -110,9 +111,10 @@ bool MipsOs16::runOnModule(Module &M) { bool usingMask = Mips32FunctionMask.length() > 0; bool doneUsingMask = false; // this will make it stop repeating - DEBUG(dbgs() << "Run on Module MipsOs16 \n" << Mips32FunctionMask << "\n"); + LLVM_DEBUG(dbgs() << "Run on Module MipsOs16 \n" + << Mips32FunctionMask << "\n"); if (usingMask) - DEBUG(dbgs() << "using mask \n" << Mips32FunctionMask << "\n"); + LLVM_DEBUG(dbgs() << "using mask \n" << Mips32FunctionMask << "\n"); unsigned int functionIndex = 0; bool modified = false; @@ -121,14 +123,14 @@ bool MipsOs16::runOnModule(Module &M) { if (F.isDeclaration()) continue; - DEBUG(dbgs() << "Working on " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "Working on " << F.getName() << "\n"); if (usingMask) { if (!doneUsingMask) { if (functionIndex == Mips32FunctionMask.length()) functionIndex = 0; switch (Mips32FunctionMask[functionIndex]) { case '1': - DEBUG(dbgs() << "mask forced mips32: " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "mask forced mips32: " << F.getName() << "\n"); F.addFnAttr("nomips16"); break; case '.': @@ -142,11 +144,11 @@ bool MipsOs16::runOnModule(Module &M) { } else { if (needsFP(F)) { - DEBUG(dbgs() << "os16 forced mips32: " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "os16 forced mips32: " << F.getName() << "\n"); F.addFnAttr("nomips16"); } else { - DEBUG(dbgs() << "os16 forced mips16: " << F.getName() << "\n"); + LLVM_DEBUG(dbgs() << "os16 forced mips16: " << F.getName() << "\n"); F.addFnAttr("mips16"); } } diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 0e0d82270c8..3c108c2ba9b 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -275,18 +275,20 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; - errs() << "<--------->\n" << MI); + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; + errs() << "<--------->\n" + << MI); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); uint64_t stackSize = MF.getFrameInfo().getStackSize(); int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); - DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" - << "spOffset : " << spOffset << "\n" - << "stackSize : " << stackSize << "\n" - << "alignment : " - << MF.getFrameInfo().getObjectAlignment(FrameIndex) << "\n"); + LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" + << "spOffset : " << spOffset << "\n" + << "stackSize : " << stackSize << "\n" + << "alignment : " + << MF.getFrameInfo().getObjectAlignment(FrameIndex) + << "\n"); eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); } diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 12916c0cbfd..a62ae07c12b 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1040,11 +1040,9 @@ MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { } if (Val.getNode()) { - DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; - N->printrWithDepth(dbgs(), &DAG); - dbgs() << "\n=> \n"; - Val.getNode()->printrWithDepth(dbgs(), &DAG); - dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; + N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n"; + Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n"); return Val; } diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp index 9b89d4077a7..c61b9db8084 100644 --- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -202,7 +202,8 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, Offset = SPOffset + (int64_t)StackSize; Offset += MI.getOperand(OpNo + 1).getImm(); - DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); + LLVM_DEBUG(errs() << "Offset : " << Offset << "\n" + << "<--------->\n"); if (!MI.isDebugValue()) { // Make sure Offset fits within the field available. diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 1cbffbf8b34..a4d159c411f 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -234,7 +234,8 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, } bool MipsSubtarget::useConstantIslands() { - DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); + LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands + << "\n"); return Mips16ConstantIslands; } diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 2b9ac2cd900..d360a9ebe36 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -207,7 +207,7 @@ MipsTargetMachine::getSubtargetImpl(const Function &F) const { } void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { - DEBUG(dbgs() << "resetSubtarget\n"); + LLVM_DEBUG(dbgs() << "resetSubtarget\n"); Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(MF->getFunction())); MF->setSubtarget(Subtarget); @@ -275,12 +275,12 @@ void MipsPassConfig::addPreRegAlloc() { TargetTransformInfo MipsTargetMachine::getTargetTransformInfo(const Function &F) { if (Subtarget->allowMixed16_32()) { - DEBUG(errs() << "No Target Transform Info Pass Added\n"); + LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); // FIXME: This is no longer necessary as the TTI returned is per-function. return TargetTransformInfo(F.getParent()->getDataLayout()); } - DEBUG(errs() << "Target Transform Info Pass Added\n"); + LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); return TargetTransformInfo(BasicTTIImpl(this, F)); } diff --git a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp index 1402033b9e6..5bb4fc3edd0 100644 --- a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp @@ -97,10 +97,12 @@ AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx, Offset = (Offset + Align - 1) / Align * Align; if (StackGrowsDown) { - DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset + << "]\n"); MFI.setObjectOffset(FrameIdx, -Offset); // Set the computed offset } else { - DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << Offset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << Offset + << "]\n"); MFI.setObjectOffset(FrameIdx, Offset); Offset += MFI.getObjectSize(FrameIdx); } @@ -163,14 +165,14 @@ NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) { // Adjust to alignment boundary. Offset = (Offset + Align - 1) / Align * Align; - DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n"); + LLVM_DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n"); // Resolve offsets for objects in the local block. for (unsigned i = 0, e = MFI.getLocalFrameObjectCount(); i != e; ++i) { std::pair<int, int64_t> Entry = MFI.getLocalFrameObjectMap(i); int64_t FIOffset = (StackGrowsDown ? -Offset : Offset) + Entry.second; - DEBUG(dbgs() << "alloc FI(" << Entry.first << ") at SP[" << - FIOffset << "]\n"); + LLVM_DEBUG(dbgs() << "alloc FI(" << Entry.first << ") at SP[" << FIOffset + << "]\n"); MFI.setObjectOffset(Entry.first, FIOffset); } // Allocate the local block diff --git a/llvm/lib/Target/NVPTX/NVVMReflect.cpp b/llvm/lib/Target/NVPTX/NVVMReflect.cpp index 152b665d0fd..60971b48adf 100644 --- a/llvm/lib/Target/NVPTX/NVVMReflect.cpp +++ b/llvm/lib/Target/NVPTX/NVVMReflect.cpp @@ -153,7 +153,7 @@ bool NVVMReflect::runOnFunction(Function &F) { StringRef ReflectArg = cast<ConstantDataSequential>(Operand)->getAsString(); ReflectArg = ReflectArg.substr(0, ReflectArg.size() - 1); - DEBUG(dbgs() << "Arg of _reflect : " << ReflectArg << "\n"); + LLVM_DEBUG(dbgs() << "Arg of _reflect : " << ReflectArg << "\n"); int ReflectVal = 0; // The default value is 0 if (ReflectArg == "__CUDA_FTZ") { diff --git a/llvm/lib/Target/Nios2/Nios2ISelDAGToDAG.cpp b/llvm/lib/Target/Nios2/Nios2ISelDAGToDAG.cpp index acc5cee055c..5f967946611 100644 --- a/llvm/lib/Target/Nios2/Nios2ISelDAGToDAG.cpp +++ b/llvm/lib/Target/Nios2/Nios2ISelDAGToDAG.cpp @@ -61,7 +61,7 @@ void Nios2DAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); Node->setNodeId(-1); return; } diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index e8490850369..4f6ebbeb4ca 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -771,11 +771,11 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { else if (MO.isGlobal()) { const GlobalValue *GV = MO.getGlobal(); MOSymbol = getSymbol(GV); - DEBUG( - unsigned char GVFlags = Subtarget->classifyGlobalReference(GV); - assert((GVFlags & PPCII::MO_NLP_FLAG) && - "LDtocL used on symbol that could be accessed directly is " - "invalid. Must match ADDIStocHA.")); + LLVM_DEBUG( + unsigned char GVFlags = Subtarget->classifyGlobalReference(GV); + assert((GVFlags & PPCII::MO_NLP_FLAG) && + "LDtocL used on symbol that could be accessed directly is " + "invalid. Must match ADDIStocHA.")); MOSymbol = lookUpOrCreateTOCEntry(MOSymbol); } @@ -800,11 +800,9 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (MO.isGlobal()) { const GlobalValue *GV = MO.getGlobal(); - DEBUG( - unsigned char GVFlags = Subtarget->classifyGlobalReference(GV); - assert ( - !(GVFlags & PPCII::MO_NLP_FLAG) && - "Interposable definitions must use indirect access.")); + LLVM_DEBUG(unsigned char GVFlags = Subtarget->classifyGlobalReference(GV); + assert(!(GVFlags & PPCII::MO_NLP_FLAG) && + "Interposable definitions must use indirect access.")); MOSymbol = getSymbol(GV); } else if (MO.isCPI()) { MOSymbol = GetCPISymbol(MO.getIndex()); diff --git a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp index 347f66d1709..bbb977f090c 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp @@ -236,18 +236,18 @@ void PPCBranchCoalescing::initialize(MachineFunction &MF) { ///\return true if and only if the branch can be coalesced, false otherwise /// bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) { - DEBUG(dbgs() << "Determine if branch block " << Cand.BranchBlock->getNumber() - << " can be coalesced:"); + LLVM_DEBUG(dbgs() << "Determine if branch block " + << Cand.BranchBlock->getNumber() << " can be coalesced:"); MachineBasicBlock *FalseMBB = nullptr; if (TII->analyzeBranch(*Cand.BranchBlock, Cand.BranchTargetBlock, FalseMBB, Cand.Cond)) { - DEBUG(dbgs() << "TII unable to Analyze Branch - skip\n"); + LLVM_DEBUG(dbgs() << "TII unable to Analyze Branch - skip\n"); return false; } for (auto &I : Cand.BranchBlock->terminators()) { - DEBUG(dbgs() << "Looking at terminator : " << I << "\n"); + LLVM_DEBUG(dbgs() << "Looking at terminator : " << I << "\n"); if (!I.isBranch()) continue; @@ -265,14 +265,14 @@ bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) { // must then be extended to prove that none of the implicit operands are // changed in the blocks that are combined during coalescing. if (I.getNumOperands() != I.getNumExplicitOperands()) { - DEBUG(dbgs() << "Terminator contains implicit operands - skip : " << I - << "\n"); + LLVM_DEBUG(dbgs() << "Terminator contains implicit operands - skip : " + << I << "\n"); return false; } } if (Cand.BranchBlock->isEHPad() || Cand.BranchBlock->hasEHPadSuccessor()) { - DEBUG(dbgs() << "EH Pad - skip\n"); + LLVM_DEBUG(dbgs() << "EH Pad - skip\n"); return false; } @@ -280,13 +280,13 @@ bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) { // FalseMBB is null, and BranchTargetBlock is a successor to BranchBlock) if (!Cand.BranchTargetBlock || FalseMBB || !Cand.BranchBlock->isSuccessor(Cand.BranchTargetBlock)) { - DEBUG(dbgs() << "Does not form a triangle - skip\n"); + LLVM_DEBUG(dbgs() << "Does not form a triangle - skip\n"); return false; } // Ensure there are only two successors if (Cand.BranchBlock->succ_size() != 2) { - DEBUG(dbgs() << "Does not have 2 successors - skip\n"); + LLVM_DEBUG(dbgs() << "Does not have 2 successors - skip\n"); return false; } @@ -305,18 +305,19 @@ bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) { assert(Succ && "Expecting a valid fall-through block\n"); if (!Succ->empty()) { - DEBUG(dbgs() << "Fall-through block contains code -- skip\n"); - return false; + LLVM_DEBUG(dbgs() << "Fall-through block contains code -- skip\n"); + return false; } if (!Succ->isSuccessor(Cand.BranchTargetBlock)) { - DEBUG(dbgs() - << "Successor of fall through block is not branch taken block\n"); - return false; + LLVM_DEBUG( + dbgs() + << "Successor of fall through block is not branch taken block\n"); + return false; } Cand.FallThroughBlock = Succ; - DEBUG(dbgs() << "Valid Candidate\n"); + LLVM_DEBUG(dbgs() << "Valid Candidate\n"); return true; } @@ -331,7 +332,7 @@ bool PPCBranchCoalescing::identicalOperands( ArrayRef<MachineOperand> OpList1, ArrayRef<MachineOperand> OpList2) const { if (OpList1.size() != OpList2.size()) { - DEBUG(dbgs() << "Operand list is different size\n"); + LLVM_DEBUG(dbgs() << "Operand list is different size\n"); return false; } @@ -339,8 +340,8 @@ bool PPCBranchCoalescing::identicalOperands( const MachineOperand &Op1 = OpList1[i]; const MachineOperand &Op2 = OpList2[i]; - DEBUG(dbgs() << "Op1: " << Op1 << "\n" - << "Op2: " << Op2 << "\n"); + LLVM_DEBUG(dbgs() << "Op1: " << Op1 << "\n" + << "Op2: " << Op2 << "\n"); if (Op1.isIdenticalTo(Op2)) { // filter out instructions with physical-register uses @@ -348,10 +349,10 @@ bool PPCBranchCoalescing::identicalOperands( // If the physical register is constant then we can assume the value // has not changed between uses. && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) { - DEBUG(dbgs() << "The operands are not provably identical.\n"); + LLVM_DEBUG(dbgs() << "The operands are not provably identical.\n"); return false; } - DEBUG(dbgs() << "Op1 and Op2 are identical!\n"); + LLVM_DEBUG(dbgs() << "Op1 and Op2 are identical!\n"); continue; } @@ -364,14 +365,14 @@ bool PPCBranchCoalescing::identicalOperands( MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg()); MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); if (TII->produceSameValue(*Op1Def, *Op2Def, MRI)) { - DEBUG(dbgs() << "Op1Def: " << *Op1Def << " and " << *Op2Def - << " produce the same value!\n"); + LLVM_DEBUG(dbgs() << "Op1Def: " << *Op1Def << " and " << *Op2Def + << " produce the same value!\n"); } else { - DEBUG(dbgs() << "Operands produce different values\n"); + LLVM_DEBUG(dbgs() << "Operands produce different values\n"); return false; } } else { - DEBUG(dbgs() << "The operands are not provably identical.\n"); + LLVM_DEBUG(dbgs() << "The operands are not provably identical.\n"); return false; } } @@ -395,7 +396,7 @@ void PPCBranchCoalescing::moveAndUpdatePHIs(MachineBasicBlock *SourceMBB, MachineBasicBlock::iterator ME = SourceMBB->getFirstNonPHI(); if (MI == ME) { - DEBUG(dbgs() << "SourceMBB contains no PHI instructions.\n"); + LLVM_DEBUG(dbgs() << "SourceMBB contains no PHI instructions.\n"); return; } @@ -425,19 +426,19 @@ bool PPCBranchCoalescing::canMoveToBeginning(const MachineInstr &MI, const MachineBasicBlock &TargetMBB ) const { - DEBUG(dbgs() << "Checking if " << MI << " can move to beginning of " - << TargetMBB.getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Checking if " << MI << " can move to beginning of " + << TargetMBB.getNumber() << "\n"); for (auto &Def : MI.defs()) { // Looking at Def for (auto &Use : MRI->use_instructions(Def.getReg())) { if (Use.isPHI() && Use.getParent() == &TargetMBB) { - DEBUG(dbgs() << " *** used in a PHI -- cannot move ***\n"); - return false; + LLVM_DEBUG(dbgs() << " *** used in a PHI -- cannot move ***\n"); + return false; } } } - DEBUG(dbgs() << " Safe to move to the beginning.\n"); + LLVM_DEBUG(dbgs() << " Safe to move to the beginning.\n"); return true; } @@ -456,22 +457,23 @@ bool PPCBranchCoalescing::canMoveToEnd(const MachineInstr &MI, const MachineBasicBlock &TargetMBB ) const { - DEBUG(dbgs() << "Checking if " << MI << " can move to end of " - << TargetMBB.getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Checking if " << MI << " can move to end of " + << TargetMBB.getNumber() << "\n"); for (auto &Use : MI.uses()) { if (Use.isReg() && TargetRegisterInfo::isVirtualRegister(Use.getReg())) { MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) { - DEBUG(dbgs() << " *** Cannot move this instruction ***\n"); + LLVM_DEBUG(dbgs() << " *** Cannot move this instruction ***\n"); return false; } else { - DEBUG(dbgs() << " *** def is in another block -- safe to move!\n"); + LLVM_DEBUG( + dbgs() << " *** def is in another block -- safe to move!\n"); } } } - DEBUG(dbgs() << " Safe to move to the end.\n"); + LLVM_DEBUG(dbgs() << " Safe to move to the end.\n"); return true; } @@ -541,15 +543,17 @@ bool PPCBranchCoalescing::canMerge(CoalescingCandidateInfo &SourceRegion, for (auto &Def : I->defs()) for (auto &Use : MRI->use_instructions(Def.getReg())) { if (Use.isPHI() && Use.getParent() == SourceRegion.BranchTargetBlock) { - DEBUG(dbgs() << "PHI " << *I << " defines register used in another " - "PHI within branch target block -- can't merge\n"); + LLVM_DEBUG(dbgs() + << "PHI " << *I + << " defines register used in another " + "PHI within branch target block -- can't merge\n"); NumPHINotMoved++; return false; } if (Use.getParent() == SourceRegion.BranchBlock) { - DEBUG(dbgs() << "PHI " << *I - << " defines register used in this " - "block -- all must move down\n"); + LLVM_DEBUG(dbgs() << "PHI " << *I + << " defines register used in this " + "block -- all must move down\n"); SourceRegion.MustMoveDown = true; } } @@ -562,13 +566,13 @@ bool PPCBranchCoalescing::canMerge(CoalescingCandidateInfo &SourceRegion, E = SourceRegion.BranchBlock->end(); I != E; ++I) { if (!canMoveToBeginning(*I, *SourceRegion.BranchTargetBlock)) { - DEBUG(dbgs() << "Instruction " << *I - << " cannot move down - must move up!\n"); + LLVM_DEBUG(dbgs() << "Instruction " << *I + << " cannot move down - must move up!\n"); SourceRegion.MustMoveUp = true; } if (!canMoveToEnd(*I, *TargetRegion.BranchBlock)) { - DEBUG(dbgs() << "Instruction " << *I - << " cannot move up - must move down!\n"); + LLVM_DEBUG(dbgs() << "Instruction " << *I + << " cannot move up - must move down!\n"); SourceRegion.MustMoveDown = true; } } @@ -719,10 +723,10 @@ bool PPCBranchCoalescing::runOnMachineFunction(MachineFunction &MF) { bool didSomething = false; - DEBUG(dbgs() << "******** Branch Coalescing ********\n"); + LLVM_DEBUG(dbgs() << "******** Branch Coalescing ********\n"); initialize(MF); - DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n"); CoalescingCandidateInfo Cand1, Cand2; // Walk over blocks and find candidates to merge @@ -752,24 +756,27 @@ bool PPCBranchCoalescing::runOnMachineFunction(MachineFunction &MF) { "Branch-taken block should post-dominate first candidate"); if (!identicalOperands(Cand1.Cond, Cand2.Cond)) { - DEBUG(dbgs() << "Blocks " << Cand1.BranchBlock->getNumber() << " and " - << Cand2.BranchBlock->getNumber() - << " have different branches\n"); + LLVM_DEBUG(dbgs() << "Blocks " << Cand1.BranchBlock->getNumber() + << " and " << Cand2.BranchBlock->getNumber() + << " have different branches\n"); break; } if (!canMerge(Cand2, Cand1)) { - DEBUG(dbgs() << "Cannot merge blocks " << Cand1.BranchBlock->getNumber() - << " and " << Cand2.BranchBlock->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Cannot merge blocks " + << Cand1.BranchBlock->getNumber() << " and " + << Cand2.BranchBlock->getNumber() << "\n"); NumBlocksNotCoalesced++; continue; } - DEBUG(dbgs() << "Merging blocks " << Cand1.BranchBlock->getNumber() - << " and " << Cand1.BranchTargetBlock->getNumber() << "\n"); + LLVM_DEBUG(dbgs() << "Merging blocks " << Cand1.BranchBlock->getNumber() + << " and " << Cand1.BranchTargetBlock->getNumber() + << "\n"); MergedCandidates = mergeCandidates(Cand2, Cand1); if (MergedCandidates) didSomething = true; - DEBUG(dbgs() << "Function after merging: "; MF.dump(); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Function after merging: "; MF.dump(); + dbgs() << "\n"); } while (MergedCandidates); } @@ -779,6 +786,6 @@ bool PPCBranchCoalescing::runOnMachineFunction(MachineFunction &MF) { MF.verify(nullptr, "Error in code produced by branch coalescing"); #endif // NDEBUG - DEBUG(dbgs() << "Finished Branch Coalescing\n"); + LLVM_DEBUG(dbgs() << "Finished Branch Coalescing\n"); return didSomething; } diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp index cd794247a7e..c96df538a6a 100644 --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -507,7 +507,7 @@ bool PPCCTRLoops::convertToCTRLoop(Loop *L) { // Process nested loops first. for (Loop::iterator I = L->begin(), E = L->end(); I != E; ++I) { MadeChange |= convertToCTRLoop(*I); - DEBUG(dbgs() << "Nested loop converted\n"); + LLVM_DEBUG(dbgs() << "Nested loop converted\n"); } // If a nested loop has been converted, then we can't convert this loop. @@ -567,8 +567,8 @@ bool PPCCTRLoops::convertToCTRLoop(Loop *L) { for (SmallVectorImpl<BasicBlock *>::iterator I = ExitingBlocks.begin(), IE = ExitingBlocks.end(); I != IE; ++I) { const SCEV *EC = SE->getExitCount(L, *I); - DEBUG(dbgs() << "Exit Count for " << *L << " from block " << - (*I)->getName() << ": " << *EC << "\n"); + LLVM_DEBUG(dbgs() << "Exit Count for " << *L << " from block " + << (*I)->getName() << ": " << *EC << "\n"); if (isa<SCEVCouldNotCompute>(EC)) continue; if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) { @@ -642,7 +642,8 @@ bool PPCCTRLoops::convertToCTRLoop(Loop *L) { if (!Preheader) return MadeChange; - DEBUG(dbgs() << "Preheader for exit count: " << Preheader->getName() << "\n"); + LLVM_DEBUG(dbgs() << "Preheader for exit count: " << Preheader->getName() + << "\n"); // Insert the count into the preheader and replace the condition used by the // selected branch. @@ -730,11 +731,12 @@ check_block: } if (I != BI && clobbersCTR(*I)) { - DEBUG(dbgs() << printMBBReference(*MBB) << " (" << MBB->getFullName() - << ") instruction " << *I << " clobbers CTR, invalidating " - << printMBBReference(*BI->getParent()) << " (" - << BI->getParent()->getFullName() << ") instruction " << *BI - << "\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " (" << MBB->getFullName() + << ") instruction " << *I + << " clobbers CTR, invalidating " + << printMBBReference(*BI->getParent()) << " (" + << BI->getParent()->getFullName() << ") instruction " + << *BI << "\n"); return false; } @@ -748,10 +750,10 @@ check_block: if (CheckPreds) { queue_preds: if (MachineFunction::iterator(MBB) == MBB->getParent()->begin()) { - DEBUG(dbgs() << "Unable to find a MTCTR instruction for " - << printMBBReference(*BI->getParent()) << " (" - << BI->getParent()->getFullName() << ") instruction " << *BI - << "\n"); + LLVM_DEBUG(dbgs() << "Unable to find a MTCTR instruction for " + << printMBBReference(*BI->getParent()) << " (" + << BI->getParent()->getFullName() << ") instruction " + << *BI << "\n"); return false; } diff --git a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp index b00e98b63e3..6151bee6133 100644 --- a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp +++ b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp @@ -126,11 +126,11 @@ public: #endif bool runOnMachineFunction(MachineFunction &MF) override { - DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n"); initialize(MF); if (!collectISELInstructions()) { - DEBUG(dbgs() << "No ISEL instructions in this function\n"); + LLVM_DEBUG(dbgs() << "No ISEL instructions in this function\n"); return false; } @@ -170,9 +170,10 @@ bool PPCExpandISEL::collectISELInstructions() { #ifndef NDEBUG void PPCExpandISEL::DumpISELInstructions() const { for (const auto &I : ISELInstructions) { - DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first)) << ":\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first)) + << ":\n"); for (const auto &VI : I.second) - DEBUG(dbgs() << " "; VI->print(dbgs())); + LLVM_DEBUG(dbgs() << " "; VI->print(dbgs())); } } #endif @@ -192,9 +193,10 @@ void PPCExpandISEL::expandAndMergeISELs() { bool ExpandISELEnabled = isExpandISELEnabled(*MF); for (auto &BlockList : ISELInstructions) { - DEBUG(dbgs() << "Expanding ISEL instructions in " - << printMBBReference(*MF->getBlockNumbered(BlockList.first)) - << "\n"); + LLVM_DEBUG( + dbgs() << "Expanding ISEL instructions in " + << printMBBReference(*MF->getBlockNumbered(BlockList.first)) + << "\n"); BlockISELList &CurrentISELList = BlockList.second; auto I = CurrentISELList.begin(); auto E = CurrentISELList.end(); @@ -210,7 +212,8 @@ void PPCExpandISEL::expandAndMergeISELs() { // as it would be ISEL %R0, %ZERO, %R0, %CRN. if (useSameRegister(Dest, TrueValue) && useSameRegister(Dest, FalseValue)) { - DEBUG(dbgs() << "Remove redudant ISEL instruction: " << **I << "\n"); + LLVM_DEBUG(dbgs() << "Remove redudant ISEL instruction: " << **I + << "\n"); // FIXME: if the CR field used has no other uses, we could eliminate the // instruction that defines it. This would have to be done manually // since this pass runs too late to run DCE after it. @@ -223,8 +226,9 @@ void PPCExpandISEL::expandAndMergeISELs() { // condition as it would be ISEL %RX, %ZERO, %R0, %CRN, which makes it // safe to fold ISEL to MR(OR) instead of ADDI. MachineBasicBlock *MBB = (*I)->getParent(); - DEBUG(dbgs() << "Fold the ISEL instruction to an unconditonal copy:\n"); - DEBUG(dbgs() << "ISEL: " << **I << "\n"); + LLVM_DEBUG( + dbgs() << "Fold the ISEL instruction to an unconditonal copy:\n"); + LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n"); NumFolded++; // Note: we're using both the TrueValue and FalseValue operands so as // not to lose the kill flag if it is set on either of them. @@ -235,8 +239,8 @@ void PPCExpandISEL::expandAndMergeISELs() { (*I)->eraseFromParent(); I++; } else if (ExpandISELEnabled) { // Normal cases expansion enabled - DEBUG(dbgs() << "Expand ISEL instructions:\n"); - DEBUG(dbgs() << "ISEL: " << **I << "\n"); + LLVM_DEBUG(dbgs() << "Expand ISEL instructions:\n"); + LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n"); BlockISELList SubISELList; SubISELList.push_back(*I++); // Collect the ISELs that can be merged together. @@ -244,7 +248,7 @@ void PPCExpandISEL::expandAndMergeISELs() { // may be redundant or foldable to a register copy. So we still keep // the handleSpecialCases() downstream to handle them. while (I != E && canMerge(SubISELList.back(), *I)) { - DEBUG(dbgs() << "ISEL: " << **I << "\n"); + LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n"); SubISELList.push_back(*I++); } @@ -264,7 +268,7 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL, auto MI = BIL.begin(); while (MI != BIL.end()) { assert(isISEL(**MI) && "Expecting an ISEL instruction"); - DEBUG(dbgs() << "ISEL: " << **MI << "\n"); + LLVM_DEBUG(dbgs() << "ISEL: " << **MI << "\n"); MachineOperand &Dest = (*MI)->getOperand(0); MachineOperand &TrueValue = (*MI)->getOperand(1); @@ -281,7 +285,7 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL, // Special case 1, all registers used by ISEL are the same one. if (!IsADDIInstRequired && !IsORIInstRequired) { - DEBUG(dbgs() << "Remove redudant ISEL instruction."); + LLVM_DEBUG(dbgs() << "Remove redudant ISEL instruction."); // FIXME: if the CR field used has no other uses, we could eliminate the // instruction that defines it. This would have to be done manually // since this pass runs too late to run DCE after it. @@ -300,7 +304,8 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL, // be zero. In this case, the useSameRegister method will return false, // thereby preventing this ISEL from being folded. if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) { - DEBUG(dbgs() << "Fold the ISEL instruction to an unconditonal copy."); + LLVM_DEBUG( + dbgs() << "Fold the ISEL instruction to an unconditonal copy."); NumFolded++; // Note: we're using both the TrueValue and FalseValue operands so as // not to lose the kill flag if it is set on either of them. @@ -439,11 +444,10 @@ void PPCExpandISEL::populateBlocks(BlockISELList &BIL) { // condition is false MachineOperand &ConditionRegister = MI->getOperand(3); // Condition - DEBUG(dbgs() << "Dest: " << Dest << "\n"); - DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n"); - DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n"); - DEBUG(dbgs() << "ConditionRegister: " << ConditionRegister << "\n"); - + LLVM_DEBUG(dbgs() << "Dest: " << Dest << "\n"); + LLVM_DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n"); + LLVM_DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n"); + LLVM_DEBUG(dbgs() << "ConditionRegister: " << ConditionRegister << "\n"); // If the Dest Register and True Value Register are not the same one, we // need the True Block. diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 4c718f8883e..55122046690 100644 --- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -180,9 +180,9 @@ void PPCDispatchGroupSBHazardRecognizer::EmitInstruction(SUnit *SU) { CurGroup.clear(); CurSlots = CurBranches = 0; } else { - DEBUG(dbgs() << "**** Adding to dispatch group: SU(" << - SU->NodeNum << "): "); - DEBUG(DAG->dumpNode(SU)); + LLVM_DEBUG(dbgs() << "**** Adding to dispatch group: SU(" << SU->NodeNum + << "): "); + LLVM_DEBUG(DAG->dumpNode(SU)); unsigned NSlots; bool MustBeFirst = mustComeFirst(MCID, NSlots); @@ -268,7 +268,7 @@ PPCHazardRecognizer970::PPCHazardRecognizer970(const ScheduleDAG &DAG) } void PPCHazardRecognizer970::EndDispatchGroup() { - DEBUG(errs() << "=== Start of dispatch group\n"); + LLVM_DEBUG(errs() << "=== Start of dispatch group\n"); NumIssued = 0; // Structural hazard info. diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index b4818731cfd..518defef373 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -518,10 +518,10 @@ static unsigned getBranchHint(unsigned PCC, FunctionLoweringInfo *FuncInfo, if (std::max(TProb, FProb) / Threshold < std::min(TProb, FProb)) return PPC::BR_NO_HINT; - DEBUG(dbgs() << "Use branch hint for '" << FuncInfo->Fn->getName() << "::" - << BB->getName() << "'\n" - << " -> " << TBB->getName() << ": " << TProb << "\n" - << " -> " << FBB->getName() << ": " << FProb << "\n"); + LLVM_DEBUG(dbgs() << "Use branch hint for '" << FuncInfo->Fn->getName() + << "::" << BB->getName() << "'\n" + << " -> " << TBB->getName() << ": " << TProb << "\n" + << " -> " << FBB->getName() << ": " << FProb << "\n"); const BasicBlockSDNode *BBDN = cast<BasicBlockSDNode>(DestMBB); @@ -1131,8 +1131,8 @@ class BitPermutationSelector { BitGroup(SDValue V, unsigned R, unsigned S, unsigned E) : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false), Repl32Coalesced(false) { - DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R << - " [" << S << ", " << E << "]\n"); + LLVM_DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R + << " [" << S << ", " << E << "]\n"); } }; @@ -1366,7 +1366,7 @@ class BitPermutationSelector { BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 && BitGroups[0].V == BitGroups[BitGroups.size()-1].V && BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) { - DEBUG(dbgs() << "\tcombining final bit group with initial one\n"); + LLVM_DEBUG(dbgs() << "\tcombining final bit group with initial one\n"); BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx; BitGroups.erase(BitGroups.begin()); } @@ -1453,9 +1453,9 @@ class BitPermutationSelector { BG.Repl32 = true; - DEBUG(dbgs() << "\t32-bit replicated bit group for " << - BG.V.getNode() << " RLAmt = " << BG.RLAmt << - " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n"); + LLVM_DEBUG(dbgs() << "\t32-bit replicated bit group for " + << BG.V.getNode() << " RLAmt = " << BG.RLAmt << " [" + << BG.StartIdx << ", " << BG.EndIdx << "]\n"); } } } @@ -1469,11 +1469,11 @@ class BitPermutationSelector { if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt && I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) { - DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " << - I->V.getNode() << " RLAmt = " << I->RLAmt << - " [" << I->StartIdx << ", " << I->EndIdx << - "] with group with range [" << - IP->StartIdx << ", " << IP->EndIdx << "]\n"); + LLVM_DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " + << I->V.getNode() << " RLAmt = " << I->RLAmt << " [" + << I->StartIdx << ", " << I->EndIdx + << "] with group with range [" << IP->StartIdx << ", " + << IP->EndIdx << "]\n"); IP->EndIdx = I->EndIdx; IP->Repl32CR = IP->Repl32CR || I->Repl32CR; @@ -1497,12 +1497,12 @@ class BitPermutationSelector { IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP && IsAllLow32(*I)) { - DEBUG(dbgs() << "\tcombining bit group for " << - I->V.getNode() << " RLAmt = " << I->RLAmt << - " [" << I->StartIdx << ", " << I->EndIdx << - "] with 32-bit replicated groups with ranges [" << - IP->StartIdx << ", " << IP->EndIdx << "] and [" << - IN->StartIdx << ", " << IN->EndIdx << "]\n"); + LLVM_DEBUG(dbgs() << "\tcombining bit group for " << I->V.getNode() + << " RLAmt = " << I->RLAmt << " [" << I->StartIdx + << ", " << I->EndIdx + << "] with 32-bit replicated groups with ranges [" + << IP->StartIdx << ", " << IP->EndIdx << "] and [" + << IN->StartIdx << ", " << IN->EndIdx << "]\n"); if (IP == IN) { // There is only one other group; change it to cover the whole @@ -1611,15 +1611,15 @@ class BitPermutationSelector { (unsigned) (ANDIMask != 0 && ANDISMask != 0) + (unsigned) (bool) Res; - DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() << - " RL: " << VRI.RLAmt << ":" << - "\n\t\t\tisel using masking: " << NumAndInsts << - " using rotates: " << VRI.NumGroups << "\n"); + LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() + << " RL: " << VRI.RLAmt << ":" + << "\n\t\t\tisel using masking: " << NumAndInsts + << " using rotates: " << VRI.NumGroups << "\n"); if (NumAndInsts >= VRI.NumGroups) continue; - DEBUG(dbgs() << "\t\t\t\tusing masking\n"); + LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n"); if (InstCnt) *InstCnt += NumAndInsts; @@ -1967,10 +1967,10 @@ class BitPermutationSelector { FirstBG = false; } - DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() << - " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") << - "\n\t\t\tisel using masking: " << NumAndInsts << - " using rotates: " << NumRLInsts << "\n"); + LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() + << " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") + << "\n\t\t\tisel using masking: " << NumAndInsts + << " using rotates: " << NumRLInsts << "\n"); // When we'd use andi/andis, we bias toward using the rotates (andi only // has a record form, and is cracked on POWER cores). However, when using @@ -1984,7 +1984,7 @@ class BitPermutationSelector { if ((Use32BitInsts || MoreBG) && NumAndInsts == NumRLInsts) continue; - DEBUG(dbgs() << "\t\t\t\tusing masking\n"); + LLVM_DEBUG(dbgs() << "\t\t\t\tusing masking\n"); if (InstCnt) *InstCnt += NumAndInsts; @@ -2235,9 +2235,9 @@ public: return nullptr; Bits = std::move(*Result.second); - DEBUG(dbgs() << "Considering bit-permutation-based instruction" - " selection for: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "Considering bit-permutation-based instruction" + " selection for: "); + LLVM_DEBUG(N->dump(CurDAG)); // Fill it RLAmt and set HasZeros. computeRotationAmounts(); @@ -2254,21 +2254,21 @@ public: // masking, we only insert the non-zero parts of the result at every step. unsigned InstCnt, InstCntLateMask; - DEBUG(dbgs() << "\tEarly masking:\n"); + LLVM_DEBUG(dbgs() << "\tEarly masking:\n"); SDNode *RN = Select(N, false, &InstCnt); - DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n"); + LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n"); - DEBUG(dbgs() << "\tLate masking:\n"); + LLVM_DEBUG(dbgs() << "\tLate masking:\n"); SDNode *RNLM = Select(N, true, &InstCntLateMask); - DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask << - " instructions\n"); + LLVM_DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask + << " instructions\n"); if (InstCnt <= InstCntLateMask) { - DEBUG(dbgs() << "\tUsing early-masking for isel\n"); + LLVM_DEBUG(dbgs() << "\tUsing early-masking for isel\n"); return RN; } - DEBUG(dbgs() << "\tUsing late-masking for isel\n"); + LLVM_DEBUG(dbgs() << "\tUsing late-masking for isel\n"); return RNLM; } }; @@ -5190,11 +5190,11 @@ void PPCDAGToDAGISel::PreprocessISelDAG() { foldBoolExts(Res, N); if (Res) { - DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: "); - DEBUG(N->dump(CurDAG)); - DEBUG(dbgs() << "\nNew: "); - DEBUG(Res.getNode()->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nNew: "); + LLVM_DEBUG(Res.getNode()->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res); MadeChange = true; @@ -5271,13 +5271,13 @@ void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) { User->getOperand(2), User->getOperand(1)); - DEBUG(dbgs() << "CR Peephole replacing:\nOld: "); - DEBUG(User->dump(CurDAG)); - DEBUG(dbgs() << "\nNew: "); - DEBUG(ResNode->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: "); + LLVM_DEBUG(User->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nNew: "); + LLVM_DEBUG(ResNode->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); - ReplaceUses(User, ResNode); + ReplaceUses(User, ResNode); } } @@ -5685,11 +5685,11 @@ void PPCDAGToDAGISel::PeepholeCROps() { SwapAllSelectUsers(MachineNode); if (ResNode != MachineNode) { - DEBUG(dbgs() << "CR Peephole replacing:\nOld: "); - DEBUG(MachineNode->dump(CurDAG)); - DEBUG(dbgs() << "\nNew: "); - DEBUG(ResNode->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "CR Peephole replacing:\nOld: "); + LLVM_DEBUG(MachineNode->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nNew: "); + LLVM_DEBUG(ResNode->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); ReplaceUses(MachineNode, ResNode); IsModified = true; @@ -5984,25 +5984,25 @@ void PPCDAGToDAGISel::PeepholePPC64ZExt() { else NewVTs.push_back(VTs.VTs[i]); - DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: "); - DEBUG(PN->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: "); + LLVM_DEBUG(PN->dump(CurDAG)); CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops); - DEBUG(dbgs() << "\nNew: "); - DEBUG(PN->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\nNew: "); + LLVM_DEBUG(PN->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); } // Now we replace the original zero extend and its associated INSERT_SUBREG // with the value feeding the INSERT_SUBREG (which has now been promoted to // return an i64). - DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: "); - DEBUG(N->dump(CurDAG)); - DEBUG(dbgs() << "\nNew: "); - DEBUG(Op32.getNode()->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nNew: "); + LLVM_DEBUG(Op32.getNode()->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); ReplaceUses(N, Op32.getNode()); } @@ -6177,11 +6177,11 @@ void PPCDAGToDAGISel::PeepholePPC64() { // immediate and substitute them into the load or store. If // needed, update the target flags for the immediate operand to // reflect the necessary relocation information. - DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); - DEBUG(Base->dump(CurDAG)); - DEBUG(dbgs() << "\nN: "); - DEBUG(N->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + LLVM_DEBUG(Base->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nN: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); // If the relocation information isn't already present on the // immediate operand, add it now. @@ -6194,7 +6194,7 @@ void PPCDAGToDAGISel::PeepholePPC64() { if (GV->getAlignment() < 4 && (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || StorageOpcode == PPC::LWA || (Offset % 4) != 0)) { - DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + LLVM_DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); continue; } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, Offset, Flags); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index abd7513a391..1f787994d9d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -5133,15 +5133,15 @@ PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, assert(isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."); - DEBUG( - const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal(); - const unsigned Width = 80 - strlen("TCO caller: ") - - strlen(", callee linkage: 0, 0"); - dbgs() << "TCO caller: " - << left_justify(DAG.getMachineFunction().getName(), Width) - << ", callee linkage: " - << GV->getVisibility() << ", " << GV->getLinkage() << "\n" - ); + LLVM_DEBUG( + const GlobalValue *GV = + cast<GlobalAddressSDNode>(Callee)->getGlobal(); + const unsigned Width = + 80 - strlen("TCO caller: ") - strlen(", callee linkage: 0, 0"); + dbgs() << "TCO caller: " + << left_justify(DAG.getMachineFunction().getName(), Width) + << ", callee linkage: " << GV->getVisibility() << ", " + << GV->getLinkage() << "\n"); } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 4ec98e2da98..c095ccbc1ee 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2418,16 +2418,17 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, CompareUseMI.RemoveOperand(2); continue; } - DEBUG(dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"); - DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump()); - DEBUG(dbgs() << "Is converted to:\n"); + LLVM_DEBUG( + dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"); + LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump()); + LLVM_DEBUG(dbgs() << "Is converted to:\n"); // Convert to copy and remove unneeded operands. CompareUseMI.setDesc(get(PPC::COPY)); CompareUseMI.RemoveOperand(3); CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1); CmpIselsConverted++; Changed = true; - DEBUG(CompareUseMI.dump()); + LLVM_DEBUG(CompareUseMI.dump()); } if (Changed) return true; @@ -2528,10 +2529,10 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, } if (ReplaceWithLI) { - DEBUG(dbgs() << "Replacing instruction:\n"); - DEBUG(MI.dump()); - DEBUG(dbgs() << "Fed by:\n"); - DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << "Replacing instruction:\n"); + LLVM_DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Fed by:\n"); + LLVM_DEBUG(DefMI->dump()); LoadImmediateInfo LII; LII.Imm = NewImm; LII.Is64Bit = Is64BitLI; @@ -2541,8 +2542,8 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, if (KilledDef && SetCR) *KilledDef = nullptr; replaceInstrWithLI(MI, LII); - DEBUG(dbgs() << "With:\n"); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "With:\n"); + LLVM_DEBUG(MI.dump()); return true; } return false; diff --git a/llvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp b/llvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp index 6bfccddda65..c360fca91c8 100644 --- a/llvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp +++ b/llvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp @@ -247,7 +247,7 @@ bool PPCLoopPreIncPrep::runOnLoop(Loop *L) { if (!L->empty()) return MadeChange; - DEBUG(dbgs() << "PIP: Examining: " << *L << "\n"); + LLVM_DEBUG(dbgs() << "PIP: Examining: " << *L << "\n"); BasicBlock *Header = L->getHeader(); @@ -332,7 +332,7 @@ bool PPCLoopPreIncPrep::runOnLoop(Loop *L) { if (!LoopPredecessor) return MadeChange; - DEBUG(dbgs() << "PIP: Found " << Buckets.size() << " buckets\n"); + LLVM_DEBUG(dbgs() << "PIP: Found " << Buckets.size() << " buckets\n"); SmallSet<BasicBlock *, 16> BBChanged; for (unsigned i = 0, e = Buckets.size(); i != e; ++i) { @@ -381,7 +381,7 @@ bool PPCLoopPreIncPrep::runOnLoop(Loop *L) { if (!BasePtrSCEV->isAffine()) continue; - DEBUG(dbgs() << "PIP: Transforming: " << *BasePtrSCEV << "\n"); + LLVM_DEBUG(dbgs() << "PIP: Transforming: " << *BasePtrSCEV << "\n"); assert(BasePtrSCEV->getLoop() == L && "AddRec for the wrong loop?"); @@ -407,7 +407,7 @@ bool PPCLoopPreIncPrep::runOnLoop(Loop *L) { if (!isSafeToExpand(BasePtrStartSCEV, *SE)) continue; - DEBUG(dbgs() << "PIP: New start is: " << *BasePtrStartSCEV << "\n"); + LLVM_DEBUG(dbgs() << "PIP: New start is: " << *BasePtrStartSCEV << "\n"); if (alreadyPrepared(L, MemI, BasePtrStartSCEV, BasePtrIncSCEV)) continue; diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 6f44e3adcfe..79bba982858 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -119,8 +119,8 @@ void PPCMIPeephole::initialize(MachineFunction &MFParm) { MRI = &MF->getRegInfo(); MDT = &getAnalysis<MachineDominatorTree>(); TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); - DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); - DEBUG(MF->dump()); + LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); + LLVM_DEBUG(MF->dump()); } static MachineInstr *getVRegDefOrNull(MachineOperand *Op, @@ -238,8 +238,8 @@ bool PPCMIPeephole::simplifyCode(void) { if (TII->convertToImmediateForm(MI)) { // We don't erase anything in case the def has other uses. Let DCE // remove it if it can be removed. - DEBUG(dbgs() << "Converted instruction to imm form: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); + LLVM_DEBUG(MI.dump()); NumConvertedToImmediateForm++; SomethingChanged = true; Simplified = true; @@ -324,10 +324,9 @@ bool PPCMIPeephole::simplifyCode(void) { }; if (DefMI && (Immed == 0 || Immed == 3)) { if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) { - DEBUG(dbgs() - << "Optimizing load-and-splat/splat " - "to load-and-splat/copy: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat " + "to load-and-splat/copy: "); + LLVM_DEBUG(MI.dump()); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), MI.getOperand(0).getReg()) .add(MI.getOperand(1)); @@ -346,10 +345,9 @@ bool PPCMIPeephole::simplifyCode(void) { TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) { - DEBUG(dbgs() - << "Optimizing splat/swap or splat/splat " - "to splat/copy: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat " + "to splat/copy: "); + LLVM_DEBUG(MI.dump()); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), MI.getOperand(0).getReg()) .add(MI.getOperand(1)); @@ -362,8 +360,8 @@ bool PPCMIPeephole::simplifyCode(void) { // parameter. else if ((Immed == 0 || Immed == 3) && FeedImmed == 2 && FeedReg1 == FeedReg2) { - DEBUG(dbgs() << "Optimizing swap/splat => splat: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: "); + LLVM_DEBUG(MI.dump()); MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); MI.getOperand(3).setImm(3 - Immed); @@ -373,8 +371,8 @@ bool PPCMIPeephole::simplifyCode(void) { // If this is a swap fed by a swap, we can replace it // with a copy from the first swap's input. else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) { - DEBUG(dbgs() << "Optimizing swap/swap => copy: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: "); + LLVM_DEBUG(MI.dump()); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), MI.getOperand(0).getReg()) .add(DefMI->getOperand(1)); @@ -389,8 +387,8 @@ bool PPCMIPeephole::simplifyCode(void) { DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); ToErase = &MI; Simplified = true; - DEBUG(dbgs() << "Removing redundant splat: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Removing redundant splat: "); + LLVM_DEBUG(MI.dump()); } } } @@ -429,8 +427,8 @@ bool PPCMIPeephole::simplifyCode(void) { // If the instruction[s] that feed this splat have already splat // the value, this splat is redundant. if (AlreadySplat) { - DEBUG(dbgs() << "Changing redundant splat to a copy: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: "); + LLVM_DEBUG(MI.dump()); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), MI.getOperand(0).getReg()) .add(MI.getOperand(OpNo)); @@ -448,14 +446,14 @@ bool PPCMIPeephole::simplifyCode(void) { if (ShiftOp1 == ShiftOp2) { unsigned NewElem = (SplatImm + ShiftImm) & 0x3; if (MRI->hasOneNonDBGUse(ShiftRes)) { - DEBUG(dbgs() << "Removing redundant shift: "); - DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << "Removing redundant shift: "); + LLVM_DEBUG(DefMI->dump()); ToErase = DefMI; } Simplified = true; - DEBUG(dbgs() << "Changing splat immediate from " << SplatImm << - " to " << NewElem << " in instruction: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm + << " to " << NewElem << " in instruction: "); + LLVM_DEBUG(MI.dump()); MI.getOperand(1).setReg(ShiftOp1); MI.getOperand(2).setImm(NewElem); } @@ -499,12 +497,12 @@ bool PPCMIPeephole::simplifyCode(void) { if (Use.getOperand(i).isReg() && Use.getOperand(i).getReg() == FRSPDefines) Use.getOperand(i).setReg(ConvReg1); - DEBUG(dbgs() << "Removing redundant FRSP:\n"); - DEBUG(RoundInstr->dump()); - DEBUG(dbgs() << "As it feeds instruction:\n"); - DEBUG(MI.dump()); - DEBUG(dbgs() << "Through instruction:\n"); - DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n"); + LLVM_DEBUG(RoundInstr->dump()); + LLVM_DEBUG(dbgs() << "As it feeds instruction:\n"); + LLVM_DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Through instruction:\n"); + LLVM_DEBUG(DefMI->dump()); RoundInstr->eraseFromParent(); } }; @@ -552,11 +550,11 @@ bool PPCMIPeephole::simplifyCode(void) { }; unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), isXForm(SrcMI->getOpcode())); - DEBUG(dbgs() << "Zero-extending load\n"); - DEBUG(SrcMI->dump()); - DEBUG(dbgs() << "and sign-extension\n"); - DEBUG(MI.dump()); - DEBUG(dbgs() << "are merged into sign-extending load\n"); + LLVM_DEBUG(dbgs() << "Zero-extending load\n"); + LLVM_DEBUG(SrcMI->dump()); + LLVM_DEBUG(dbgs() << "and sign-extension\n"); + LLVM_DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); SrcMI->setDesc(TII->get(Opc)); SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); ToErase = &MI; @@ -596,11 +594,11 @@ bool PPCMIPeephole::simplifyCode(void) { }; unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), isXForm(SrcMI->getOpcode())); - DEBUG(dbgs() << "Zero-extending load\n"); - DEBUG(SrcMI->dump()); - DEBUG(dbgs() << "and sign-extension\n"); - DEBUG(MI.dump()); - DEBUG(dbgs() << "are merged into sign-extending load\n"); + LLVM_DEBUG(dbgs() << "Zero-extending load\n"); + LLVM_DEBUG(SrcMI->dump()); + LLVM_DEBUG(dbgs() << "and sign-extension\n"); + LLVM_DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); SrcMI->setDesc(TII->get(Opc)); SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); ToErase = &MI; @@ -610,7 +608,7 @@ bool PPCMIPeephole::simplifyCode(void) { TII->isSignExtended(*SrcMI)) { // We can eliminate EXTSW if the input is known to be already // sign-extended. - DEBUG(dbgs() << "Removing redundant sign-extension\n"); + LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n"); unsigned TmpReg = MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), @@ -661,7 +659,7 @@ bool PPCMIPeephole::simplifyCode(void) { unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII); if (MI.getOperand(3).getImm() <= KnownZeroCount) { - DEBUG(dbgs() << "Removing redundant zero-extension\n"); + LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n"); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), MI.getOperand(0).getReg()) .addReg(SrcReg); @@ -727,8 +725,8 @@ bool PPCMIPeephole::simplifyCode(void) { MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); - DEBUG(dbgs() << "Optimizing LI to ADDI: "); - DEBUG(LiMI->dump()); + LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: "); + LLVM_DEBUG(LiMI->dump()); // There could be repeated registers in the PHI, e.g: %1 = // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've @@ -746,12 +744,12 @@ bool PPCMIPeephole::simplifyCode(void) { MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI) .addReg(DominatorReg) .addImm(LiImm); // restore the imm of LI - DEBUG(LiMI->dump()); + LLVM_DEBUG(LiMI->dump()); } // Replace ADD with COPY - DEBUG(dbgs() << "Optimizing ADD to COPY: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: "); + LLVM_DEBUG(MI.dump()); BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), MI.getOperand(0).getReg()) .add(Op1); @@ -1197,11 +1195,11 @@ bool PPCMIPeephole::eliminateRedundantCompare(void) { continue; } - DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); - DEBUG(CMPI1->dump()); - DEBUG(BI1->dump()); - DEBUG(CMPI2->dump()); - DEBUG(BI2->dump()); + LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); + LLVM_DEBUG(CMPI1->dump()); + LLVM_DEBUG(BI1->dump()); + LLVM_DEBUG(CMPI2->dump()); + LLVM_DEBUG(BI2->dump()); // We adjust opcode, predicates and immediate as we determined above. if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) { @@ -1260,15 +1258,15 @@ bool PPCMIPeephole::eliminateRedundantCompare(void) { BI2->getOperand(1).setIsKill(true); BI1->getOperand(1).setIsKill(false); - DEBUG(dbgs() << "into a compare and two branches:\n"); - DEBUG(CMPI1->dump()); - DEBUG(BI1->dump()); - DEBUG(BI2->dump()); + LLVM_DEBUG(dbgs() << "into a compare and two branches:\n"); + LLVM_DEBUG(CMPI1->dump()); + LLVM_DEBUG(BI1->dump()); + LLVM_DEBUG(BI2->dump()); if (IsPartiallyRedundant) { - DEBUG(dbgs() << "The following compare is moved into " - << printMBBReference(*MBBtoMoveCmp) - << " to handle partial redundancy.\n"); - DEBUG(CMPI2->dump()); + LLVM_DEBUG(dbgs() << "The following compare is moved into " + << printMBBReference(*MBBtoMoveCmp) + << " to handle partial redundancy.\n"); + LLVM_DEBUG(CMPI2->dump()); } Simplified = true; diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp index d524c354ed3..1892d1e3dc2 100644 --- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp @@ -67,8 +67,8 @@ namespace { if (TII->convertToImmediateForm(MI, &DefMIToErase)) { Changed = true; NumRRConvertedInPreEmit++; - DEBUG(dbgs() << "Converted instruction to imm form: "); - DEBUG(MI.dump()); + LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); + LLVM_DEBUG(MI.dump()); if (DefMIToErase) { InstrsToErase.push_back(DefMIToErase); } @@ -76,8 +76,8 @@ namespace { } } for (MachineInstr *MI : InstrsToErase) { - DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: "); + LLVM_DEBUG(MI->dump()); MI->eraseFromParent(); NumRemovedInPreEmit++; } diff --git a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp index 76e25af9449..d6d948e9e1e 100644 --- a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp +++ b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp @@ -150,8 +150,9 @@ static bool splitMBB(BlockSplitInfo &BSI) { MachineRegisterInfo *MRI = &MF->getRegInfo(); assert(MRI->isSSA() && "Can only do this while the function is in SSA form."); if (ThisMBB->succ_size() != 2) { - DEBUG(dbgs() << "Don't know how to handle blocks that don't have exactly" - << " two succesors.\n"); + LLVM_DEBUG( + dbgs() << "Don't know how to handle blocks that don't have exactly" + << " two succesors.\n"); return false; } @@ -218,9 +219,9 @@ static bool splitMBB(BlockSplitInfo &BSI) { } addIncomingValuesToPHIs(NewBRTarget, ThisMBB, NewMBB, MRI); - DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump()); - DEBUG(dbgs() << "NewMBB:\n"; NewMBB->dump()); - DEBUG(dbgs() << "New branch-to block:\n"; NewBRTarget->dump()); + LLVM_DEBUG(dbgs() << "After splitting, ThisMBB:\n"; ThisMBB->dump()); + LLVM_DEBUG(dbgs() << "NewMBB:\n"; NewMBB->dump()); + LLVM_DEBUG(dbgs() << "New branch-to block:\n"; NewBRTarget->dump()); return true; } @@ -491,7 +492,7 @@ PPCReduceCRLogicals::createCRLogicalOpInfo(MachineInstr &MIParam) { Ret.ContainedInBlock &= (MIParam.getParent() == Ret.TrueDefs.second->getParent()); } - DEBUG(Ret.dump()); + LLVM_DEBUG(Ret.dump()); if (Ret.IsBinary && Ret.ContainedInBlock && Ret.SingleUse) { NumContainedSingleUseBinOps++; if (Ret.FeedsBR && Ret.DefsSingleUse) @@ -585,14 +586,15 @@ bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) { /// BC %vr9<kill>, <BB#2>; CRBITRC:%vr9 bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) { if (CRI.CopyDefs.first == CRI.CopyDefs.second) { - DEBUG(dbgs() << "Unable to split as the two operands are the same\n"); + LLVM_DEBUG(dbgs() << "Unable to split as the two operands are the same\n"); NumNotSplitIdenticalOperands++; return false; } if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() || CRI.TrueDefs.first->isPHI() || CRI.TrueDefs.second->isPHI()) { - DEBUG(dbgs() << "Unable to split because one of the operands is a PHI or " - "chain of copies.\n"); + LLVM_DEBUG( + dbgs() << "Unable to split because one of the operands is a PHI or " + "chain of copies.\n"); NumNotSplitChainCopies++; return false; } @@ -603,11 +605,11 @@ bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) { CRI.MI->getOpcode() != PPC::CRNAND && CRI.MI->getOpcode() != PPC::CRORC && CRI.MI->getOpcode() != PPC::CRANDC) { - DEBUG(dbgs() << "Unable to split blocks on this opcode.\n"); + LLVM_DEBUG(dbgs() << "Unable to split blocks on this opcode.\n"); NumNotSplitWrongOpcode++; return false; } - DEBUG(dbgs() << "Splitting the following CR op:\n"; CRI.dump()); + LLVM_DEBUG(dbgs() << "Splitting the following CR op:\n"; CRI.dump()); MachineBasicBlock::iterator Def1It = CRI.TrueDefs.first; MachineBasicBlock::iterator Def2It = CRI.TrueDefs.second; @@ -621,9 +623,9 @@ bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) { } } - DEBUG(dbgs() << "We will split the following block:\n";); - DEBUG(CRI.MI->getParent()->dump()); - DEBUG(dbgs() << "Before instruction:\n"; SplitBefore->dump()); + LLVM_DEBUG(dbgs() << "We will split the following block:\n";); + LLVM_DEBUG(CRI.MI->getParent()->dump()); + LLVM_DEBUG(dbgs() << "Before instruction:\n"; SplitBefore->dump()); // Get the branch instruction. MachineInstr *Branch = @@ -656,10 +658,11 @@ bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) { TargetIsFallThrough); MachineInstr *SplitCond = UsingDef1 ? CRI.CopyDefs.second : CRI.CopyDefs.first; - DEBUG(dbgs() << "We will " << (InvertNewBranch ? "invert" : "copy")); - DEBUG(dbgs() << " the original branch and the target is the " << - (TargetIsFallThrough ? "fallthrough block\n" : "orig. target block\n")); - DEBUG(dbgs() << "Original branch instruction: "; Branch->dump()); + LLVM_DEBUG(dbgs() << "We will " << (InvertNewBranch ? "invert" : "copy")); + LLVM_DEBUG(dbgs() << " the original branch and the target is the " + << (TargetIsFallThrough ? "fallthrough block\n" + : "orig. target block\n")); + LLVM_DEBUG(dbgs() << "Original branch instruction: "; Branch->dump()); BlockSplitInfo BSI { Branch, SplitBefore, SplitCond, InvertNewBranch, InvertOrigBranch, TargetIsFallThrough, MBPI, CRI.MI, UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second }; diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp index 49f2699ab08..903d4e97701 100644 --- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp +++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp @@ -77,7 +77,7 @@ protected: continue; } - DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI); + LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI); unsigned OutReg = MI.getOperand(0).getReg(); unsigned InReg = MI.getOperand(1).getReg(); diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index f15af790de8..6586f503a7b 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -241,7 +241,7 @@ protected: assert(OldFMAReg == AddendMI->getOperand(0).getReg() && "Addend copy not tied to old FMA output!"); - DEBUG(dbgs() << "VSX FMA Mutation:\n " << MI); + LLVM_DEBUG(dbgs() << "VSX FMA Mutation:\n " << MI); MI.getOperand(0).setReg(KilledProdReg); MI.getOperand(1).setReg(KilledProdReg); @@ -273,7 +273,7 @@ protected: MI.getOperand(2).setIsUndef(OtherProdRegUndef); } - DEBUG(dbgs() << " -> " << MI); + LLVM_DEBUG(dbgs() << " -> " << MI); // The killed product operand was killed here, so we can reuse it now // for the result of the fma. @@ -310,7 +310,7 @@ protected: NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end, NewFMAValNo)); } - DEBUG(dbgs() << " extended: " << NewFMAInt << '\n'); + LLVM_DEBUG(dbgs() << " extended: " << NewFMAInt << '\n'); // Extend the live interval of the addend source (it might end at the // copy to be removed, or somewhere in between there and here). This @@ -323,15 +323,15 @@ protected: LiveRange &AddendSrcRange = LIS->getRegUnit(Unit); AddendSrcRange.extendInBlock(LIS->getMBBStartIdx(&MBB), FMAIdx.getRegSlot()); - DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n'); + LLVM_DEBUG(dbgs() << " extended: " << AddendSrcRange << '\n'); } FMAInt.removeValNo(FMAValNo); - DEBUG(dbgs() << " trimmed: " << FMAInt << '\n'); + LLVM_DEBUG(dbgs() << " trimmed: " << FMAInt << '\n'); // Remove the (now unused) copy. - DEBUG(dbgs() << " removing: " << *AddendMI << '\n'); + LLVM_DEBUG(dbgs() << " removing: " << *AddendMI << '\n'); LIS->RemoveMachineInstrFromMaps(*AddendMI); AddendMI->eraseFromParent(); diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp index 83c9dd67c33..2fe54a88b65 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp @@ -528,8 +528,8 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() { } if (RelevantFunction) { - DEBUG(dbgs() << "Swap vector when first built\n\n"); - DEBUG(dumpSwapVector()); + LLVM_DEBUG(dbgs() << "Swap vector when first built\n\n"); + LLVM_DEBUG(dumpSwapVector()); } return RelevantFunction; @@ -588,14 +588,14 @@ unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg, // as such so their containing webs will not be optimized. void PPCVSXSwapRemoval::formWebs() { - DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n"); + LLVM_DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n"); for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) { MachineInstr *MI = SwapVector[EntryIdx].VSEMI; - DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " "); + LLVM_DEBUG(MI->dump()); // It's sufficient to walk vector uses and join them to their unique // definitions. In addition, check full vector register operands @@ -625,10 +625,11 @@ void PPCVSXSwapRemoval::formWebs() { (void)EC->unionSets(SwapVector[DefIdx].VSEId, SwapVector[EntryIdx].VSEId); - DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId, - SwapVector[EntryIdx].VSEId)); - DEBUG(dbgs() << " Def: "); - DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << format("Unioning %d with %d\n", + SwapVector[DefIdx].VSEId, + SwapVector[EntryIdx].VSEId)); + LLVM_DEBUG(dbgs() << " Def: "); + LLVM_DEBUG(DefMI->dump()); } } } @@ -639,7 +640,7 @@ void PPCVSXSwapRemoval::formWebs() { // as rejected. void PPCVSXSwapRemoval::recordUnoptimizableWebs() { - DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n"); + LLVM_DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n"); for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) { int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId); @@ -657,12 +658,13 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() { SwapVector[Repr].WebRejected = 1; - DEBUG(dbgs() << - format("Web %d rejected for physreg, partial reg, or not " - "swap[pable]\n", Repr)); - DEBUG(dbgs() << " in " << EntryIdx << ": "); - DEBUG(SwapVector[EntryIdx].VSEMI->dump()); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG( + dbgs() << format("Web %d rejected for physreg, partial reg, or not " + "swap[pable]\n", + Repr)); + LLVM_DEBUG(dbgs() << " in " << EntryIdx << ": "); + LLVM_DEBUG(SwapVector[EntryIdx].VSEMI->dump()); + LLVM_DEBUG(dbgs() << "\n"); } // Reject webs than contain swapping loads that feed something other @@ -683,13 +685,13 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() { SwapVector[Repr].WebRejected = 1; - DEBUG(dbgs() << - format("Web %d rejected for load not feeding swap\n", Repr)); - DEBUG(dbgs() << " def " << EntryIdx << ": "); - DEBUG(MI->dump()); - DEBUG(dbgs() << " use " << UseIdx << ": "); - DEBUG(UseMI.dump()); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << format( + "Web %d rejected for load not feeding swap\n", Repr)); + LLVM_DEBUG(dbgs() << " def " << EntryIdx << ": "); + LLVM_DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); + LLVM_DEBUG(UseMI.dump()); + LLVM_DEBUG(dbgs() << "\n"); } } @@ -707,13 +709,13 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() { SwapVector[Repr].WebRejected = 1; - DEBUG(dbgs() << - format("Web %d rejected for store not fed by swap\n", Repr)); - DEBUG(dbgs() << " def " << DefIdx << ": "); - DEBUG(DefMI->dump()); - DEBUG(dbgs() << " use " << EntryIdx << ": "); - DEBUG(MI->dump()); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << format( + "Web %d rejected for store not fed by swap\n", Repr)); + LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); + LLVM_DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << " use " << EntryIdx << ": "); + LLVM_DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << "\n"); } // Ensure all uses of the register defined by DefMI feed store @@ -724,21 +726,22 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() { if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) { SwapVector[Repr].WebRejected = 1; - DEBUG(dbgs() << - format("Web %d rejected for swap not feeding only stores\n", - Repr)); - DEBUG(dbgs() << " def " << " : "); - DEBUG(DefMI->dump()); - DEBUG(dbgs() << " use " << UseIdx << ": "); - DEBUG(SwapVector[UseIdx].VSEMI->dump()); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG( + dbgs() << format( + "Web %d rejected for swap not feeding only stores\n", Repr)); + LLVM_DEBUG(dbgs() << " def " + << " : "); + LLVM_DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << " use " << UseIdx << ": "); + LLVM_DEBUG(SwapVector[UseIdx].VSEMI->dump()); + LLVM_DEBUG(dbgs() << "\n"); } } } } - DEBUG(dbgs() << "Swap vector after web analysis:\n\n"); - DEBUG(dumpSwapVector()); + LLVM_DEBUG(dbgs() << "Swap vector after web analysis:\n\n"); + LLVM_DEBUG(dumpSwapVector()); } // Walk the swap vector entries looking for swaps fed by permuting loads @@ -748,7 +751,7 @@ void PPCVSXSwapRemoval::recordUnoptimizableWebs() { // such that multiple loads feed the same swap, etc.) void PPCVSXSwapRemoval::markSwapsForRemoval() { - DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n"); + LLVM_DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n"); for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) { @@ -763,8 +766,8 @@ void PPCVSXSwapRemoval::markSwapsForRemoval() { int UseIdx = SwapMap[&UseMI]; SwapVector[UseIdx].WillRemove = 1; - DEBUG(dbgs() << "Marking swap fed by load for removal: "); - DEBUG(UseMI.dump()); + LLVM_DEBUG(dbgs() << "Marking swap fed by load for removal: "); + LLVM_DEBUG(UseMI.dump()); } } @@ -778,8 +781,8 @@ void PPCVSXSwapRemoval::markSwapsForRemoval() { int DefIdx = SwapMap[DefMI]; SwapVector[DefIdx].WillRemove = 1; - DEBUG(dbgs() << "Marking swap feeding store for removal: "); - DEBUG(DefMI->dump()); + LLVM_DEBUG(dbgs() << "Marking swap feeding store for removal: "); + LLVM_DEBUG(DefMI->dump()); } } else if (SwapVector[EntryIdx].IsSwappable && @@ -824,8 +827,8 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { MachineInstr *MI = SwapVector[EntryIdx].VSEMI; unsigned NElts; - DEBUG(dbgs() << "Changing splat: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << "Changing splat: "); + LLVM_DEBUG(MI->dump()); switch (MI->getOpcode()) { default: @@ -848,8 +851,8 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { else MI->getOperand(1).setImm(EltNo); - DEBUG(dbgs() << " Into: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << " Into: "); + LLVM_DEBUG(MI->dump()); break; } @@ -862,8 +865,8 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { case SHValues::SH_XXPERMDI: { MachineInstr *MI = SwapVector[EntryIdx].VSEMI; - DEBUG(dbgs() << "Changing XXPERMDI: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << "Changing XXPERMDI: "); + LLVM_DEBUG(MI->dump()); unsigned Selector = MI->getOperand(3).getImm(); if (Selector == 0 || Selector == 3) @@ -875,8 +878,8 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { MI->getOperand(1).setReg(Reg2); MI->getOperand(2).setReg(Reg1); - DEBUG(dbgs() << " Into: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << " Into: "); + LLVM_DEBUG(MI->dump()); break; } @@ -886,16 +889,16 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { case SHValues::SH_COPYWIDEN: { MachineInstr *MI = SwapVector[EntryIdx].VSEMI; - DEBUG(dbgs() << "Changing SUBREG_TO_REG: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << "Changing SUBREG_TO_REG: "); + LLVM_DEBUG(MI->dump()); unsigned DstReg = MI->getOperand(0).getReg(); const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); unsigned NewVReg = MRI->createVirtualRegister(DstRC); MI->getOperand(0).setReg(NewVReg); - DEBUG(dbgs() << " Into: "); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << " Into: "); + LLVM_DEBUG(MI->dump()); auto InsertPoint = ++MachineBasicBlock::iterator(MI); @@ -911,19 +914,19 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(), TII->get(PPC::COPY), VSRCTmp1) .addReg(NewVReg); - DEBUG(std::prev(InsertPoint)->dump()); + LLVM_DEBUG(std::prev(InsertPoint)->dump()); insertSwap(MI, InsertPoint, VSRCTmp2, VSRCTmp1); - DEBUG(std::prev(InsertPoint)->dump()); + LLVM_DEBUG(std::prev(InsertPoint)->dump()); BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(), TII->get(PPC::COPY), DstReg) .addReg(VSRCTmp2); - DEBUG(std::prev(InsertPoint)->dump()); + LLVM_DEBUG(std::prev(InsertPoint)->dump()); } else { insertSwap(MI, InsertPoint, DstReg, NewVReg); - DEBUG(std::prev(InsertPoint)->dump()); + LLVM_DEBUG(std::prev(InsertPoint)->dump()); } break; } @@ -934,7 +937,7 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) { // a copy operation. bool PPCVSXSwapRemoval::removeSwaps() { - DEBUG(dbgs() << "\n*** Removing swaps ***\n\n"); + LLVM_DEBUG(dbgs() << "\n*** Removing swaps ***\n\n"); bool Changed = false; @@ -947,9 +950,9 @@ bool PPCVSXSwapRemoval::removeSwaps() { MI->getOperand(0).getReg()) .add(MI->getOperand(1)); - DEBUG(dbgs() << format("Replaced %d with copy: ", - SwapVector[EntryIdx].VSEId)); - DEBUG(MI->dump()); + LLVM_DEBUG(dbgs() << format("Replaced %d with copy: ", + SwapVector[EntryIdx].VSEId)); + LLVM_DEBUG(MI->dump()); MI->eraseFromParent(); } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 91c72aa191d..7bbb371a757 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -258,14 +258,15 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, // It's a 32 bit instruction if bit 0 and 1 are 1. if ((Bytes[0] & 0x3) == 0x3) { Insn = support::endian::read32le(Bytes.data()); - DEBUG(dbgs() << "Trying RISCV32 table :\n"); + LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); Size = 4; } else { Insn = support::endian::read16le(Bytes.data()); if (!STI.getFeatureBits()[RISCV::Feature64Bit]) { - DEBUG(dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n"); + LLVM_DEBUG( + dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address, this, STI); @@ -275,7 +276,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, } } - DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n"); + LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); Size = 2; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index b7d06879cad..04441b9a9b1 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -71,7 +71,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we have already selected if (Node->isMachineOpcode()) { - DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n"); Node->setNodeId(-1); return; } @@ -196,11 +196,11 @@ void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() { continue; } - DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); - DEBUG(Base->dump(CurDAG)); - DEBUG(dbgs() << "\nN: "); - DEBUG(N->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + LLVM_DEBUG(Base->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nN: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); // Modify the offset operand of the load/store. if (BaseOpIdx == 0) // Load @@ -237,13 +237,14 @@ void RISCVDAGToDAGISel::doPeepholeBuildPairF64SplitF64() { SDValue F64Val = N->getOperand(0); if (F64Val.isMachineOpcode() && F64Val.getMachineOpcode() == RISCV::BuildPairF64Pseudo) { - DEBUG(dbgs() << "Removing redundant SplitF64Pseudo and replacing uses " - "with BuildPairF64Pseudo operands:\n"); - DEBUG(dbgs() << "N: "); - DEBUG(N->dump(CurDAG)); - DEBUG(dbgs() << "F64Val: "); - DEBUG(F64Val->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG( + dbgs() << "Removing redundant SplitF64Pseudo and replacing uses " + "with BuildPairF64Pseudo operands:\n"); + LLVM_DEBUG(dbgs() << "N: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "F64Val: "); + LLVM_DEBUG(F64Val->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); SDValue From[] = {SDValue(N, 0), SDValue(N, 1)}; SDValue To[] = {F64Val.getOperand(0), F64Val.getOperand(1)}; CurDAG->ReplaceAllUsesOfValuesWith(From, To, 2); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ead9f0bdc63..52c027ba314 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -824,8 +824,8 @@ void RISCVTargetLowering::analyzeInputArgs( if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) { - DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " - << EVT(ArgVT).getEVTString() << '\n'); + LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " + << EVT(ArgVT).getEVTString() << '\n'); llvm_unreachable(nullptr); } } @@ -844,8 +844,8 @@ void RISCVTargetLowering::analyzeOutputArgs( if (CC_RISCV(MF.getDataLayout(), i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) { - DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " - << EVT(ArgVT).getEVTString() << "\n"); + LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " + << EVT(ArgVT).getEVTString() << "\n"); llvm_unreachable(nullptr); } } diff --git a/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp b/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp index a643b056528..9e8acdaabd9 100644 --- a/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp +++ b/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp @@ -85,7 +85,7 @@ void SystemZHazardRecognizer::Reset() { GrpCount = 0; LastFPdOpCycleIdx = UINT_MAX; LastEmittedMI = nullptr; - DEBUG(CurGroupDbg = "";); + LLVM_DEBUG(CurGroupDbg = "";); } bool @@ -112,8 +112,8 @@ void SystemZHazardRecognizer::nextGroup() { if (CurrGroupSize == 0) return; - DEBUG(dumpCurrGroup("Completed decode group")); - DEBUG(CurGroupDbg = "";); + LLVM_DEBUG(dumpCurrGroup("Completed decode group")); + LLVM_DEBUG(CurGroupDbg = "";); GrpCount++; @@ -131,7 +131,7 @@ void SystemZHazardRecognizer::nextGroup() { ProcResCostLim)) CriticalResourceIdx = UINT_MAX; - DEBUG(dumpState();); + LLVM_DEBUG(dumpState();); } #ifndef NDEBUG // Debug output @@ -234,25 +234,23 @@ static inline bool isBranchRetTrap(MachineInstr *MI) { void SystemZHazardRecognizer:: EmitInstruction(SUnit *SU) { const MCSchedClassDesc *SC = getSchedClass(SU); - DEBUG(dbgs() << "++ HazardRecognizer emitting "; dumpSU(SU, dbgs()); - dbgs() << "\n";); - DEBUG(dumpCurrGroup("Decode group before emission");); + LLVM_DEBUG(dbgs() << "++ HazardRecognizer emitting "; dumpSU(SU, dbgs()); + dbgs() << "\n";); + LLVM_DEBUG(dumpCurrGroup("Decode group before emission");); // If scheduling an SU that must begin a new decoder group, move on // to next group. if (!fitsIntoCurrentGroup(SU)) nextGroup(); - DEBUG(raw_string_ostream cgd(CurGroupDbg); - if (CurGroupDbg.length()) - cgd << ", "; - dumpSU(SU, cgd);); + LLVM_DEBUG(raw_string_ostream cgd(CurGroupDbg); + if (CurGroupDbg.length()) cgd << ", "; dumpSU(SU, cgd);); LastEmittedMI = SU->getInstr(); // After returning from a call, we don't know much about the state. if (SU->isCall) { - DEBUG(dbgs() << "++ Clearing state after call.\n";); + LLVM_DEBUG(dbgs() << "++ Clearing state after call.\n";); Reset(); LastEmittedMI = SU->getInstr(); return; @@ -274,9 +272,10 @@ EmitInstruction(SUnit *SU) { (PI->ProcResourceIdx != CriticalResourceIdx && CurrCounter > ProcResourceCounters[CriticalResourceIdx]))) { - DEBUG(dbgs() << "++ New critical resource: " - << SchedModel->getProcResource(PI->ProcResourceIdx)->Name - << "\n";); + LLVM_DEBUG( + dbgs() << "++ New critical resource: " + << SchedModel->getProcResource(PI->ProcResourceIdx)->Name + << "\n";); CriticalResourceIdx = PI->ProcResourceIdx; } } @@ -284,8 +283,8 @@ EmitInstruction(SUnit *SU) { // Make note of an instruction that uses a blocking resource (FPd). if (SU->isUnbuffered) { LastFPdOpCycleIdx = getCurrCycleIdx(SU); - DEBUG(dbgs() << "++ Last FPd cycle index: " - << LastFPdOpCycleIdx << "\n";); + LLVM_DEBUG(dbgs() << "++ Last FPd cycle index: " << LastFPdOpCycleIdx + << "\n";); } // Insert SU into current group by increasing number of slots used @@ -409,7 +408,7 @@ void SystemZHazardRecognizer:: copyState(SystemZHazardRecognizer *Incoming) { // Current decoder group CurrGroupSize = Incoming->CurrGroupSize; - DEBUG(CurGroupDbg = Incoming->CurGroupDbg;); + LLVM_DEBUG(CurGroupDbg = Incoming->CurGroupDbg;); // Processor resources ProcResourceCounters = Incoming->ProcResourceCounters; diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 3e13cf249a5..99f17639d2e 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -589,7 +589,7 @@ bool SystemZDAGToDAGISel::selectAddress(SDValue Addr, if (AM.isDynAlloc() && !AM.IncludesDynAlloc) return false; - DEBUG(AM.dump()); + LLVM_DEBUG(AM.dump()); return true; } @@ -1427,7 +1427,7 @@ bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N, void SystemZDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); Node->setNodeId(-1); return; } @@ -1827,11 +1827,11 @@ void SystemZDAGToDAGISel::PreprocessISelDAG() { } if (Res) { - DEBUG(dbgs() << "SystemZ DAG preprocessing replacing:\nOld: "); - DEBUG(N->dump(CurDAG)); - DEBUG(dbgs() << "\nNew: "); - DEBUG(Res.getNode()->dump(CurDAG)); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SystemZ DAG preprocessing replacing:\nOld: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nNew: "); + LLVM_DEBUG(Res.getNode()->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res); MadeChange = true; diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp index 1de11a1166d..fcbf4c4b5fe 100644 --- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp +++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp @@ -72,23 +72,22 @@ advanceTo(MachineBasicBlock::iterator NextBegin) { } void SystemZPostRASchedStrategy::initialize(ScheduleDAGMI *dag) { - DEBUG(HazardRec->dumpState();); + LLVM_DEBUG(HazardRec->dumpState();); } void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) { assert ((SchedStates.find(NextMBB) == SchedStates.end()) && "Entering MBB twice?"); - DEBUG(dbgs() << "** Entering " << printMBBReference(*NextMBB)); + LLVM_DEBUG(dbgs() << "** Entering " << printMBBReference(*NextMBB)); MBB = NextMBB; /// Create a HazardRec for MBB, save it in SchedStates and set HazardRec to /// point to it. HazardRec = SchedStates[MBB] = new SystemZHazardRecognizer(TII, &SchedModel); - DEBUG(const MachineLoop *Loop = MLI->getLoopFor(MBB); - if(Loop && Loop->getHeader() == MBB) - dbgs() << " (Loop header)"; - dbgs() << ":\n";); + LLVM_DEBUG(const MachineLoop *Loop = MLI->getLoopFor(MBB); + if (Loop && Loop->getHeader() == MBB) dbgs() << " (Loop header)"; + dbgs() << ":\n";); // Try to take over the state from a single predecessor, if it has been // scheduled. If this is not possible, we are done. @@ -98,17 +97,17 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) { SchedStates.find(SinglePredMBB) == SchedStates.end()) return; - DEBUG(dbgs() << "** Continued scheduling from " - << printMBBReference(*SinglePredMBB) << "\n";); + LLVM_DEBUG(dbgs() << "** Continued scheduling from " + << printMBBReference(*SinglePredMBB) << "\n";); HazardRec->copyState(SchedStates[SinglePredMBB]); - DEBUG(HazardRec->dumpState();); + LLVM_DEBUG(HazardRec->dumpState();); // Emit incoming terminator(s). Be optimistic and assume that branch // prediction will generally do "the right thing". for (MachineBasicBlock::iterator I = SinglePredMBB->getFirstTerminator(); I != SinglePredMBB->end(); I++) { - DEBUG(dbgs() << "** Emitting incoming branch: "; I->dump();); + LLVM_DEBUG(dbgs() << "** Emitting incoming branch: "; I->dump();); bool TakenBranch = (I->isBranch() && (TII->getBranchInfo(*I).Target->isReg() || // Relative branch TII->getBranchInfo(*I).Target->getMBB() == MBB)); @@ -119,7 +118,7 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) { } void SystemZPostRASchedStrategy::leaveMBB() { - DEBUG(dbgs() << "** Leaving " << printMBBReference(*MBB) << "\n";); + LLVM_DEBUG(dbgs() << "** Leaving " << printMBBReference(*MBB) << "\n";); // Advance to first terminator. The successor block will handle terminators // dependent on CFG layout (T/NT branch etc). @@ -165,14 +164,14 @@ SUnit *SystemZPostRASchedStrategy::pickNode(bool &IsTopNode) { // If only one choice, return it. if (Available.size() == 1) { - DEBUG(dbgs() << "** Only one: "; - HazardRec->dumpSU(*Available.begin(), dbgs()); dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "** Only one: "; + HazardRec->dumpSU(*Available.begin(), dbgs()); dbgs() << "\n";); return *Available.begin(); } // All nodes that are possible to schedule are stored by in the // Available set. - DEBUG(dbgs() << "** Available: "; Available.dump(*HazardRec);); + LLVM_DEBUG(dbgs() << "** Available: "; Available.dump(*HazardRec);); Candidate Best; for (auto *SU : Available) { @@ -183,13 +182,11 @@ SUnit *SystemZPostRASchedStrategy::pickNode(bool &IsTopNode) { // Remeber which SU is the best candidate. if (Best.SU == nullptr || c < Best) { Best = c; - DEBUG(dbgs() << "** Best so far: ";); + LLVM_DEBUG(dbgs() << "** Best so far: ";); } else - DEBUG(dbgs() << "** Tried : ";); - DEBUG(HazardRec->dumpSU(c.SU, dbgs()); - c.dumpCosts(); - dbgs() << " Height:" << c.SU->getHeight(); - dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "** Tried : ";); + LLVM_DEBUG(HazardRec->dumpSU(c.SU, dbgs()); c.dumpCosts(); + dbgs() << " Height:" << c.SU->getHeight(); dbgs() << "\n";); // Once we know we have seen all SUs that affect grouping or use unbuffered // resources, we can stop iterating if Best looks good. @@ -243,12 +240,9 @@ operator<(const Candidate &other) { } void SystemZPostRASchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { - DEBUG(dbgs() << "** Scheduling SU(" << SU->NodeNum << ") "; - if (Available.size() == 1) - dbgs() << "(only one) "; - Candidate c(SU, *HazardRec); - c.dumpCosts(); - dbgs() << "\n";); + LLVM_DEBUG(dbgs() << "** Scheduling SU(" << SU->NodeNum << ") "; + if (Available.size() == 1) dbgs() << "(only one) "; + Candidate c(SU, *HazardRec); c.dumpCosts(); dbgs() << "\n";); // Remove SU from Available set and update HazardRec. Available.erase(SU); diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp index 2efac06e5be..d58c83d14ae 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp @@ -88,7 +88,8 @@ void WebAssemblyMCCodeEmitter::encodeInstruction( assert(Desc.TSFlags == 0 && "WebAssembly non-variable_ops don't use TSFlags"); const MCOperandInfo &Info = Desc.OpInfo[i]; - DEBUG(dbgs() << "Encoding immediate: type=" << int(Info.OperandType) << "\n"); + LLVM_DEBUG(dbgs() << "Encoding immediate: type=" + << int(Info.OperandType) << "\n"); if (Info.OperandType == WebAssembly::OPERAND_I32IMM) { encodeSLEB128(int32_t(MO.getImm()), OS); } else if (Info.OperandType == WebAssembly::OPERAND_OFFSET32) { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp index 3c17b2ec0f6..7c8a631cde8 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp @@ -68,7 +68,7 @@ FunctionPass *llvm::createWebAssemblyArgumentMove() { } bool WebAssemblyArgumentMove::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Argument Move **********\n" << "********** Function: " << MF.getName() << '\n'; }); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index a224ae7316a..c85050ce2e5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -54,7 +54,7 @@ MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const { MVT::v4i32, MVT::v4f32}) if (TRI->isTypeLegalForClass(*TRC, T)) return T; - DEBUG(errs() << "Unknown type for register number: " << RegNo); + LLVM_DEBUG(errs() << "Unknown type for register number: " << RegNo); llvm_unreachable("Unknown register type"); return MVT::Other; } @@ -191,7 +191,7 @@ void WebAssemblyAsmPrinter::EmitFunctionBodyEnd() { } void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) { - DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n'); + LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n'); switch (MI->getOpcode()) { case WebAssembly::ARGUMENT_I32: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp index b2607f27142..bb1b8254984 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp @@ -264,9 +264,9 @@ static void SortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI, } bool WebAssemblyCFGSort::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** CFG Sorting **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** CFG Sorting **********\n" + "********** Function: " + << MF.getName() << '\n'); const auto &MLI = getAnalysis<MachineLoopInfo>(); auto &MDT = getAnalysis<MachineDominatorTree>(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp index 3429c4fc6e2..1245ac03727 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp @@ -366,9 +366,9 @@ static void PlaceMarkers(MachineFunction &MF, const MachineLoopInfo &MLI, } bool WebAssemblyCFGStackify::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** CFG Stackifying **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** CFG Stackifying **********\n" + "********** Function: " + << MF.getName() << '\n'); const auto &MLI = getAnalysis<MachineLoopInfo>(); auto &MDT = getAnalysis<MachineDominatorTree>(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp index 03bfe24e30b..c1820bf66bc 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp @@ -83,8 +83,8 @@ static bool IsPseudoCallIndirect(const MachineInstr &MI) { } bool WebAssemblyCallIndirectFixup::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Fixing up CALL_INDIRECTs **********\n" - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Fixing up CALL_INDIRECTs **********\n" + << MF.getName() << '\n'); bool Changed = false; const WebAssemblyInstrInfo *TII = @@ -93,7 +93,7 @@ bool WebAssemblyCallIndirectFixup::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { if (IsPseudoCallIndirect(MI)) { - DEBUG(dbgs() << "Found call_indirect: " << MI << '\n'); + LLVM_DEBUG(dbgs() << "Found call_indirect: " << MI << '\n'); // Rewrite pseudo to non-pseudo const MCInstrDesc &Desc = TII->get(GetNonPseudoCallIndirectOpcode(MI)); @@ -123,13 +123,13 @@ bool WebAssemblyCallIndirectFixup::runOnMachineFunction(MachineFunction &MF) { for (const MachineOperand &MO : Ops) MI.addOperand(MO); - DEBUG(dbgs() << " After transform: " << MI); + LLVM_DEBUG(dbgs() << " After transform: " << MI); Changed = true; } } } - DEBUG(dbgs() << "\nDone fixing up CALL_INDIRECTs\n\n"); + LLVM_DEBUG(dbgs() << "\nDone fixing up CALL_INDIRECTs\n\n"); return Changed; } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp index caf12a610be..8639cb9fc86 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp @@ -181,9 +181,9 @@ static MachineInstr *FindStartOfTree(MachineOperand &MO, } bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Make Locals Explicit **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Make Locals Explicit **********\n" + "********** Function: " + << MF.getName() << '\n'); // Disable this pass if directed to do so. if (DisableWebAssemblyExplicitLocals) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp index c710c6972a6..bea027be771 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp @@ -177,7 +177,7 @@ bool WebAssemblyFixIrreducibleControlFlow::VisitLoop(MachineFunction &MF, if (LLVM_LIKELY(RewriteSuccs.empty())) return false; - DEBUG(dbgs() << "Irreducible control flow detected!\n"); + LLVM_DEBUG(dbgs() << "Irreducible control flow detected!\n"); // Ok. We have irreducible control flow! Create a dispatch block which will // contains a jump table to any block in the problematic set of blocks. @@ -208,7 +208,8 @@ bool WebAssemblyFixIrreducibleControlFlow::VisitLoop(MachineFunction &MF, continue; unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; - DEBUG(dbgs() << printMBBReference(*MBB) << " has index " << Index << "\n"); + LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has index " << Index + << "\n"); Pair.first->second = Index; for (auto Pred : MBB->predecessors()) @@ -267,9 +268,9 @@ bool WebAssemblyFixIrreducibleControlFlow::VisitLoop(MachineFunction &MF, bool WebAssemblyFixIrreducibleControlFlow::runOnMachineFunction( MachineFunction &MF) { - DEBUG(dbgs() << "********** Fixing Irreducible Control Flow **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Fixing Irreducible Control Flow **********\n" + "********** Function: " + << MF.getName() << '\n'); bool Changed = false; auto &MLI = getAnalysis<MachineLoopInfo>(); @@ -287,7 +288,7 @@ bool WebAssemblyFixIrreducibleControlFlow::runOnMachineFunction( // If we made any changes, completely recompute everything. if (LLVM_UNLIKELY(Changed)) { - DEBUG(dbgs() << "Recomputing dominators and loops.\n"); + LLVM_DEBUG(dbgs() << "Recomputing dominators and loops.\n"); MF.getRegInfo().invalidateLiveness(); MF.RenumberBlocks(); getAnalysis<MachineDominatorTree>().runOnMachineFunction(MF); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp index d22dda7546e..5e00755a81f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -70,7 +70,7 @@ private: void WebAssemblyDAGToDAGISel::Select(SDNode *Node) { // If we have a custom node, we already have selected! if (Node->isMachineOpcode()) { - DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); + LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n"); Node->setNodeId(-1); return; } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp index adb8f6c7c73..5fb97e38939 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp @@ -55,9 +55,9 @@ FunctionPass *llvm::createWebAssemblyLowerBrUnless() { } bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Lowering br_unless **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Lowering br_unless **********\n" + "********** Function: " + << MF.getName() << '\n'); auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>(); const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp index 53e7688e265..1c65478fe14 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp @@ -66,9 +66,9 @@ FunctionPass *llvm::createWebAssemblyOptimizeLiveIntervals() { } bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n" + "********** Function: " + << MF.getName() << '\n'); MachineRegisterInfo &MRI = MF.getRegInfo(); LiveIntervals &LIS = getAnalysis<LiveIntervals>(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp index aa70c91cb4b..520f94cf06b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp @@ -116,7 +116,7 @@ static bool MaybeRewriteToFallthrough(MachineInstr &MI, MachineBasicBlock &MBB, } bool WebAssemblyPeephole::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Peephole **********\n" << "********** Function: " << MF.getName() << '\n'; }); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp index f61d65b6530..e44e7057e23 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp @@ -71,7 +71,7 @@ static bool HasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) { } bool WebAssemblyPrepareForLiveIntervals::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Prepare For LiveIntervals **********\n" << "********** Function: " << MF.getName() << '\n'; }); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp index 494259b17b0..d69a2793710 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp @@ -74,7 +74,7 @@ static float computeWeight(const MachineRegisterInfo *MRI, } bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Register Coloring **********\n" << "********** Function: " << MF.getName() << '\n'; }); @@ -97,7 +97,7 @@ bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) { SmallVector<LiveInterval *, 0> SortedIntervals; SortedIntervals.reserve(NumVRegs); - DEBUG(dbgs() << "Interesting register intervals:\n"); + LLVM_DEBUG(dbgs() << "Interesting register intervals:\n"); for (unsigned i = 0; i < NumVRegs; ++i) { unsigned VReg = TargetRegisterInfo::index2VirtReg(i); if (MFI.isVRegStackified(VReg)) @@ -109,10 +109,10 @@ bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) { LiveInterval *LI = &Liveness->getInterval(VReg); assert(LI->weight == 0.0f); LI->weight = computeWeight(MRI, MBFI, VReg); - DEBUG(LI->dump()); + LLVM_DEBUG(LI->dump()); SortedIntervals.push_back(LI); } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); // Sort them to put arguments first (since we don't want to rename live-in // registers), by weight next, and then by position. @@ -129,7 +129,7 @@ bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) { return *LHS < *RHS; }); - DEBUG(dbgs() << "Coloring register intervals:\n"); + LLVM_DEBUG(dbgs() << "Coloring register intervals:\n"); SmallVector<unsigned, 16> SlotMapping(SortedIntervals.size(), -1u); SmallVector<SmallVector<LiveInterval *, 4>, 16> Assignments( SortedIntervals.size()); @@ -159,9 +159,9 @@ bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) { Changed |= Old != New; UsedColors.set(Color); Assignments[Color].push_back(LI); - DEBUG(dbgs() << "Assigning vreg" - << TargetRegisterInfo::virtReg2Index(LI->reg) << " to vreg" - << TargetRegisterInfo::virtReg2Index(New) << "\n"); + LLVM_DEBUG( + dbgs() << "Assigning vreg" << TargetRegisterInfo::virtReg2Index(LI->reg) + << " to vreg" << TargetRegisterInfo::virtReg2Index(New) << "\n"); } if (!Changed) return false; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp index 7f518ac9868..1e2a248f097 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp @@ -60,9 +60,9 @@ FunctionPass *llvm::createWebAssemblyRegNumbering() { } bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Register Numbering **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Register Numbering **********\n" + "********** Function: " + << MF.getName() << '\n'); WebAssemblyFunctionInfo &MFI = *MF.getInfo<WebAssemblyFunctionInfo>(); MachineRegisterInfo &MRI = MF.getRegInfo(); @@ -77,8 +77,8 @@ bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) { break; int64_t Imm = MI.getOperand(1).getImm(); - DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg() << " -> WAReg " - << Imm << "\n"); + LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg() + << " -> WAReg " << Imm << "\n"); MFI.setWAReg(MI.getOperand(0).getReg(), Imm); } @@ -96,13 +96,13 @@ bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) { continue; // Handle stackified registers. if (MFI.isVRegStackified(VReg)) { - DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " - << (INT32_MIN | NumStackRegs) << "\n"); + LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " + << (INT32_MIN | NumStackRegs) << "\n"); MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++); continue; } if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg) { - DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n"); + LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n"); MFI.setWAReg(VReg, CurReg++); } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index c326bdb8a7b..0b71edae3ce 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -473,7 +473,7 @@ static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI) { - DEBUG(dbgs() << "Move for single use: "; Def->dump()); + LLVM_DEBUG(dbgs() << "Move for single use: "; Def->dump()); MBB.splice(Insert, &MBB, Def); LIS.handleMove(*Def); @@ -500,7 +500,7 @@ static MachineInstr *MoveForSingleUse(unsigned Reg, MachineOperand& Op, MFI.stackifyVReg(NewReg); - DEBUG(dbgs() << " - Replaced register: "; Def->dump()); + LLVM_DEBUG(dbgs() << " - Replaced register: "; Def->dump()); } ImposeStackOrdering(Def); @@ -514,8 +514,8 @@ static MachineInstr *RematerializeCheapDef( MachineBasicBlock::instr_iterator Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII, const WebAssemblyRegisterInfo *TRI) { - DEBUG(dbgs() << "Rematerializing cheap def: "; Def.dump()); - DEBUG(dbgs() << " - for use in "; Op.getParent()->dump()); + LLVM_DEBUG(dbgs() << "Rematerializing cheap def: "; Def.dump()); + LLVM_DEBUG(dbgs() << " - for use in "; Op.getParent()->dump()); unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI); @@ -526,7 +526,7 @@ static MachineInstr *RematerializeCheapDef( MFI.stackifyVReg(NewReg); ImposeStackOrdering(Clone); - DEBUG(dbgs() << " - Cloned to "; Clone->dump()); + LLVM_DEBUG(dbgs() << " - Cloned to "; Clone->dump()); // Shrink the interval. bool IsDead = MRI.use_empty(Reg); @@ -538,7 +538,7 @@ static MachineInstr *RematerializeCheapDef( // If that was the last use of the original, delete the original. if (IsDead) { - DEBUG(dbgs() << " - Deleting original\n"); + LLVM_DEBUG(dbgs() << " - Deleting original\n"); SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot(); LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx); LIS.removeInterval(Reg); @@ -573,7 +573,7 @@ static MachineInstr *MoveAndTeeForMultiUse( unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) { - DEBUG(dbgs() << "Move and tee for multi-use:"; Def->dump()); + LLVM_DEBUG(dbgs() << "Move and tee for multi-use:"; Def->dump()); // Move Def into place. MBB.splice(Insert, &MBB, Def); @@ -609,8 +609,8 @@ static MachineInstr *MoveAndTeeForMultiUse( ImposeStackOrdering(Def); ImposeStackOrdering(Tee); - DEBUG(dbgs() << " - Replaced register: "; Def->dump()); - DEBUG(dbgs() << " - Tee instruction: "; Tee->dump()); + LLVM_DEBUG(dbgs() << " - Replaced register: "; Def->dump()); + LLVM_DEBUG(dbgs() << " - Tee instruction: "; Tee->dump()); return Def; } @@ -737,9 +737,9 @@ public: } // end anonymous namespace bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Register Stackifying **********\n" - "********** Function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** Register Stackifying **********\n" + "********** Function: " + << MF.getName() << '\n'); bool Changed = false; MachineRegisterInfo &MRI = MF.getRegInfo(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp index f66081174e9..f432b367d15 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp @@ -62,7 +62,7 @@ FunctionPass *llvm::createWebAssemblyReplacePhysRegs() { } bool WebAssemblyReplacePhysRegs::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Replace Physical Registers **********\n" << "********** Function: " << MF.getName() << '\n'; }); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp index ac53151047f..93c109f9390 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp @@ -76,7 +76,7 @@ static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) { } bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Set p2align Operands **********\n" << "********** Function: " << MF.getName() << '\n'; }); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp index f1c700f9e8f..893e8484c4c 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp @@ -111,8 +111,8 @@ static bool ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI, continue; Changed = true; - DEBUG(dbgs() << "Setting operand " << O << " in " << *Where << " from " - << MI << "\n"); + LLVM_DEBUG(dbgs() << "Setting operand " << O << " in " << *Where << " from " + << MI << "\n"); O.setReg(ToReg); // If the store's def was previously dead, it is no longer. @@ -170,7 +170,7 @@ static bool optimizeCall(MachineBasicBlock &MBB, MachineInstr &MI, } bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "********** Store Results **********\n" << "********** Function: " << MF.getName() << '\n'; }); @@ -189,7 +189,7 @@ bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) { assert(MRI.tracksLiveness() && "StoreResults expects liveness tracking"); for (auto &MBB : MF) { - DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n'); for (auto &MI : MBB) switch (MI.getOpcode()) { default: diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index b3c491b3de5..bac9d02d69c 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -103,7 +103,7 @@ StringRef llvm::X86Disassembler::GetInstrName(unsigned Opcode, return MII->getName(Opcode); } -#define debug(s) DEBUG(Debug(__FILE__, __LINE__, s)); +#define debug(s) LLVM_DEBUG(Debug(__FILE__, __LINE__, s)); namespace llvm { diff --git a/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp b/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp index e89dd497259..53fc9754590 100644 --- a/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp +++ b/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp @@ -407,7 +407,7 @@ void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size)); if (LoadBase.isReg()) getBaseOperand(NewLoad).setIsKill(false); - DEBUG(NewLoad->dump()); + LLVM_DEBUG(NewLoad->dump()); // If the load and store are consecutive, use the loadInst location to // reduce register pressure. MachineInstr *StInst = StoreInst; @@ -428,7 +428,7 @@ void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands); assert(StoreSrcVReg.isReg() && "Expected virtual register"); NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill()); - DEBUG(NewStore->dump()); + LLVM_DEBUG(NewStore->dump()); } void X86AvoidSFBPass::buildCopies(int Size, MachineInstr *LoadInst, @@ -674,7 +674,7 @@ bool X86AvoidSFBPass::runOnMachineFunction(MachineFunction &MF) { TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo(); AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); - DEBUG(dbgs() << "Start X86AvoidStoreForwardBlocks\n";); + LLVM_DEBUG(dbgs() << "Start X86AvoidStoreForwardBlocks\n";); // Look for a load then a store to XMM/YMM which look like a memcpy findPotentiallylBlockedCopies(MF); @@ -711,10 +711,10 @@ bool X86AvoidSFBPass::runOnMachineFunction(MachineFunction &MF) { // into smaller copies such that each smaller store that was causing // a store block would now be copied separately. MachineInstr *StoreInst = LoadStoreInstPair.second; - DEBUG(dbgs() << "Blocked load and store instructions: \n"); - DEBUG(LoadInst->dump()); - DEBUG(StoreInst->dump()); - DEBUG(dbgs() << "Replaced with:\n"); + LLVM_DEBUG(dbgs() << "Blocked load and store instructions: \n"); + LLVM_DEBUG(LoadInst->dump()); + LLVM_DEBUG(StoreInst->dump()); + LLVM_DEBUG(dbgs() << "Replaced with:\n"); removeRedundantBlockingStores(BlockingStoresDispSizeMap); breakBlockedCopies(LoadInst, StoreInst, BlockingStoresDispSizeMap); updateKillStatus(LoadInst, StoreInst); @@ -726,7 +726,7 @@ bool X86AvoidSFBPass::runOnMachineFunction(MachineFunction &MF) { } ForRemoval.clear(); BlockedLoadsStoresPairs.clear(); - DEBUG(dbgs() << "End X86AvoidStoreForwardBlocks\n";); + LLVM_DEBUG(dbgs() << "End X86AvoidStoreForwardBlocks\n";); return Changed; } diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp index 38baa90f479..f73455cc31b 100644 --- a/llvm/lib/Target/X86/X86CmovConversion.cpp +++ b/llvm/lib/Target/X86/X86CmovConversion.cpp @@ -169,8 +169,8 @@ bool X86CmovConverterPass::runOnMachineFunction(MachineFunction &MF) { if (!EnableCmovConverter) return false; - DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() - << "**********\n"); + LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() + << "**********\n"); bool Changed = false; MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); @@ -776,7 +776,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches( auto *NewCMOV = NewMIs.pop_back_val(); assert(X86::getCondFromCMovOpc(NewCMOV->getOpcode()) == OppCC && "Last new instruction isn't the expected CMOV!"); - DEBUG(dbgs() << "\tRewritten cmov: "; NewCMOV->dump()); + LLVM_DEBUG(dbgs() << "\tRewritten cmov: "; NewCMOV->dump()); MBB->insert(MachineBasicBlock::iterator(MI), NewCMOV); if (&*MIItBegin == &MI) MIItBegin = MachineBasicBlock::iterator(NewCMOV); @@ -784,7 +784,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches( // Sink whatever instructions were needed to produce the unfolded operand // into the false block. for (auto *NewMI : NewMIs) { - DEBUG(dbgs() << "\tRewritten load instr: "; NewMI->dump()); + LLVM_DEBUG(dbgs() << "\tRewritten load instr: "; NewMI->dump()); FalseMBB->insert(FalseInsertionPoint, NewMI); // Re-map any operands that are from other cmovs to the inputs for this block. for (auto &MOp : NewMI->uses()) { @@ -846,8 +846,8 @@ void X86CmovConverterPass::convertCmovInstsToBranches( .addReg(Op2Reg) .addMBB(MBB); (void)MIB; - DEBUG(dbgs() << "\tFrom: "; MIIt->dump()); - DEBUG(dbgs() << "\tTo: "; MIB->dump()); + LLVM_DEBUG(dbgs() << "\tFrom: "; MIIt->dump()); + LLVM_DEBUG(dbgs() << "\tTo: "; MIB->dump()); // Add this PHI to the rewrite table. RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); diff --git a/llvm/lib/Target/X86/X86DomainReassignment.cpp b/llvm/lib/Target/X86/X86DomainReassignment.cpp index b41640f7bd7..ef854dcc2a7 100644 --- a/llvm/lib/Target/X86/X86DomainReassignment.cpp +++ b/llvm/lib/Target/X86/X86DomainReassignment.cpp @@ -701,8 +701,9 @@ bool X86DomainReassignment::runOnMachineFunction(MachineFunction &MF) { if (DisableX86DomainReassignment) return false; - DEBUG(dbgs() << "***** Machine Function before Domain Reassignment *****\n"); - DEBUG(MF.print(dbgs())); + LLVM_DEBUG( + dbgs() << "***** Machine Function before Domain Reassignment *****\n"); + LLVM_DEBUG(MF.print(dbgs())); STI = &MF.getSubtarget<X86Subtarget>(); // GPR->K is the only transformation currently supported, bail out early if no @@ -752,8 +753,9 @@ bool X86DomainReassignment::runOnMachineFunction(MachineFunction &MF) { DeleteContainerSeconds(Converters); - DEBUG(dbgs() << "***** Machine Function after Domain Reassignment *****\n"); - DEBUG(MF.print(dbgs())); + LLVM_DEBUG( + dbgs() << "***** Machine Function after Domain Reassignment *****\n"); + LLVM_DEBUG(MF.print(dbgs())); return Changed; } diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp index 46f13821bae..d9bf60c2c9f 100644 --- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp +++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp @@ -155,13 +155,13 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) { MLI = &getAnalysis<MachineLoopInfo>(); LiveRegs.init(TII->getRegisterInfo()); - DEBUG(dbgs() << "Start X86FixupBWInsts\n";); + LLVM_DEBUG(dbgs() << "Start X86FixupBWInsts\n";); // Process all basic blocks. for (auto &MBB : MF) processBasicBlock(MF, MBB); - DEBUG(dbgs() << "End X86FixupBWInsts\n";); + LLVM_DEBUG(dbgs() << "End X86FixupBWInsts\n";); return true; } diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index df8c8340a61..157b07d819b 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -206,11 +206,11 @@ bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) { TSM.init(&Func.getSubtarget()); TII = ST.getInstrInfo(); - DEBUG(dbgs() << "Start X86FixupLEAs\n";); + LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";); // Process all basic blocks. for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I) processBasicBlock(Func, I); - DEBUG(dbgs() << "End X86FixupLEAs\n";); + LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";); return true; } @@ -408,9 +408,9 @@ void FixupLEAPass::seekLEAFixup(MachineOperand &p, MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI); if (NewMI) { ++NumLEAs; - DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump();); + LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump();); // now to replace with an equivalent LEA... - DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump();); + LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump();); MFI->erase(MBI); MachineBasicBlock::iterator J = static_cast<MachineBasicBlock::iterator>(NewMI); @@ -435,8 +435,8 @@ void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I, return; if (MI.getOperand(2).getImm() > 1) return; - DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump();); - DEBUG(dbgs() << "FixLEA: Replaced by: ";); + LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump();); + LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";); MachineInstr *NewMI = nullptr; // Make ADD instruction for two registers writing to LEA's destination if (SrcR1 != 0 && SrcR2 != 0) { @@ -444,7 +444,7 @@ void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I, const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1); NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); } // Make ADD instruction for immediate if (MI.getOperand(4).getImm() != 0) { @@ -454,7 +454,7 @@ void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I, NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR) .add(SrcR) .addImm(MI.getOperand(4).getImm()); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); } if (NewMI) { MFI->erase(I); @@ -504,8 +504,8 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode)); const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset)); - DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump();); - DEBUG(dbgs() << "FixLEA: Replaced by: ";); + LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump();); + LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";); // First try to replace LEA with one or two (for the 3-op LEA case) // add instructions: @@ -515,11 +515,11 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, const MachineOperand &Src = DstR == BaseR ? Index : Base; MachineInstr *NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); // Create ADD instruction for the Offset in case of 3-Ops LEA. if (hasLEAOffset(Offset)) { NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); } return NewMI; } @@ -535,11 +535,11 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, .add(IsInefficientBase ? Base : Index) .addImm(0) .add(Segment); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); // Create ADD instruction for the Offset in case of 3-Ops LEA. if (hasLEAOffset(Offset)) { NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); } return NewMI; } @@ -551,11 +551,11 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, if (IsScale1 && !hasLEAOffset(Offset)) { bool BIK = Base.isKill() && BaseR != IndexR; TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK); - DEBUG(MI.getPrevNode()->dump();); + LLVM_DEBUG(MI.getPrevNode()->dump();); MachineInstr *NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); return NewMI; } // lea offset(%base,%index,scale), %dst => @@ -567,10 +567,10 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, .add(Index) .add(Offset) .add(Segment); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base); - DEBUG(NewMI->dump();); + LLVM_DEBUG(NewMI->dump();); return NewMI; } diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp index e31a47c5224..c18739254b0 100644 --- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -338,8 +338,8 @@ static MachineBasicBlock &splitBlock(MachineBasicBlock &MBB, } bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() - << " **********\n"); + LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() + << " **********\n"); auto &Subtarget = MF.getSubtarget<X86Subtarget>(); MRI = &MF.getRegInfo(); @@ -381,8 +381,9 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { // instructions. Until we have a motivating test case and fail to avoid // it by changing other parts of LLVM's lowering, we refuse to handle // this complex case here. - DEBUG(dbgs() << "ERROR: Encountered unexpected def of an eflags copy: "; - CopyDefI.dump()); + LLVM_DEBUG( + dbgs() << "ERROR: Encountered unexpected def of an eflags copy: "; + CopyDefI.dump()); report_fatal_error( "Cannot lower EFLAGS copy unless it is defined in turn by a copy!"); } @@ -406,7 +407,7 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { auto TestPos = CopyDefI.getIterator(); DebugLoc TestLoc = CopyDefI.getDebugLoc(); - DEBUG(dbgs() << "Rewriting copy: "; CopyI->dump()); + LLVM_DEBUG(dbgs() << "Rewriting copy: "; CopyI->dump()); // Scan for usage of newly set EFLAGS so we can rewrite them. We just buffer // jumps because their usage is very constrained. @@ -443,7 +444,7 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { // other lowering transformation could induce this to happen, we do // a hard check even in non-debug builds here. if (&TestMBB != &UseMBB && !MDT->dominates(&TestMBB, &UseMBB)) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "ERROR: Encountered use that is not dominated by our test " "basic block! Rewriting this would require inserting PHI " "nodes to track the flag state across the CFG.\n\nTest " @@ -477,7 +478,7 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { continue; } - DEBUG(dbgs() << " Rewriting use: "; MI.dump()); + LLVM_DEBUG(dbgs() << " Rewriting use: "; MI.dump()); // Check the kill flag before we rewrite as that may change it. if (FlagUse->isKill()) @@ -570,7 +571,8 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { if (MI.getOpcode() == TargetOpcode::COPY && (MI.getOperand(0).getReg() == X86::EFLAGS || MI.getOperand(1).getReg() == X86::EFLAGS)) { - DEBUG(dbgs() << "ERROR: Found a COPY involving EFLAGS: "; MI.dump()); + LLVM_DEBUG(dbgs() << "ERROR: Found a COPY involving EFLAGS: "; + MI.dump()); llvm_unreachable("Unlowered EFLAGS copy!"); } #endif @@ -608,7 +610,7 @@ unsigned X86FlagsCopyLoweringPass::promoteCondToReg( auto SetI = BuildMI(TestMBB, TestPos, TestLoc, TII->get(X86::getSETFromCond(Cond)), Reg); (void)SetI; - DEBUG(dbgs() << " save cond: "; SetI->dump()); + LLVM_DEBUG(dbgs() << " save cond: "; SetI->dump()); ++NumSetCCsInserted; return Reg; } @@ -633,7 +635,7 @@ void X86FlagsCopyLoweringPass::insertTest(MachineBasicBlock &MBB, auto TestI = BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg); (void)TestI; - DEBUG(dbgs() << " test cond: "; TestI->dump()); + LLVM_DEBUG(dbgs() << " test cond: "; TestI->dump()); ++NumTestsInserted; } @@ -685,7 +687,7 @@ void X86FlagsCopyLoweringPass::rewriteArithmetic( .addReg(CondReg) .addImm(Addend); (void)AddI; - DEBUG(dbgs() << " add cond: "; AddI->dump()); + LLVM_DEBUG(dbgs() << " add cond: "; AddI->dump()); ++NumAddsInserted; FlagUse.setIsKill(true); } @@ -715,7 +717,7 @@ void X86FlagsCopyLoweringPass::rewriteCMov(MachineBasicBlock &TestMBB, Inverted ? X86::COND_E : X86::COND_NE, TRI->getRegSizeInBits(CMovRC) / 8, !CMovI.memoperands_empty()))); FlagUse.setIsKill(true); - DEBUG(dbgs() << " fixed cmov: "; CMovI.dump()); + LLVM_DEBUG(dbgs() << " fixed cmov: "; CMovI.dump()); } void X86FlagsCopyLoweringPass::rewriteCondJmp( @@ -739,7 +741,7 @@ void X86FlagsCopyLoweringPass::rewriteCondJmp( X86::GetCondBranchFromCond(Inverted ? X86::COND_E : X86::COND_NE))); const int ImplicitEFLAGSOpIdx = 1; JmpI.getOperand(ImplicitEFLAGSOpIdx).setIsKill(true); - DEBUG(dbgs() << " fixed jCC: "; JmpI.dump()); + LLVM_DEBUG(dbgs() << " fixed jCC: "; JmpI.dump()); } void X86FlagsCopyLoweringPass::rewriteCopy(MachineInstr &MI, diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index ffdb949918f..ae748901164 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -435,7 +435,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { PrevMI = &*std::prev(I); ++NumFP; // Keep track of # of pseudo instrs - DEBUG(dbgs() << "\nFPInst:\t" << MI); + LLVM_DEBUG(dbgs() << "\nFPInst:\t" << MI); // Get dead variables list now because the MI pointer may be deleted as part // of processing! @@ -465,13 +465,13 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { // is in the clobber list and marked dead might not be live on the stack. static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers"); if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) { - DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); + LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n"); freeStackSlotAfter(I, Reg-X86::FP0); } } // Print out all of the instructions expanded to if -debug - DEBUG({ + LLVM_DEBUG({ MachineBasicBlock::iterator PrevI = PrevMI; if (I == PrevI) { dbgs() << "Just deleted pseudo instruction\n"; @@ -500,15 +500,15 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { /// setupBlockStack - Use the live bundles to set up our model of the stack /// to match predecessors' live out stack. void FPS::setupBlockStack() { - DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB) - << " derived from " << MBB->getName() << ".\n"); + LLVM_DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB) + << " derived from " << MBB->getName() << ".\n"); StackTop = 0; // Get the live-in bundle for MBB. const LiveBundle &Bundle = LiveBundles[Bundles->getBundle(MBB->getNumber(), false)]; if (!Bundle.Mask) { - DEBUG(dbgs() << "Block has no FP live-ins.\n"); + LLVM_DEBUG(dbgs() << "Block has no FP live-ins.\n"); return; } @@ -517,8 +517,8 @@ void FPS::setupBlockStack() { // Push the fixed live-in registers. for (unsigned i = Bundle.FixCount; i > 0; --i) { - DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %fp" - << unsigned(Bundle.FixStack[i-1]) << '\n'); + LLVM_DEBUG(dbgs() << "Live-in st(" << (i - 1) << "): %fp" + << unsigned(Bundle.FixStack[i - 1]) << '\n'); pushReg(Bundle.FixStack[i-1]); } @@ -527,7 +527,7 @@ void FPS::setupBlockStack() { // to be revived at the end of a short block. It might save a few instrs. unsigned Mask = calcLiveInMask(MBB, /*RemoveFPs=*/true); adjustLiveRegs(Mask, MBB->begin()); - DEBUG(MBB->dump()); + LLVM_DEBUG(MBB->dump()); } /// finishBlockStack - Revive live-outs that are implicitly defined out of @@ -539,8 +539,8 @@ void FPS::finishBlockStack() { if (MBB->succ_empty()) return; - DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB) - << " derived from " << MBB->getName() << ".\n"); + LLVM_DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB) + << " derived from " << MBB->getName() << ".\n"); // Get MBB's live-out bundle. unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true); @@ -552,18 +552,18 @@ void FPS::finishBlockStack() { adjustLiveRegs(Bundle.Mask, Term); if (!Bundle.Mask) { - DEBUG(dbgs() << "No live-outs.\n"); + LLVM_DEBUG(dbgs() << "No live-outs.\n"); return; } // Has the stack order been fixed yet? - DEBUG(dbgs() << "LB#" << BundleIdx << ": "); + LLVM_DEBUG(dbgs() << "LB#" << BundleIdx << ": "); if (Bundle.isFixed()) { - DEBUG(dbgs() << "Shuffling stack to match.\n"); + LLVM_DEBUG(dbgs() << "Shuffling stack to match.\n"); shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term); } else { // Not fixed yet, we get to choose. - DEBUG(dbgs() << "Fixing stack order now.\n"); + LLVM_DEBUG(dbgs() << "Fixing stack order now.\n"); Bundle.FixCount = StackTop; for (unsigned i = 0; i < StackTop; ++i) Bundle.FixStack[i] = getStackEntry(i); @@ -895,7 +895,8 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { while (Kills && Defs) { unsigned KReg = countTrailingZeros(Kills); unsigned DReg = countTrailingZeros(Defs); - DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg << "\n"); + LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg + << "\n"); std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); std::swap(RegMap[KReg], RegMap[DReg]); Kills &= ~(1 << KReg); @@ -909,7 +910,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { unsigned KReg = getStackEntry(0); if (!(Kills & (1 << KReg))) break; - DEBUG(dbgs() << "Popping %fp" << KReg << "\n"); + LLVM_DEBUG(dbgs() << "Popping %fp" << KReg << "\n"); popStackAfter(I2); Kills &= ~(1 << KReg); } @@ -918,7 +919,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { // Manually kill the rest. while (Kills) { unsigned KReg = countTrailingZeros(Kills); - DEBUG(dbgs() << "Killing %fp" << KReg << "\n"); + LLVM_DEBUG(dbgs() << "Killing %fp" << KReg << "\n"); freeStackSlotBefore(I, KReg); Kills &= ~(1 << KReg); } @@ -926,14 +927,14 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { // Load zeros for all the imp-defs. while(Defs) { unsigned DReg = countTrailingZeros(Defs); - DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); + LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); pushReg(DReg); Defs &= ~(1 << DReg); } // Now we should have the correct registers live. - DEBUG(dumpStack()); + LLVM_DEBUG(dumpStack()); assert(StackTop == countPopulation(Mask) && "Live count mismatch"); } @@ -956,7 +957,7 @@ void FPS::shuffleStackTop(const unsigned char *FixStack, if (FixCount > 0) moveToTop(OldReg, I); } - DEBUG(dumpStack()); + LLVM_DEBUG(dumpStack()); } @@ -1468,7 +1469,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { case TargetOpcode::IMPLICIT_DEF: { // All FP registers must be explicitly defined, so load a 0 instead. unsigned Reg = MI.getOperand(0).getReg() - X86::FP0; - DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n'); + LLVM_DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n'); BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0)); pushReg(Reg); break; @@ -1573,8 +1574,9 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { MI.emitError("implicitly popped regs must be last on the x87 stack"); unsigned NumSTPopped = countTrailingOnes(STPopped); - DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " - << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n"); + LLVM_DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " + << NumSTPopped << ", and defines " << NumSTDefs + << " regs.\n"); #ifndef NDEBUG // If any input operand uses constraint "f", all output register @@ -1612,7 +1614,10 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { STUsesArray[I] = I; shuffleStackTop(STUsesArray, NumSTUses, Inst); - DEBUG({dbgs() << "Before asm: "; dumpStack();}); + LLVM_DEBUG({ + dbgs() << "Before asm: "; + dumpStack(); + }); // With the stack layout fixed, rewrite the FP registers. for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { @@ -1660,7 +1665,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { // We want to leave I pointing to the previous instruction, but what if we // just erased the first instruction? if (Inst == MBB->begin()) { - DEBUG(dbgs() << "Inserting dummy KILL\n"); + LLVM_DEBUG(dbgs() << "Inserting dummy KILL\n"); Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL)); } else --Inst; diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 73455912d2c..c041d0212b0 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1308,10 +1308,10 @@ static bool foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM, unsigned Depth) { SDLoc dl(N); - DEBUG({ - dbgs() << "MatchAddress: "; - AM.dump(CurDAG); - }); + LLVM_DEBUG({ + dbgs() << "MatchAddress: "; + AM.dump(CurDAG); + }); // Limit recursion. if (Depth > 5) return matchAddressBase(N, AM); @@ -2744,7 +2744,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) { SDLoc dl(Node); if (Node->isMachineOpcode()) { - DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); Node->setNodeId(-1); return; // Already selected. } @@ -3025,7 +3025,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) { InFlag = ResLo.getValue(2); } ReplaceUses(SDValue(Node, 0), ResLo); - DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); + dbgs() << '\n'); } // Copy the high half of the result, if it is needed. if (!SDValue(Node, 1).use_empty()) { @@ -3036,7 +3037,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) { InFlag = ResHi.getValue(2); } ReplaceUses(SDValue(Node, 1), ResHi); - DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); + dbgs() << '\n'); } CurDAG->RemoveDeadNode(Node); @@ -3198,7 +3200,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) { CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result); } ReplaceUses(SDValue(Node, 1), Result); - DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); + dbgs() << '\n'); } // Copy the division (low) result, if it is needed. if (!SDValue(Node, 0).use_empty()) { @@ -3206,7 +3209,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) { LoReg, NVT, InFlag); InFlag = Result.getValue(2); ReplaceUses(SDValue(Node, 0), Result); - DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); + dbgs() << '\n'); } // Copy the remainder (high) result, if it is needed. if (!SDValue(Node, 1).use_empty()) { @@ -3214,7 +3218,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) { HiReg, NVT, InFlag); InFlag = Result.getValue(2); ReplaceUses(SDValue(Node, 1), Result); - DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); + dbgs() << '\n'); } CurDAG->RemoveDeadNode(Node); return; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 31ce4bdc767..fe86cf0e8ff 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6847,8 +6847,8 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, report_fatal_error("Unable to copy EFLAGS physical register!"); } - DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) - << " to " << RI.getName(DestReg) << '\n'); + LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to " + << RI.getName(DestReg) << '\n'); llvm_unreachable("Cannot emit physreg copy instruction"); } diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index 4996288a193..36d36cb11d7 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -296,8 +296,8 @@ bool X86InstructionSelector::selectCopy(MachineInstr &I, const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); if (!OldRC || !DstRC->hasSubClassEq(OldRC)) { if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } } @@ -333,7 +333,7 @@ bool X86InstructionSelector::select(MachineInstr &I, if (selectImpl(I, CoverageInfo)) return true; - DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs())); + LLVM_DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs())); // TODO: This should be implemented by tblgen. switch (I.getOpcode()) { @@ -503,7 +503,7 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I, auto &MemOp = **I.memoperands_begin(); if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) { - DEBUG(dbgs() << "Atomic load/store not supported yet\n"); + LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n"); return false; } @@ -675,8 +675,8 @@ bool X86InstructionSelector::selectTurnIntoCOPY( if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } I.setDesc(TII.get(X86::COPY)); @@ -700,8 +700,8 @@ bool X86InstructionSelector::selectTruncOrPtrToInt(MachineInstr &I, const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); if (DstRB.getID() != SrcRB.getID()) { - DEBUG(dbgs() << TII.getName(I.getOpcode()) - << " input/output on different banks\n"); + LLVM_DEBUG(dbgs() << TII.getName(I.getOpcode()) + << " input/output on different banks\n"); return false; } @@ -738,8 +738,8 @@ bool X86InstructionSelector::selectTruncOrPtrToInt(MachineInstr &I, if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << "\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << "\n"); return false; } @@ -792,8 +792,8 @@ bool X86InstructionSelector::selectZext(MachineInstr &I, if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } @@ -894,8 +894,8 @@ bool X86InstructionSelector::selectAnyext(MachineInstr &I, if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } @@ -1111,7 +1111,7 @@ bool X86InstructionSelector::emitExtractSubreg(unsigned DstReg, unsigned SrcReg, if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain G_TRUNC\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain G_TRUNC\n"); return false; } @@ -1148,7 +1148,7 @@ bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg, if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain INSERT_SUBREG\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain INSERT_SUBREG\n"); return false; } @@ -1392,8 +1392,8 @@ bool X86InstructionSelector::selectImplicitDefOrPHI( const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI); if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } } @@ -1544,8 +1544,8 @@ bool X86InstructionSelector::selectSDiv(MachineInstr &I, if (!RBI.constrainGenericRegister(DividentReg, *RegRC, MRI) || !RBI.constrainGenericRegister(DiviserReg, *RegRC, MRI) || !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); + LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); return false; } diff --git a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp index 6329375720b..42db51b3cf0 100644 --- a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp +++ b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp @@ -541,7 +541,7 @@ bool OptimizeLEAPass::removeRedundantAddrCalc(MemOpMap &LEAs) { MRI->clearKillFlags(DefMI->getOperand(0).getReg()); ++NumSubstLEAs; - DEBUG(dbgs() << "OptimizeLEAs: Candidate to replace: "; MI.dump();); + LLVM_DEBUG(dbgs() << "OptimizeLEAs: Candidate to replace: "; MI.dump();); // Change instruction operands. MI.getOperand(MemOpNo + X86::AddrBaseReg) @@ -553,7 +553,7 @@ bool OptimizeLEAPass::removeRedundantAddrCalc(MemOpMap &LEAs) { MI.getOperand(MemOpNo + X86::AddrSegmentReg) .ChangeToRegister(X86::NoRegister, false); - DEBUG(dbgs() << "OptimizeLEAs: Replaced by: "; MI.dump();); + LLVM_DEBUG(dbgs() << "OptimizeLEAs: Replaced by: "; MI.dump();); Changed = true; } @@ -649,7 +649,8 @@ bool OptimizeLEAPass::removeRedundantLEAs(MemOpMap &LEAs) { MRI->clearKillFlags(FirstVReg); ++NumRedundantLEAs; - DEBUG(dbgs() << "OptimizeLEAs: Remove redundant LEA: "; Last.dump();); + LLVM_DEBUG(dbgs() << "OptimizeLEAs: Remove redundant LEA: "; + Last.dump();); // By this moment, all of the Last LEA's uses must be replaced. So we // can freely remove it. diff --git a/llvm/lib/Target/X86/X86RetpolineThunks.cpp b/llvm/lib/Target/X86/X86RetpolineThunks.cpp index f37c3fbc399..250deb3523b 100644 --- a/llvm/lib/Target/X86/X86RetpolineThunks.cpp +++ b/llvm/lib/Target/X86/X86RetpolineThunks.cpp @@ -91,7 +91,7 @@ bool X86RetpolineThunks::doInitialization(Module &M) { } bool X86RetpolineThunks::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << getPassName() << '\n'); + LLVM_DEBUG(dbgs() << getPassName() << '\n'); TM = &MF.getTarget();; STI = &MF.getSubtarget<X86Subtarget>(); diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index a137cb4ed38..963016548f2 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -231,9 +231,9 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { else llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!"); - DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel - << ", 3DNowLevel " << X863DNowLevel - << ", 64bit " << HasX86_64 << "\n"); + LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel + << ", 3DNowLevel " << X863DNowLevel << ", 64bit " + << HasX86_64 << "\n"); assert((!In64BitMode || HasX86_64) && "64-bit code requested on a subtarget that doesn't support it!"); diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp index 224262830b1..f882b760927 100644 --- a/llvm/lib/Target/X86/X86VZeroUpper.cpp +++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp @@ -264,8 +264,8 @@ void VZeroUpperInserter::processBasicBlock(MachineBasicBlock &MBB) { } } - DEBUG(dbgs() << "MBB #" << MBB.getNumber() << " exit state: " - << getBlockExitStateName(CurState) << '\n'); + LLVM_DEBUG(dbgs() << "MBB #" << MBB.getNumber() << " exit state: " + << getBlockExitStateName(CurState) << '\n'); if (CurState == EXITS_DIRTY) for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), @@ -341,8 +341,8 @@ bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) { // successors need to be added to the worklist (if they haven't been // already). if (BBState.ExitState == PASS_THROUGH) { - DEBUG(dbgs() << "MBB #" << MBB.getNumber() - << " was Pass-through, is now Dirty-out.\n"); + LLVM_DEBUG(dbgs() << "MBB #" << MBB.getNumber() + << " was Pass-through, is now Dirty-out.\n"); for (MachineBasicBlock *Succ : MBB.successors()) addDirtySuccessor(*Succ); } diff --git a/llvm/lib/Target/X86/X86WinEHState.cpp b/llvm/lib/Target/X86/X86WinEHState.cpp index 6d6dedc6073..dde9c734f49 100644 --- a/llvm/lib/Target/X86/X86WinEHState.cpp +++ b/llvm/lib/Target/X86/X86WinEHState.cpp @@ -695,10 +695,10 @@ void WinEHStatePass::addStateStores(Function &F, WinEHFuncInfo &FuncInfo) { Worklist.push_back(BB); continue; } - DEBUG(dbgs() << "X86WinEHState: " << BB->getName() - << " InitialState=" << InitialState << '\n'); - DEBUG(dbgs() << "X86WinEHState: " << BB->getName() - << " FinalState=" << FinalState << '\n'); + LLVM_DEBUG(dbgs() << "X86WinEHState: " << BB->getName() + << " InitialState=" << InitialState << '\n'); + LLVM_DEBUG(dbgs() << "X86WinEHState: " << BB->getName() + << " FinalState=" << FinalState << '\n'); InitialStates.insert({BB, InitialState}); FinalStates.insert({BB, FinalState}); } @@ -743,8 +743,8 @@ void WinEHStatePass::addStateStores(Function &F, WinEHFuncInfo &FuncInfo) { continue; int PrevState = getPredState(FinalStates, F, ParentBaseState, BB); - DEBUG(dbgs() << "X86WinEHState: " << BB->getName() - << " PrevState=" << PrevState << '\n'); + LLVM_DEBUG(dbgs() << "X86WinEHState: " << BB->getName() + << " PrevState=" << PrevState << '\n'); for (Instruction &I : *BB) { CallSite CS(&I); diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp index 70376d40a37..1915aaedc35 100644 --- a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -274,14 +274,13 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int StackSize = MF.getFrameInfo().getStackSize(); #ifndef NDEBUG - DEBUG(errs() << "\nFunction : " - << MF.getName() << "\n"); - DEBUG(errs() << "<--------->\n"); - DEBUG(MI.print(errs())); - DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"); - DEBUG(errs() << "FrameOffset : " << Offset << "\n"); - DEBUG(errs() << "StackSize : " << StackSize << "\n"); - #endif + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"); + LLVM_DEBUG(errs() << "<--------->\n"); + LLVM_DEBUG(MI.print(errs())); + LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"); + LLVM_DEBUG(errs() << "FrameOffset : " << Offset << "\n"); + LLVM_DEBUG(errs() << "StackSize : " << StackSize << "\n"); +#endif Offset += StackSize; @@ -299,7 +298,8 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0); assert(Offset%4 == 0 && "Misaligned stack offset"); - DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); + LLVM_DEBUG(errs() << "Offset : " << Offset << "\n" + << "<--------->\n"); Offset/=4; unsigned Reg = MI.getOperand(0).getReg(); |
