diff options
Diffstat (limited to 'llvm/lib/Target')
57 files changed, 193 insertions, 49 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 14daab33ecf..706d0b05e06 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -29,7 +29,7 @@ #include <algorithm> -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "AArch64GenInstrInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index eece389302e..5c693c18c6a 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -25,6 +25,9 @@ using namespace llvm; +// Pin the vtable to this file. +void AArch64Subtarget::anchor() {} + AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS) : AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false), HasCrypto(false), TargetTriple(TT), CPUString(CPU) { diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 57eb187c9d1..bbfd3bc7dfa 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -27,6 +27,7 @@ class StringRef; class GlobalValue; class AArch64Subtarget : public AArch64GenSubtargetInfo { + virtual void anchor(); protected: bool HasFPARMv8; bool HasNEON; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp index dd12e2c08c5..add874c1201 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -37,3 +37,6 @@ AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() { // Exceptions handling ExceptionsType = ExceptionHandling::DwarfCFI; } + +// Pin the vtable to this file. +void AArch64ELFMCAsmInfo::anchor() {} diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h index ae0a674fa83..d1dd285c832 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h @@ -18,9 +18,11 @@ namespace llvm { - struct AArch64ELFMCAsmInfo : public MCAsmInfoELF { - explicit AArch64ELFMCAsmInfo(); - }; +struct AArch64ELFMCAsmInfo : public MCAsmInfoELF { + explicit AArch64ELFMCAsmInfo(); +private: + virtual void anchor(); +}; } // namespace llvm diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index b76ef9671bb..b2dd9d85e52 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -37,7 +37,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "ARMGenInstrInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt index 2b797910e43..ae3c9ebc255 100644 --- a/llvm/lib/Target/Hexagon/CMakeLists.txt +++ b/llvm/lib/Target/Hexagon/CMakeLists.txt @@ -17,6 +17,7 @@ add_llvm_target(HexagonCodeGen HexagonFrameLowering.cpp HexagonHardwareLoops.cpp HexagonFixupHwLoops.cpp + HexagonMachineFunctionInfo.cpp HexagonMachineScheduler.cpp HexagonMCInstLower.cpp HexagonInstrInfo.cpp diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 5af645c7cb6..6b97609415a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -26,7 +26,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #define GET_INSTRMAP_INFO #include "HexagonGenInstrInfo.inc" #include "HexagonGenDFAPacketizer.inc" @@ -55,6 +55,8 @@ const int Hexagon_MEMH_AUTOINC_MIN = -16; const int Hexagon_MEMB_AUTOINC_MAX = 7; const int Hexagon_MEMB_AUTOINC_MIN = -8; +// Pin the vtable to this file. +void HexagonInstrInfo::anchor() {} HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 3c28df438d1..3f45b8b2986 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -26,6 +26,7 @@ namespace llvm { class HexagonInstrInfo : public HexagonGenInstrInfo { + virtual void anchor(); const HexagonRegisterInfo RI; const HexagonSubtarget &Subtarget; typedef unsigned Opcode_t; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp new file mode 100644 index 00000000000..9579c8b6df1 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp @@ -0,0 +1,16 @@ +//= HexagonMachineFunctionInfo.cpp - Hexagon machine function info *- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "HexagonMachineFunctionInfo.h" + +using namespace llvm; + +// pin vtable to this file +void HexagonMachineFunctionInfo::anchor() {} + diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h index bd7b26a6190..a59c8c9dd2a 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -1,4 +1,4 @@ -//=- HexagonMachineFuctionInfo.h - Hexagon machine function info --*- C++ -*-=// +//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -10,6 +10,7 @@ #ifndef HexagonMACHINEFUNCTIONINFO_H #define HexagonMACHINEFUNCTIONINFO_H +#include <map> #include "llvm/CodeGen/MachineFunction.h" namespace llvm { @@ -30,9 +31,8 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo { int VarArgsFrameIndex; bool HasClobberLR; bool HasEHReturn; - std::map<const MachineInstr*, unsigned> PacketInfo; - + virtual void anchor(); public: HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0), diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 07d5ce1d8ab..fca67073ef3 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -86,3 +86,5 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): ModeIEEERndNear = false; } +// Pin the vtable to this file. +void HexagonSubtarget::anchor() {} diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index 76a8fba195f..690bef0d729 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -27,7 +27,7 @@ namespace llvm { class HexagonSubtarget : public HexagonGenSubtargetInfo { - + virtual void anchor(); bool UseMemOps; bool ModeIEEERndNear; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index b9fef0ce4d7..3f9415b94df 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -15,6 +15,9 @@ using namespace llvm; +// Pin the vtable to this file. +void HexagonMCAsmInfo::anchor() {} + HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index b2c1d377a32..bd8cb7637af 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -19,6 +19,7 @@ namespace llvm { class HexagonMCAsmInfo : public MCAsmInfoELF { + virtual void anchor(); public: explicit HexagonMCAsmInfo(StringRef TT); }; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index c8505946dfa..7a0b00ae366 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -22,11 +22,14 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "MSP430GenInstrInfo.inc" using namespace llvm; +// Pin the vtable to this file. +void MSP430InstrInfo::anchor() {} + MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm) : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), RI(tm) {} diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h index d79f99245e7..ad2b8cc7cd4 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -42,6 +42,7 @@ namespace MSP430II { class MSP430InstrInfo : public MSP430GenInstrInfo { const MSP430RegisterInfo RI; + virtual void anchor(); public: explicit MSP430InstrInfo(MSP430TargetMachine &TM); diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 7b04a9a3759..0ebad058475 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -22,11 +22,14 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "MipsGenInstrInfo.inc" using namespace llvm; +// Pin the vtable to this file. +void MipsInstrInfo::anchor() {} + MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr) : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), TM(tm), UncondBrOpc(UncondBr) {} diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index b6480ef3376..d9ac961cd33 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -27,6 +27,7 @@ namespace llvm { class MipsInstrInfo : public MipsGenInstrInfo { + virtual void anchor(); protected: MipsTargetMachine &TM; unsigned UncondBrOpc; diff --git a/llvm/lib/Target/Mips/MipsTargetStreamer.h b/llvm/lib/Target/Mips/MipsTargetStreamer.h index 0037f3f58c1..a3908ce1faa 100644 --- a/llvm/lib/Target/Mips/MipsTargetStreamer.h +++ b/llvm/lib/Target/Mips/MipsTargetStreamer.h @@ -16,7 +16,6 @@ namespace llvm { class MipsTargetStreamer : public MCTargetStreamer { virtual void anchor(); - public: virtual void emitMipsHackELFFlags(unsigned Flags) = 0; virtual void emitMipsHackSTOCG(MCSymbol *Sym, unsigned Val) = 0; diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 7ff43bf2310..6a8be753c87 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -2288,3 +2288,29 @@ void NVPTXTargetLowering::ReplaceNodeResults( return; } } + +// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file. +void NVPTXSection::anchor() {} + +NVPTXTargetObjectFile::~NVPTXTargetObjectFile() { + delete TextSection; + delete DataSection; + delete BSSSection; + delete ReadOnlySection; + + delete StaticCtorSection; + delete StaticDtorSection; + delete LSDASection; + delete EHFrameSection; + delete DwarfAbbrevSection; + delete DwarfInfoSection; + delete DwarfLineSection; + delete DwarfFrameSection; + delete DwarfPubTypesSection; + delete DwarfDebugInlineSection; + delete DwarfStrSection; + delete DwarfLocSection; + delete DwarfARangesSection; + delete DwarfRangesSection; + delete DwarfMacroInfoSection; +} diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp index 1f54d3e6ed3..86ddd381770 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -14,7 +14,7 @@ #include "NVPTX.h" #include "NVPTXInstrInfo.h" #include "NVPTXTargetMachine.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "NVPTXGenInstrInfo.inc" #include "llvm/IR/Function.h" #include "llvm/ADT/STLExtras.h" @@ -24,6 +24,9 @@ using namespace llvm; +// Pin the vtable to this file. +void NVPTXInstrInfo::anchor() {} + // FIXME: Add the subtarget support on this constructor. NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm) : NVPTXGenInstrInfo(), TM(tm), RegInfo(*TM.getSubtargetImpl()) {} diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h index b1972e9b725..600fc5c60a1 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -26,6 +26,7 @@ namespace llvm { class NVPTXInstrInfo : public NVPTXGenInstrInfo { NVPTXTargetMachine &TM; const NVPTXRegisterInfo RegInfo; + virtual void anchor(); public: explicit NVPTXInstrInfo(NVPTXTargetMachine &TM); diff --git a/llvm/lib/Target/NVPTX/NVPTXSection.h b/llvm/lib/Target/NVPTX/NVPTXSection.h index e57ace92e85..f8a692e9b1a 100644 --- a/llvm/lib/Target/NVPTX/NVPTXSection.h +++ b/llvm/lib/Target/NVPTX/NVPTXSection.h @@ -24,10 +24,10 @@ namespace llvm { /// the ASMPrint interface. /// class NVPTXSection : public MCSection { - + virtual void anchor(); public: NVPTXSection(SectionVariant V, SectionKind K) : MCSection(V, K) {} - ~NVPTXSection() {} + virtual ~NVPTXSection() {} /// Override this as NVPTX has its own way of printing switching /// to a section. diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp index c4d0d6e4193..9771a176d8d 100644 --- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp @@ -20,6 +20,9 @@ using namespace llvm; +// Pin the vtable to this file. +void NVPTXSubtarget::anchor() {} + NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0), diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h index 670077daaa6..004be116a96 100644 --- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h +++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h @@ -25,7 +25,7 @@ namespace llvm { class NVPTXSubtarget : public NVPTXGenSubtargetInfo { - + virtual void anchor(); std::string TargetName; NVPTX::DrvInterface drvInterface; bool Is64Bit; diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h b/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h index 1449f52a966..2a7394b79ae 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h @@ -44,28 +44,7 @@ public: DwarfMacroInfoSection = 0; } - ~NVPTXTargetObjectFile() { - delete TextSection; - delete DataSection; - delete BSSSection; - delete ReadOnlySection; - - delete StaticCtorSection; - delete StaticDtorSection; - delete LSDASection; - delete EHFrameSection; - delete DwarfAbbrevSection; - delete DwarfInfoSection; - delete DwarfLineSection; - delete DwarfFrameSection; - delete DwarfPubTypesSection; - delete DwarfDebugInlineSection; - delete DwarfStrSection; - delete DwarfLocSection; - delete DwarfARangesSection; - delete DwarfRangesSection; - delete DwarfMacroInfoSection; - } + virtual ~NVPTXTargetObjectFile(); virtual void Initialize(MCContext &ctx, const TargetMachine &TM) { TargetLoweringObjectFile::Initialize(ctx, TM); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index 5c08de1ccf3..f18d095c6d0 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -37,6 +37,9 @@ using namespace llvm; +// Pin the vtable to this file. +PPCTargetStreamer::~PPCTargetStreamer() {} + static MCInstrInfo *createPPCMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitPPCMCInstrInfo(X); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 375daee59e9..87e13ef9eb1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -33,7 +33,7 @@ #include "llvm/Support/raw_ostream.h" #define GET_INSTRMAP_INFO -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "PPCGenInstrInfo.inc" using namespace llvm; @@ -45,6 +45,9 @@ opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden); +// Pin the vtable to this file. +void PPCInstrInfo::anchor() {} + PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl()) {} diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index bd72a4d9e51..f140c41a2a8 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -78,6 +78,7 @@ class PPCInstrInfo : public PPCGenInstrInfo { const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const; + virtual void anchor(); public: explicit PPCInstrInfo(PPCTargetMachine &TM); diff --git a/llvm/lib/Target/PowerPC/PPCTargetStreamer.h b/llvm/lib/Target/PowerPC/PPCTargetStreamer.h index 3ecd8a8b0a4..e876be16a9b 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetStreamer.h +++ b/llvm/lib/Target/PowerPC/PPCTargetStreamer.h @@ -15,6 +15,7 @@ namespace llvm { class PPCTargetStreamer : public MCTargetStreamer { public: + virtual ~PPCTargetStreamer(); virtual void emitTCEntry(const MCSymbol &S) = 0; }; } diff --git a/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp b/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp index 1b2e131fb9c..4f7084b9202 100644 --- a/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -20,13 +20,17 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #define GET_INSTRINFO_NAMED_OPS #define GET_INSTRMAP_INFO #include "AMDGPUGenInstrInfo.inc" using namespace llvm; + +// Pin the vtable to this file. +void AMDGPUInstrInfo::anchor() {} + AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { } diff --git a/llvm/lib/Target/R600/AMDGPUInstrInfo.h b/llvm/lib/Target/R600/AMDGPUInstrInfo.h index 6378fdd1eb4..ce5b58c6923 100644 --- a/llvm/lib/Target/R600/AMDGPUInstrInfo.h +++ b/llvm/lib/Target/R600/AMDGPUInstrInfo.h @@ -43,6 +43,7 @@ private: const AMDGPURegisterInfo RI; bool getNextBranchInstr(MachineBasicBlock::iterator &iter, MachineBasicBlock &MBB) const; + virtual void anchor(); protected: TargetMachine &TM; public: diff --git a/llvm/lib/Target/R600/AMDGPUMachineFunction.cpp b/llvm/lib/Target/R600/AMDGPUMachineFunction.cpp index f2342b0e885..14171f46020 100644 --- a/llvm/lib/Target/R600/AMDGPUMachineFunction.cpp +++ b/llvm/lib/Target/R600/AMDGPUMachineFunction.cpp @@ -6,6 +6,9 @@ using namespace llvm; static const char *const ShaderTypeAttribute = "ShaderType"; +// Pin the vtable to this file. +void AMDGPUMachineFunction::anchor() {} + AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) : MachineFunctionInfo() { ShaderType = ShaderType::COMPUTE; diff --git a/llvm/lib/Target/R600/AMDGPUMachineFunction.h b/llvm/lib/Target/R600/AMDGPUMachineFunction.h index fe80ce3f015..fea0b39e91e 100644 --- a/llvm/lib/Target/R600/AMDGPUMachineFunction.h +++ b/llvm/lib/Target/R600/AMDGPUMachineFunction.h @@ -19,6 +19,7 @@ namespace llvm { class AMDGPUMachineFunction : public MachineFunctionInfo { + virtual void anchor(); public: AMDGPUMachineFunction(const MachineFunction &MF); unsigned ShaderType; diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp new file mode 100644 index 00000000000..521b3b39bba --- /dev/null +++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp @@ -0,0 +1,21 @@ +//===-- AMDGPUCodeEmitter.cpp - AMDGPU Code Emitter interface -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// \file +/// \brief CodeEmitter interface for R600 and SI codegen. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUMCCodeEmitter.h" + +using namespace llvm; + +// pin vtable to this file +void AMDGPUMCCodeEmitter::anchor() {} + diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h index cd3a7ce65aa..d8cf64adb91 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -24,6 +24,7 @@ class MCInst; class MCOperand; class AMDGPUMCCodeEmitter : public MCCodeEmitter { + virtual void anchor(); public: uint64_t getBinaryCodeForInstr(const MCInst &MI, diff --git a/llvm/lib/Target/R600/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/R600/MCTargetDesc/CMakeLists.txt index 3ccdf420601..98f6925d9fb 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/R600/MCTargetDesc/CMakeLists.txt @@ -2,6 +2,7 @@ add_llvm_library(LLVMR600Desc AMDGPUAsmBackend.cpp AMDGPUELFObjectWriter.cpp + AMDGPUMCCodeEmitter.cpp AMDGPUMCTargetDesc.cpp AMDGPUMCAsmInfo.cpp R600MCCodeEmitter.cpp diff --git a/llvm/lib/Target/R600/R600InstrInfo.cpp b/llvm/lib/Target/R600/R600InstrInfo.cpp index 6381c38919a..1f4741634e1 100644 --- a/llvm/lib/Target/R600/R600InstrInfo.cpp +++ b/llvm/lib/Target/R600/R600InstrInfo.cpp @@ -23,7 +23,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "AMDGPUGenDFAPacketizer.inc" using namespace llvm; diff --git a/llvm/lib/Target/R600/R600MachineFunctionInfo.cpp b/llvm/lib/Target/R600/R600MachineFunctionInfo.cpp index 018b4036336..01105c614c5 100644 --- a/llvm/lib/Target/R600/R600MachineFunctionInfo.cpp +++ b/llvm/lib/Target/R600/R600MachineFunctionInfo.cpp @@ -12,7 +12,9 @@ using namespace llvm; -R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF) - : AMDGPUMachineFunction(MF) { } +// Pin the vtable to this file. +void R600MachineFunctionInfo::anchor() {} +R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF) + : AMDGPUMachineFunction(MF) { } diff --git a/llvm/lib/Target/R600/R600MachineFunctionInfo.h b/llvm/lib/Target/R600/R600MachineFunctionInfo.h index f23d9b78b31..c1bec0aae7e 100644 --- a/llvm/lib/Target/R600/R600MachineFunctionInfo.h +++ b/llvm/lib/Target/R600/R600MachineFunctionInfo.h @@ -21,6 +21,7 @@ namespace llvm { class R600MachineFunctionInfo : public AMDGPUMachineFunction { + virtual void anchor(); public: R600MachineFunctionInfo(const MachineFunction &MF); SmallVector<unsigned, 4> LiveOuts; diff --git a/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp b/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp index ee0e30755f0..071f9fa43a1 100644 --- a/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/R600/SIMachineFunctionInfo.cpp @@ -13,6 +13,10 @@ using namespace llvm; + +// Pin the vtable to this file. +void SIMachineFunctionInfo::anchor() {} + SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) : AMDGPUMachineFunction(MF), PSInputAddr(0) { } diff --git a/llvm/lib/Target/R600/SIMachineFunctionInfo.h b/llvm/lib/Target/R600/SIMachineFunctionInfo.h index 6da9f7f9a14..2f1961cafdb 100644 --- a/llvm/lib/Target/R600/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/R600/SIMachineFunctionInfo.h @@ -22,6 +22,7 @@ namespace llvm { /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which /// tells the hardware which interpolation parameters to load. class SIMachineFunctionInfo : public AMDGPUMachineFunction { + virtual void anchor(); public: SIMachineFunctionInfo(const MachineFunction &MF); unsigned PSInputAddr; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 93d7b56501f..c10b5b30051 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -24,11 +24,15 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "SparcGenInstrInfo.inc" using namespace llvm; + +// Pin the vtable to this file. +void SparcInstrInfo::anchor() {} + SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(ST), Subtarget(ST) { diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index d0b220b73d4..a86cbcb1c4b 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -37,6 +37,7 @@ namespace SPII { class SparcInstrInfo : public SparcGenInstrInfo { const SparcRegisterInfo RI; const SparcSubtarget& Subtarget; + virtual void anchor(); public: explicit SparcInstrInfo(SparcSubtarget &ST); diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt index 8a4eaa35e92..d21c0a8086f 100644 --- a/llvm/lib/Target/SystemZ/CMakeLists.txt +++ b/llvm/lib/Target/SystemZ/CMakeLists.txt @@ -21,6 +21,7 @@ add_llvm_target(SystemZCodeGen SystemZISelLowering.cpp SystemZInstrInfo.cpp SystemZLongBranch.cpp + SystemZMachineFunctionInfo.cpp SystemZMCInstLower.cpp SystemZRegisterInfo.cpp SystemZSelectionDAGInfo.cpp diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 2ebbc0d81ae..acfeed80b54 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -17,7 +17,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #define GET_INSTRMAP_INFO #include "SystemZGenInstrInfo.inc" @@ -37,6 +37,9 @@ static bool isHighReg(unsigned int Reg) { return false; } +// Pin the vtable to this file. +void SystemZInstrInfo::anchor() {} + SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP), RI(tm), TM(tm) { diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index 7978be42c90..be4c8fe2add 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -127,6 +127,7 @@ class SystemZInstrInfo : public SystemZGenInstrInfo { void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, unsigned LowLowOpcode, unsigned Size, bool KillSrc) const; + virtual void anchor(); public: explicit SystemZInstrInfo(SystemZTargetMachine &TM); diff --git a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp new file mode 100644 index 00000000000..00572d0b9d7 --- /dev/null +++ b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp @@ -0,0 +1,17 @@ +//== SystemZMachineFuctionInfo.cpp - SystemZ machine function info-*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "SystemZMachineFunctionInfo.h" + +using namespace llvm; + + +// pin vtable to this file +void SystemZMachineFunctionInfo::anchor() {} + diff --git a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h index 69c269137e0..845291f4f3f 100644 --- a/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h @@ -15,6 +15,7 @@ namespace llvm { class SystemZMachineFunctionInfo : public MachineFunctionInfo { + virtual void anchor(); unsigned LowSavedGPR; unsigned HighSavedGPR; unsigned VarArgsFirstGPR; diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index 474192099f2..3971d5e2a5f 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -18,6 +18,9 @@ using namespace llvm; +// Pin the vtabel to this file. +void SystemZSubtarget::anchor() {} + SystemZSubtarget::SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.h b/llvm/lib/Target/SystemZ/SystemZSubtarget.h index 74d3f90ad74..5817491d458 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -26,6 +26,7 @@ class GlobalValue; class StringRef; class SystemZSubtarget : public SystemZGenSubtargetInfo { + virtual void anchor(); protected: bool HasDistinctOps; bool HasLoadStoreOnCond; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp index ed64a32eeff..6da414287cf 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp @@ -27,7 +27,7 @@ namespace { public: X86WinCOFFObjectWriter(bool Is64Bit_); - ~X86WinCOFFObjectWriter(); + virtual ~X86WinCOFFObjectWriter(); virtual unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup, diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 63f699a0072..d0dfb80a77b 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -36,7 +36,7 @@ #include "llvm/Target/TargetOptions.h" #include <limits> -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "X86GenInstrInfo.inc" using namespace llvm; @@ -92,6 +92,9 @@ struct X86OpTblEntry { uint16_t Flags; }; +// Pin the vtable to this file. +void X86InstrInfo::anchor() {} + X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() ? X86::ADJCALLSTACKDOWN64 diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 532e7805ad5..600e3922a71 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -152,6 +152,8 @@ class X86InstrInfo : public X86GenInstrInfo { MemOp2RegOpTableType &M2RTable, unsigned RegOp, unsigned MemOp, unsigned Flags); + virtual void anchor(); + public: explicit X86InstrInfo(X86TargetMachine &tm); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index d6b8c2d5ede..33c7f31be76 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -22,7 +22,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR +#define GET_INSTRINFO_CTOR_DTOR #include "XCoreGenInstrInfo.inc" namespace llvm { @@ -39,6 +39,10 @@ namespace XCore { using namespace llvm; + +// Pin the vtable to this file. +void XCoreInstrInfo::anchor() {} + XCoreInstrInfo::XCoreInstrInfo() : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), RI() { diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 51d66a1f20d..4429b07e41e 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -24,6 +24,7 @@ namespace llvm { class XCoreInstrInfo : public XCoreGenInstrInfo { const XCoreRegisterInfo RI; + virtual void anchor(); public: XCoreInstrInfo(); |
