diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.h | 6 |
2 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index e721a7fd680..c94f9febc50 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -17,6 +17,7 @@ #include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSubtarget.h" +#include "ARMBaseRegisterInfo.h" #include <string> namespace llvm { @@ -129,8 +130,11 @@ protected: /// enablePostRAScheduler - True at 'More' optimization except /// for Thumb1. bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtarget::AntiDepBreakMode& mode) const { - mode = TargetSubtarget::ANTIDEP_CRITICAL; + TargetSubtarget::AntiDepBreakMode& Mode, + ExcludedRCVector& ExcludedRCs) const { + Mode = TargetSubtarget::ANTIDEP_CRITICAL; + ExcludedRCs.clear(); + ExcludedRCs.push_back(&ARM::GPRRegClass); return PostRAScheduler && OptLevel >= CodeGenOpt::Default; } diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 1c8cefa760f..f18def1f6a9 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -219,8 +219,10 @@ public: /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling /// at 'More' optimization level. bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtarget::AntiDepBreakMode& mode) const { - mode = TargetSubtarget::ANTIDEP_CRITICAL; + TargetSubtarget::AntiDepBreakMode& Mode, + ExcludedRCVector& ExcludedRCs) const { + Mode = TargetSubtarget::ANTIDEP_CRITICAL; + ExcludedRCs.clear(); return OptLevel >= CodeGenOpt::Default; } }; |
