diff options
Diffstat (limited to 'llvm/lib/Target')
19 files changed, 119 insertions, 80 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 6e9ca8428bb..c4005fcb1fb 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -329,7 +329,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { ++NumImmRangeRejs; return nullptr; } - // Fall through. + LLVM_FALLTHROUGH; case AArch64::SUBSWrr: case AArch64::SUBSXrr: case AArch64::ADDSWrr: diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 05775a84bef..2236071e5ff 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -7057,7 +7057,7 @@ bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const { // trunc(sext ty1 to ty2) to ty1. if (Instr->getType() == Ext->getOperand(0)->getType()) continue; - // FALL THROUGH. + LLVM_FALLTHROUGH; default: return false; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 8866dcd4ecb..c0ecae849bd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -286,7 +286,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) { if (STM.getGeneration() >= R600Subtarget::EVERGREEN) { // Evergreen / Northern Islands switch (MF.getFunction()->getCallingConv()) { - default: // Fall through + default: LLVM_FALLTHROUGH; case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break; case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break; case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break; @@ -295,9 +295,9 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) { } else { // R600 / R700 switch (MF.getFunction()->getCallingConv()) { - default: // Fall through - case CallingConv::AMDGPU_GS: // Fall through - case CallingConv::AMDGPU_CS: // Fall through + default: LLVM_FALLTHROUGH; + case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH; + case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH; case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break; case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break; } @@ -574,7 +574,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, static unsigned getRsrcReg(CallingConv::ID CallConv) { switch (CallConv) { - default: // Fall through + default: LLVM_FALLTHROUGH; case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1; case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS; case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS; diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 960b711c6de..9b4747b1b08 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1868,6 +1868,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); // Fall through to soft float variant, variadic functions don't // use hard floating point ABI. + LLVM_FALLTHROUGH; case CallingConv::ARM_AAPCS: return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); case CallingConv::ARM_APCS: diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ed126c177e7..cc0b58f9f33 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -8659,7 +8659,7 @@ static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, // (zext cc) can never be the all ones value. if (AllOnes) return false; - // Fall through. + LLVM_FALLTHROUGH; case ISD::SIGN_EXTEND: { SDLoc dl(N); EVT VT = N->getValueType(0); @@ -11409,7 +11409,7 @@ bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL, case 1: if (Subtarget->isThumb1Only()) return false; - // FALL THROUGH. + LLVM_FALLTHROUGH; default: // ARM doesn't support any R+R*scale+imm addr modes. if (AM.BaseOffs) diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 3196a57ccc3..4da28861abd 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1432,7 +1432,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, case ARM::STC_POST: case ARM::STCL_POST: imm |= U << 8; - // fall through. + LLVM_FALLTHROUGH; default: // The 'option' variant doesn't encode 'U' in the immediate since // the immediate is unsigned [0,255]. @@ -2555,6 +2555,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, break; } // Fall through to handle the register offset variant. + LLVM_FALLTHROUGH; case ARM::VLD1d8wb_fixed: case ARM::VLD1d16wb_fixed: case ARM::VLD1d32wb_fixed: @@ -4157,7 +4158,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, case 0x93: // faultmask_ns if (!(FeatureBits[ARM::HasV8MMainlineOps])) return MCDisassembler::Fail; - // fall through + LLVM_FALLTHROUGH; case 10: // msplim case 11: // psplim case 0x88: // msp_ns @@ -5310,4 +5311,3 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, return S; } - diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index 9b600baa273..64c51806b20 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -630,7 +630,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case ARM::fixup_arm_pcrel_10: Value = Value - 4; // ARM fixups offset by an additional word and don't // need to adjust for the half-word ordering. - // Fall through. + LLVM_FALLTHROUGH; case ARM::fixup_t2_pcrel_10: { // Offset by 4, adjusted by two due to the half-word ordering of thumb. Value = Value - 4; @@ -657,7 +657,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case ARM::fixup_arm_pcrel_9: Value = Value - 4; // ARM fixups offset by an additional word and don't // need to adjust for the half-word ordering. - // Fall through. + LLVM_FALLTHROUGH; case ARM::fixup_t2_pcrel_9: { // Offset by 4, adjusted by two due to the half-word ordering of thumb. Value = Value - 4; diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp index e67389217e8..efd28350183 100644 --- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -116,8 +116,8 @@ bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { const MachineOperand &A = MI->getOperand(2); if (!A.isImm() || A.getImm() != 0) return false; + LLVM_FALLTHROUGH; } - // Fall through. case Hexagon::A2_tfr: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &SrcOp = MI->getOperand(1); diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index f832ff2db9f..e4e259be139 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -337,6 +337,7 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const { if (V == 0 || V == -1) return 10; // Fall through into A2_combinew. + LLVM_FALLTHROUGH; } case Hexagon::A2_combinew: return 2; diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index e3f0d16d660..0fd56ad8384 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1606,7 +1606,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, case Mips::BBIT1: case Mips::BBIT132: assert(hasCnMips() && "instruction only valid for octeon cpus"); - // Fall through + LLVM_FALLTHROUGH; case Mips::BEQ: case Mips::BNE: diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index e627be0b23d..b975f2719d4 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -2124,7 +2124,7 @@ NVPTXAsmPrinter::lowerConstantForGV(const Constant *CV, bool ProcessingGeneric) // expression properly. This is important for differences between // blockaddress labels. Since the two labels are in the same function, it // is reasonable to treat their delta as a 32-bit value. - // FALL THROUGH. + LLVM_FALLTHROUGH; case Instruction::BitCast: return lowerConstantForGV(CE->getOperand(0), ProcessingGeneric); diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index ecedded3fa0..bf1de7f1293 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -118,19 +118,19 @@ static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) case SPCC::CPCC_A: return SPCC::CPCC_N; case SPCC::CPCC_N: return SPCC::CPCC_A; - case SPCC::CPCC_3: // Fall through - case SPCC::CPCC_2: // Fall through - case SPCC::CPCC_23: // Fall through - case SPCC::CPCC_1: // Fall through - case SPCC::CPCC_13: // Fall through - case SPCC::CPCC_12: // Fall through - case SPCC::CPCC_123: // Fall through - case SPCC::CPCC_0: // Fall through - case SPCC::CPCC_03: // Fall through - case SPCC::CPCC_02: // Fall through - case SPCC::CPCC_023: // Fall through - case SPCC::CPCC_01: // Fall through - case SPCC::CPCC_013: // Fall through + case SPCC::CPCC_3: LLVM_FALLTHROUGH; + case SPCC::CPCC_2: LLVM_FALLTHROUGH; + case SPCC::CPCC_23: LLVM_FALLTHROUGH; + case SPCC::CPCC_1: LLVM_FALLTHROUGH; + case SPCC::CPCC_13: LLVM_FALLTHROUGH; + case SPCC::CPCC_12: LLVM_FALLTHROUGH; + case SPCC::CPCC_123: LLVM_FALLTHROUGH; + case SPCC::CPCC_0: LLVM_FALLTHROUGH; + case SPCC::CPCC_03: LLVM_FALLTHROUGH; + case SPCC::CPCC_02: LLVM_FALLTHROUGH; + case SPCC::CPCC_023: LLVM_FALLTHROUGH; + case SPCC::CPCC_01: LLVM_FALLTHROUGH; + case SPCC::CPCC_013: LLVM_FALLTHROUGH; case SPCC::CPCC_012: // "Opposite" code is not meaningful, as we don't know // what the CoProc condition means here. The cond-code will diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index cd7fcc3070a..c74d396e3aa 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -832,7 +832,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const { RxSBG.Input = N.getOperand(0); return true; } - // Fall through. + LLVM_FALLTHROUGH; case ISD::SIGN_EXTEND: { // Check that the extension bits are don't-care (i.e. are masked out @@ -1265,7 +1265,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) { if (Node->getOperand(1).getOpcode() != ISD::Constant) if (tryRxSBG(Node, SystemZ::RNSBG)) return; - // Fall through. + LLVM_FALLTHROUGH; case ISD::ROTL: case ISD::SHL: case ISD::SRL: diff --git a/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp b/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp index 4657bbbe151..1953e92efde 100644 --- a/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp +++ b/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp @@ -382,7 +382,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VBLENDPDrri: case X86::VBLENDPDYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::BLENDPDrmi: case X86::VBLENDPDrmi: case X86::VBLENDPDYrmi: @@ -398,7 +398,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VBLENDPSrri: case X86::VBLENDPSYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::BLENDPSrmi: case X86::VBLENDPSrmi: case X86::VBLENDPSYrmi: @@ -414,7 +414,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPBLENDWrri: case X86::VPBLENDWYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::PBLENDWrmi: case X86::VPBLENDWrmi: case X86::VPBLENDWYrmi: @@ -429,7 +429,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPBLENDDrri: case X86::VPBLENDDYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::VPBLENDDrmi: case X86::VPBLENDDYrmi: if (MI->getOperand(NumOperands - 1).isImm()) @@ -444,7 +444,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VINSERTPSrr: case X86::VINSERTPSZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::INSERTPSrm: case X86::VINSERTPSrm: case X86::VINSERTPSZrm: @@ -507,7 +507,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_MOVDUP(MOVSLDUP, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_MOVDUP(MOVSLDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); @@ -515,7 +516,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_MOVDUP(MOVSHDUP, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_MOVDUP(MOVSHDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); @@ -523,7 +525,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_MOVDUP(MOVDDUP, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_MOVDUP(MOVDDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); @@ -566,7 +569,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PALIGNR, rri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PALIGNR, rmi) Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -578,7 +582,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PSHUFD, ri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PSHUFD, mi) DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -589,7 +594,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PSHUFHW, ri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PSHUFHW, mi) DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -600,7 +606,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PSHUFLW, ri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PSHUFLW, mi) DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -611,7 +618,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PSHUFWri: Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MMX_PSHUFWmi: DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -622,7 +630,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PSWAPDrr: Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::PSWAPDrm: DestName = getRegName(MI->getOperand(0).getReg()); DecodePSWAPMask(MVT::v2i32, ShuffleMask); @@ -632,7 +641,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKHBWirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHBW, m) case X86::MMX_PUNPCKHBWirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -644,7 +654,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKHWDirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHWD, m) case X86::MMX_PUNPCKHWDirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -656,7 +667,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKHDQirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHDQ, m) case X86::MMX_PUNPCKHDQirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -667,7 +679,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(PUNPCKHQDQ, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHQDQ, m) Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -678,7 +691,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKLBWirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLBW, m) case X86::MMX_PUNPCKLBWirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -690,7 +704,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKLWDirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLWD, m) case X86::MMX_PUNPCKLWDirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -702,7 +717,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKLDQirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLDQ, m) case X86::MMX_PUNPCKLDQirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -713,7 +729,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(PUNPCKLQDQ, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLQDQ, m) Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -723,7 +740,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(SHUFPD, rri) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(SHUFPD, rmi) if (MI->getOperand(NumOperands - 1).isImm()) DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0), @@ -736,7 +754,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(SHUFPS, rri) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(SHUFPS, rmi) if (MI->getOperand(NumOperands - 1).isImm()) DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0), @@ -749,7 +768,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VSHUF(64X2, r) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VSHUF(64X2, m) decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0), MI->getOperand(NumOperands - 1).getImm(), @@ -761,7 +781,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VSHUF(32X4, r) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VSHUF(32X4, m) decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0), MI->getOperand(NumOperands - 1).getImm(), @@ -773,7 +794,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKLPD, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKLPD, m) DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -783,7 +805,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKLPS, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKLPS, m) DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -793,7 +816,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKHPD, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKHPD, m) DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -803,7 +827,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKHPS, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKHPS, m) DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -812,7 +837,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERMILPI(PERMILPS, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERMILPI(PERMILPS, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0), @@ -823,7 +849,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERMILPI(PERMILPD, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERMILPI(PERMILPD, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0), @@ -835,7 +862,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPERM2F128rr: case X86::VPERM2I128rr: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::VPERM2F128rm: case X86::VPERM2I128rm: // For instruction comments purpose, assume the 256-bit vector is v4i64. @@ -849,7 +877,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERM(PERMPD, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERM(PERMPD, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0), @@ -860,7 +889,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERM(PERMQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERM(PERMQ, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0), @@ -874,7 +904,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVSDZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MOVSDrm: case X86::VMOVSDrm: case X86::VMOVSDZrm: @@ -887,7 +918,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVSSZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MOVSSrm: case X86::VMOVSSrm: case X86::VMOVSSZrm: @@ -901,7 +933,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVZPQILo2PQIrr: case X86::VMOVZPQILo2PQIZrr: Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MOVQI2PQIrm: case X86::MOVZQI2PQIrm: case X86::MOVZPQILo2PQIrm: @@ -954,7 +987,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_PMOVZX(PMOVZXBD, r) CASE_PMOVZX(PMOVZXBQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_PMOVZX(PMOVZXBW, m) CASE_PMOVZX(PMOVZXBD, m) CASE_PMOVZX(PMOVZXBQ, m) @@ -965,7 +999,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_PMOVZX(PMOVZXWD, r) CASE_PMOVZX(PMOVZXWQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_PMOVZX(PMOVZXWD, m) CASE_PMOVZX(PMOVZXWQ, m) DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask); @@ -974,7 +1009,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_PMOVZX(PMOVZXDQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_PMOVZX(PMOVZXDQ, m) DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index ada3d99b8e2..f30331f0a11 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -2969,7 +2969,7 @@ bool X86FastISel::fastLowerArguments() { default: llvm_unreachable("Unexpected value type."); case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break; case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break; - case MVT::f32: // fall-through + case MVT::f32: LLVM_FALLTHROUGH; case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break; } unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); @@ -3508,7 +3508,7 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) { unsigned Opc = 0; switch (VT.SimpleTy) { default: llvm_unreachable("Unexpected value type"); - case MVT::i1: VT = MVT::i8; // fall-through + case MVT::i1: VT = MVT::i8; LLVM_FALLTHROUGH; case MVT::i8: Opc = X86::MOV8ri; break; case MVT::i16: Opc = X86::MOV16ri; break; case MVT::i32: Opc = X86::MOV32ri; break; diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index bce0acbd206..e0ec983edac 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1234,7 +1234,7 @@ bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM, case ISD::UMUL_LOHI: // A mul_lohi where we need the low part can be folded as a plain multiply. if (N.getResNo() != 0) break; - // FALL THROUGH + LLVM_FALLTHROUGH; case ISD::MUL: case X86ISD::MUL_IMM: // X*[3,5,9] -> X+X*[2,4,8] diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5c5c0dc1421..d3f61cc129f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15028,7 +15028,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl, if (!Subtarget.hasBMI() || !isAndn || !isLegalAndnType) break; } - // FALL THROUGH + LLVM_FALLTHROUGH; case ISD::SUB: case ISD::OR: case ISD::XOR: @@ -27635,7 +27635,7 @@ static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) { break; assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B && "Invalid use of SETCC_CARRY!"); - // FALL THROUGH + LLVM_FALLTHROUGH; case X86ISD::SETCC: // Set the condition code or opposite one if necessary. CC = X86::CondCode(SetCC.getConstantOperandVal(0)); @@ -32229,7 +32229,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, return std::make_pair(0U, &X86::VR64RegClass); case 'Y': // SSE_REGS if SSE2 allowed if (!Subtarget.hasSSE2()) break; - // FALL THROUGH. + LLVM_FALLTHROUGH; case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed if (!Subtarget.hasSSE1()) break; diff --git a/llvm/lib/Target/X86/X86WinAllocaExpander.cpp b/llvm/lib/Target/X86/X86WinAllocaExpander.cpp index cc82074e685..9f22ca1fd15 100644 --- a/llvm/lib/Target/X86/X86WinAllocaExpander.cpp +++ b/llvm/lib/Target/X86/X86WinAllocaExpander.cpp @@ -225,6 +225,7 @@ void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { break; // Fall through to make any remaining adjustment. + LLVM_FALLTHROUGH; case Sub: assert(Amount > 0); if (Amount == SlotSize) { diff --git a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp index be66e6cb812..ba94ac772b8 100644 --- a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -140,7 +140,7 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || GV->hasCommonLinkage()) OutStreamer->EmitSymbolAttribute(GVSym, MCSA_Weak); - // FALL THROUGH + LLVM_FALLTHROUGH; case GlobalValue::InternalLinkage: case GlobalValue::PrivateLinkage: break; |
