diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 30 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.h | 1 |
2 files changed, 4 insertions, 27 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index b41d1e3e97a..4195b3bf0a4 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -10984,33 +10984,11 @@ bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; } -Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder, - ARM_MB::MemBOpt Domain) const { +static void makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); - - // First, if the target has no DMB, see what fallback we can use. - if (!Subtarget->hasDataBarrier()) { - // Some ARMv6 cpus can support data barriers with an mcr instruction. - // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get - // here. - if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) { - Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr); - ArrayRef<Value*> args = {Builder.getInt32(15), Builder.getInt32(0), - Builder.getInt32(0), Builder.getInt32(7), - Builder.getInt32(10), Builder.getInt32(5)}; - return Builder.CreateCall(MCR, args); - } else { - // Instead of using barriers, atomic accesses on these subtargets use - // libcalls. - llvm_unreachable("makeDMB on a target so old that it has no barriers"); - } - } else { - Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb); - // Only a full system barrier exists in the M-class architectures. - Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; - Constant *CDomain = Builder.getInt32(Domain); - return Builder.CreateCall(DMB, CDomain); - } + Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb); + Constant *CDomain = Builder.getInt32(Domain); + Builder.CreateCall(DMB, CDomain); } // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index d5483553898..aa268f16498 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -393,7 +393,6 @@ namespace llvm { Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; bool hasLoadLinkedStoreConditional() const override; - Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override; Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, |
