diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 36 |
1 files changed, 13 insertions, 23 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b2c463e8525..b757b2448e7 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -194,8 +194,8 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions); - void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, - SmallVectorImpl<MCInst> &Instructions); + void expandLoadAddressSym(const MCOperand &DstRegOp, const MCOperand &SymOp, + SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions); void expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions, bool isLoad, @@ -1869,17 +1869,18 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, bool MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { + const MCOperand &DstRegOp = Inst.getOperand(0); + assert(DstRegOp.isReg() && "expected register operand kind"); + const MCOperand &ImmOp = Inst.getOperand(2); assert((ImmOp.isImm() || ImmOp.isExpr()) && "expected immediate operand kind"); if (!ImmOp.isImm()) { - expandLoadAddressSym(Inst, IDLoc, Instructions); + expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions); return false; } const MCOperand &SrcRegOp = Inst.getOperand(1); assert(SrcRegOp.isReg() && "expected register operand kind"); - const MCOperand &DstRegOp = Inst.getOperand(0); - assert(DstRegOp.isReg() && "expected register operand kind"); if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(), Is32BitImm, IDLoc, Instructions)) @@ -1891,15 +1892,16 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, bool MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { + const MCOperand &DstRegOp = Inst.getOperand(0); + assert(DstRegOp.isReg() && "expected register operand kind"); + const MCOperand &ImmOp = Inst.getOperand(1); assert((ImmOp.isImm() || ImmOp.isExpr()) && "expected immediate operand kind"); if (!ImmOp.isImm()) { - expandLoadAddressSym(Inst, IDLoc, Instructions); + expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions); return false; } - const MCOperand &DstRegOp = Inst.getOperand(0); - assert(DstRegOp.isReg() && "expected register operand kind"); if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, Is32BitImm, IDLoc, Instructions)) @@ -1909,23 +1911,11 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, } void -MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, +MipsAsmParser::expandLoadAddressSym(const MCOperand &DstRegOp, + const MCOperand &SymOp, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { - // FIXME: If we do have a valid at register to use, we should generate a - // slightly shorter sequence here. MCInst tmpInst; - int ExprOperandNo = 1; - // Sometimes the assembly parser will get the immediate expression as - // a $zero + an immediate. - if (Inst.getNumOperands() == 3) { - assert(Inst.getOperand(1).getReg() == - (isGP64bit() ? Mips::ZERO_64 : Mips::ZERO)); - ExprOperandNo = 2; - } - const MCOperand &SymOp = Inst.getOperand(ExprOperandNo); - assert(SymOp.isExpr() && "expected symbol operand kind"); - const MCOperand &RegOp = Inst.getOperand(0); - unsigned RegNo = RegOp.getReg(); + unsigned RegNo = DstRegOp.getReg(); const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr()); const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), |
