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-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp2
-rw-r--r--llvm/lib/Target/Alpha/AlphaISelLowering.h2
-rw-r--r--llvm/lib/Target/Alpha/AlphaRelocations.h2
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp2
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.h4
-rw-r--r--llvm/lib/Target/PowerPC/PPCJITInfo.cpp2
-rw-r--r--llvm/lib/Target/PowerPC/PPCRelocations.h2
-rw-r--r--llvm/lib/Target/Sparc/Sparc.h2
-rw-r--r--llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp2
-rw-r--r--llvm/lib/Target/Sparc/SparcInstrInfo.h2
-rw-r--r--llvm/lib/Target/Sparc/SparcSubtarget.cpp2
-rw-r--r--llvm/lib/Target/TargetMachine.cpp4
-rw-r--r--llvm/lib/Target/X86/X86ISelDAGToDAG.cpp2
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.h2
-rw-r--r--llvm/lib/Target/X86/X86InstrBuilder.h2
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.h2
-rw-r--r--llvm/lib/Target/X86/X86JITInfo.cpp2
-rw-r--r--llvm/lib/Target/X86/X86Relocations.h2
18 files changed, 20 insertions, 20 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 0a489781310..7cf7dd37a4a 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -31,7 +31,7 @@ using namespace llvm;
namespace ARMISD {
enum {
FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
- RET_FLAG,
+ RET_FLAG
};
}
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.h b/llvm/lib/Target/Alpha/AlphaISelLowering.h
index 569fa74a8cf..d6886fcc69e 100644
--- a/llvm/lib/Target/Alpha/AlphaISelLowering.h
+++ b/llvm/lib/Target/Alpha/AlphaISelLowering.h
@@ -42,7 +42,7 @@ namespace llvm {
CALL,
/// DIVCALL - used for special library calls for div and rem
- DivCall,
+ DivCall
};
}
diff --git a/llvm/lib/Target/Alpha/AlphaRelocations.h b/llvm/lib/Target/Alpha/AlphaRelocations.h
index 59b97650858..c532f21f161 100644
--- a/llvm/lib/Target/Alpha/AlphaRelocations.h
+++ b/llvm/lib/Target/Alpha/AlphaRelocations.h
@@ -23,7 +23,7 @@ namespace llvm {
reloc_gprellow,
reloc_gprelhigh,
reloc_gpdist,
- reloc_bsr,
+ reloc_bsr
};
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 1e6c1e5c787..850b4127ac9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1748,7 +1748,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
OP_VSPLTISW3,
OP_VSLDOI4,
OP_VSLDOI8,
- OP_VSLDOI12,
+ OP_VSLDOI12
};
if (OpNum == OP_COPY) {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 857d42b71b2..25551fb6c29 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -44,7 +44,7 @@ enum {
/// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
/// an instruction is issued to.
PPC970_Shift = 3,
- PPC970_Mask = 0x07 << PPC970_Shift,
+ PPC970_Mask = 0x07 << PPC970_Shift
};
enum PPC970_Unit {
/// These are the various PPC970 execution unit pipelines. Each instruction
@@ -56,7 +56,7 @@ enum PPC970_Unit {
PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
- PPC970_BRU = 7 << PPC970_Shift, // Branch Unit
+ PPC970_BRU = 7 << PPC970_Shift // Branch Unit
};
}
diff --git a/llvm/lib/Target/PowerPC/PPCJITInfo.cpp b/llvm/lib/Target/PowerPC/PPCJITInfo.cpp
index a6d630efa2c..6ee10d78b63 100644
--- a/llvm/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -165,7 +165,7 @@ PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
// If this is just a call to an external function, emit a branch instead of a
// call. The code is the same except for one bit of the last instruction.
- if (Fn != PPC32CompilationCallback) {
+ if (Fn != (void*)PPC32CompilationCallback) {
MCE.startFunctionStub(4*4);
void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
MCE.emitWordBE(0);
diff --git a/llvm/lib/Target/PowerPC/PPCRelocations.h b/llvm/lib/Target/PowerPC/PPCRelocations.h
index 77c351980cf..20d747b06d5 100644
--- a/llvm/lib/Target/PowerPC/PPCRelocations.h
+++ b/llvm/lib/Target/PowerPC/PPCRelocations.h
@@ -50,7 +50,7 @@ namespace llvm {
// relocated to point to a POINTER to the indicated global. The low-16
// bits of the instruction are rewritten with the low 16-bits of the
// address of the pointer.
- reloc_absolute_ptr_low,
+ reloc_absolute_ptr_low
};
}
}
diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h
index 084bfe3987f..c2ae18d9c4f 100644
--- a/llvm/lib/Target/Sparc/Sparc.h
+++ b/llvm/lib/Target/Sparc/Sparc.h
@@ -75,7 +75,7 @@ namespace llvm {
FCC_UGE = 12+16, // Unordered or Greater or Equal
FCC_LE = 13+16, // Less or Equal
FCC_ULE = 14+16, // Unordered or Less or Equal
- FCC_O = 15+16, // Ordered
+ FCC_O = 15+16 // Ordered
};
}
diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 123b86aa294..25f6e234a2f 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -48,7 +48,7 @@ namespace SPISD {
ITOF, // Int to FP within a FP register.
CALL, // A call instruction.
- RET_FLAG, // Return with a flag operand.
+ RET_FLAG // Return with a flag operand.
};
}
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h
index 3dd8b8e8b3f..166793e2e04 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.h
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h
@@ -29,7 +29,7 @@ namespace SPII {
Store = (1<<2),
DelaySlot = (1<<3)
};
-};
+}
class SparcInstrInfo : public TargetInstrInfo {
const SparcRegisterInfo RI;
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
index beda79d49b0..9940fcf3b1d 100644
--- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
@@ -40,4 +40,4 @@ SparcSubtarget::SparcSubtarget(const Module &M, const std::string &FS) {
// Unless explicitly enabled, disable the V9 instructions.
if (!EnableV9)
IsV9 = false;
-};
+}
diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index bf70d12a6b8..c9e92fa8540 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -28,7 +28,7 @@ namespace llvm {
bool UnsafeFPMath;
bool FiniteOnlyFPMathOption;
Reloc::Model RelocationModel;
-};
+}
namespace {
cl::opt<bool, true> PrintCode("print-machineinstrs",
cl::desc("Print generated machine code"),
@@ -70,7 +70,7 @@ namespace {
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
-};
+}
//---------------------------------------------------------------------------
// TargetMachine Class
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 50c42ec0406..b53748ab75d 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -47,7 +47,7 @@ namespace {
struct X86ISelAddressMode {
enum {
RegBase,
- FrameIndexBase,
+ FrameIndexBase
} BaseType;
struct { // This is really a union, discriminated by BaseType!
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 9269daf9abf..38aa227c957 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -156,7 +156,7 @@ namespace llvm {
/// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
/// corresponds to X86::PINSRW.
- PINSRW,
+ PINSRW
};
// X86 specific condition code. These correspond to X86_*_COND in
diff --git a/llvm/lib/Target/X86/X86InstrBuilder.h b/llvm/lib/Target/X86/X86InstrBuilder.h
index f3e1c28e4d8..c0fa58debff 100644
--- a/llvm/lib/Target/X86/X86InstrBuilder.h
+++ b/llvm/lib/Target/X86/X86InstrBuilder.h
@@ -35,7 +35,7 @@ namespace llvm {
struct X86AddressMode {
enum {
RegBase,
- FrameIndexBase,
+ FrameIndexBase
} BaseType;
union {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index d6dfae14e6b..b49c351d68f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -162,7 +162,7 @@ namespace X86II {
SpecialFP = 7 << FPTypeShift,
OpcodeShift = 16,
- OpcodeMask = 0xFF << OpcodeShift,
+ OpcodeMask = 0xFF << OpcodeShift
// Bits 25 -> 31 are unused
};
}
diff --git a/llvm/lib/Target/X86/X86JITInfo.cpp b/llvm/lib/Target/X86/X86JITInfo.cpp
index 3d1222128af..6f83651c184 100644
--- a/llvm/lib/Target/X86/X86JITInfo.cpp
+++ b/llvm/lib/Target/X86/X86JITInfo.cpp
@@ -167,7 +167,7 @@ X86JITInfo::getLazyResolverFunction(JITCompilerFn F) {
}
void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
- if (Fn != X86CompilationCallback) {
+ if (Fn != (void*)X86CompilationCallback) {
MCE.startFunctionStub(5);
MCE.emitByte(0xE9);
MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4);
diff --git a/llvm/lib/Target/X86/X86Relocations.h b/llvm/lib/Target/X86/X86Relocations.h
index 7a5f1a68844..bc1efabc7ab 100644
--- a/llvm/lib/Target/X86/X86Relocations.h
+++ b/llvm/lib/Target/X86/X86Relocations.h
@@ -25,7 +25,7 @@ namespace llvm {
// reloc_absolute_word - Absolute relocation, just add the relocated value
// to the value already in memory.
- reloc_absolute_word = 1,
+ reloc_absolute_word = 1
};
}
}
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