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-rw-r--r--llvm/lib/Target/PowerPC/PPC.h2
-rw-r--r--llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp52
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetMachine.cpp2
3 files changed, 19 insertions, 37 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index 23077637388..38ae62b2675 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -44,7 +44,7 @@ namespace llvm {
FunctionPass *createPPCQPXLoadSplatPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCTLSDynamicCallPass();
- FunctionPass *createPPCBoolRetToIntPass(PPCTargetMachine *TM);
+ FunctionPass *createPPCBoolRetToIntPass();
FunctionPass *createPPCExpandISELPass();
void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP, bool isDarwin);
diff --git a/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp b/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
index aa78178e91e..93c201d0386 100644
--- a/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
+++ b/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp
@@ -7,15 +7,15 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements converting i1 values to i32/i64 if they could be more
+// This file implements converting i1 values to i32 if they could be more
// profitably allocated as GPRs rather than CRs. This pass will become totally
// unnecessary if Register Bank Allocation and Global Instruction Selection ever
// go upstream.
//
-// Presently, the pass converts i1 Constants, and Arguments to i32/i64 if the
+// Presently, the pass converts i1 Constants, and Arguments to i32 if the
// transitive closure of their uses includes only PHINodes, CallInsts, and
// ReturnInsts. The rational is that arguments are generally passed and returned
-// in GPRs rather than CRs, so casting them to i32/i64 at the LLVM IR level will
+// in GPRs rather than CRs, so casting them to i32 at the LLVM IR level will
// actually save casts at the Machine Instruction level.
//
// It might be useful to expand this pass to add bit-wise operations to the list
@@ -33,7 +33,6 @@
//===----------------------------------------------------------------------===//
#include "PPC.h"
-#include "PPCTargetMachine.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
@@ -88,19 +87,17 @@ class PPCBoolRetToInt : public FunctionPass {
return Defs;
}
- // Translate a i1 value to an equivalent i32/i64 value:
- Value *translate(Value *V) {
- Type *IntTy = ST->isPPC64() ? Type::getInt64Ty(V->getContext())
- : Type::getInt32Ty(V->getContext());
-
+ // Translate a i1 value to an equivalent i32 value:
+ static Value *translate(Value *V) {
+ Type *Int32Ty = Type::getInt32Ty(V->getContext());
if (auto *C = dyn_cast<Constant>(V))
- return ConstantExpr::getZExt(C, IntTy);
+ return ConstantExpr::getZExt(C, Int32Ty);
if (auto *P = dyn_cast<PHINode>(V)) {
// Temporarily set the operands to 0. We'll fix this later in
// runOnUse.
- Value *Zero = Constant::getNullValue(IntTy);
+ Value *Zero = Constant::getNullValue(Int32Ty);
PHINode *Q =
- PHINode::Create(IntTy, P->getNumIncomingValues(), P->getName(), P);
+ PHINode::Create(Int32Ty, P->getNumIncomingValues(), P->getName(), P);
for (unsigned i = 0; i < P->getNumOperands(); ++i)
Q->addIncoming(Zero, P->getIncomingBlock(i));
return Q;
@@ -112,7 +109,7 @@ class PPCBoolRetToInt : public FunctionPass {
auto InstPt =
A ? &*A->getParent()->getEntryBlock().begin() : I->getNextNode();
- return new ZExtInst(V, IntTy, "", InstPt);
+ return new ZExtInst(V, Int32Ty, "", InstPt);
}
typedef SmallPtrSet<const PHINode *, 8> PHINodeSet;
@@ -180,11 +177,7 @@ class PPCBoolRetToInt : public FunctionPass {
public:
static char ID;
- PPCBoolRetToInt() : FunctionPass(ID), TM(nullptr) {
- initializePPCBoolRetToIntPass(*PassRegistry::getPassRegistry());
- }
-
- PPCBoolRetToInt(TargetMachine *&TM) : FunctionPass(ID), TM(TM) {
+ PPCBoolRetToInt() : FunctionPass(ID) {
initializePPCBoolRetToIntPass(*PassRegistry::getPassRegistry());
}
@@ -192,10 +185,6 @@ class PPCBoolRetToInt : public FunctionPass {
if (skipFunction(F))
return false;
- if (!TM)
- return false;
- ST = ((PPCTargetMachine*)TM)->getSubtargetImpl(F);
-
PHINodeSet PromotablePHINodes = getPromotablePHINodes(F);
B2IMap Bool2IntMap;
bool Changed = false;
@@ -216,7 +205,7 @@ class PPCBoolRetToInt : public FunctionPass {
return Changed;
}
- bool runOnUse(Use &U, const PHINodeSet &PromotablePHINodes,
+ static bool runOnUse(Use &U, const PHINodeSet &PromotablePHINodes,
B2IMap &BoolToIntMap) {
auto Defs = findAllDefs(U);
@@ -273,20 +262,13 @@ class PPCBoolRetToInt : public FunctionPass {
AU.addPreserved<DominatorTreeWrapperPass>();
FunctionPass::getAnalysisUsage(AU);
}
-
-private:
- const PPCSubtarget *ST;
- TargetMachine *TM;
};
} // end anonymous namespace
char PPCBoolRetToInt::ID = 0;
-INITIALIZE_TM_PASS(PPCBoolRetToInt, "bool-ret-to-int",
- "Convert i1 constants to i32/i64 if they are returned",
- false, false)
-
-FunctionPass *llvm::createPPCBoolRetToIntPass(PPCTargetMachine *TM) {
- TargetMachine *pTM = TM;
- return new PPCBoolRetToInt(pTM);
-}
+INITIALIZE_PASS(PPCBoolRetToInt, "bool-ret-to-int",
+ "Convert i1 constants to i32 if they are returned",
+ false, false)
+
+FunctionPass *llvm::createPPCBoolRetToIntPass() { return new PPCBoolRetToInt(); }
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 298f8ec0bbf..5d68f32ccc5 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -323,7 +323,7 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
void PPCPassConfig::addIRPasses() {
if (TM->getOptLevel() != CodeGenOpt::None)
- addPass(createPPCBoolRetToIntPass(&getPPCTargetMachine()));
+ addPass(createPPCBoolRetToIntPass());
addPass(createAtomicExpandPass(&getPPCTargetMachine()));
// For the BG/Q (or if explicitly requested), add explicit data prefetch
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