summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp16
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.td22
-rw-r--r--llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp4
4 files changed, 17 insertions, 29 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 63c96103e3b..749022ddb49 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -404,7 +404,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
dl, PointerTy,
TargAddr);
// Figure out base + offset opcode
- if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
+ if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io;
else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
@@ -597,7 +597,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = Hexagon::POST_LDrid;
else
- Opcode = Hexagon::LDrid;
+ Opcode = Hexagon::L2_loadrd_io;
} else if (LoadedVT == MVT::i32) {
if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = Hexagon::POST_LDriw;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 8e6e0e3f842..01952990bad 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -79,7 +79,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
switch (MI->getOpcode()) {
default: break;
case Hexagon::L2_loadri_io:
- case Hexagon::LDrid:
+ case Hexagon::L2_loadrd_io:
case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadrb_io:
case Hexagon::L2_loadrub_io:
@@ -536,7 +536,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} else if (RC == &Hexagon::DoubleRegsRegClass) {
- BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
+ BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} else if (RC == &Hexagon::PredRegsRegClass) {
BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
@@ -670,8 +670,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::STrib_nv_V4:
return isUInt<6>(MI->getOperand(1).getImm());
- case Hexagon::LDrid:
- case Hexagon::LDrid_indexed:
+ case Hexagon::L2_loadrd_io:
return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
case Hexagon::L2_loadri_io:
@@ -1110,8 +1109,7 @@ isValidOffset(const int Opcode, const int Offset) const {
return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
(Offset <= Hexagon_MEMW_OFFSET_MAX);
- case Hexagon::LDrid:
- case Hexagon::LDrid_indexed:
+ case Hexagon::L2_loadrd_io:
case Hexagon::LDrid_f:
case Hexagon::STrid:
case Hexagon::STrid_indexed:
@@ -1346,10 +1344,8 @@ isConditionalLoad (const MachineInstr* MI) const {
switch (MI->getOpcode())
{
default: return false;
- case Hexagon::LDrid_cPt :
- case Hexagon::LDrid_cNotPt :
- case Hexagon::LDrid_indexed_cPt :
- case Hexagon::LDrid_indexed_cNotPt :
+ case Hexagon::L2_ploadrdt_io :
+ case Hexagon::L2_ploadrdf_io:
case Hexagon::L2_ploadrit_io:
case Hexagon::L2_ploadrif_io:
case Hexagon::L2_ploadrht_io:
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index da8a8e54193..2b2415346b9 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -1555,6 +1555,9 @@ let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
+let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
+defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
+
///
// Load -- MEMri operand
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
@@ -1594,11 +1597,6 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
}
}
-let addrMode = BaseImmOffset, isMEMri = "true" in {
- let accessSize = DoubleWordAccess in
- defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
-}
-
def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
(L2_loadrb_io AddrFI:$addr, 0) >;
@@ -1615,7 +1613,7 @@ def : Pat < (i32 (load ADDRriS11_2:$addr)),
(L2_loadri_io AddrFI:$addr, 0) >;
def : Pat < (i64 (load ADDRriS11_3:$addr)),
- (LDrid ADDRriS11_3:$addr) >;
+ (L2_loadrd_io AddrFI:$addr, 0) >;
// Load - Base with Immediate offset addressing mode
@@ -1658,12 +1656,6 @@ multiclass LD_Idxd2<string mnemonic, string CextOp, RegisterClass RC,
}
}
-let addrMode = BaseImmOffset in {
- let accessSize = DoubleWordAccess in
- defm LDrid_indexed: LD_Idxd2 <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
- 14, 9>, AddrModeRel;
-}
-
let AddedComplexity = 20 in {
def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
(L2_loadrb_io IntRegs:$src1, s11_0ExtPred:$offset) >;
@@ -1681,7 +1673,7 @@ def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
(L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset) >;
def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
- (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
+ (L2_loadrd_io IntRegs:$src1, s11_3ExtPred:$offset) >;
}
//===----------------------------------------------------------------------===//
@@ -3664,10 +3656,10 @@ def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
// 64 bit atomic load
def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
- (i64 (LDrid ADDRriS11_3:$src1))>;
+ (i64 (L2_loadrd_io AddrFI:$src1, 0))>;
def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
- (i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
+ (i64 (L2_loadrd_io (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 43b3883fc4f..1270c6e4e0c 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -160,14 +160,14 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// r0 = add(r30, #10000)
// r0 = memw(r0)
if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||
- (MI.getOpcode() == Hexagon::LDrid) ||
+ (MI.getOpcode() == Hexagon::L2_loadrd_io) ||
(MI.getOpcode() == Hexagon::L2_loadrh_io) ||
(MI.getOpcode() == Hexagon::L2_loadruh_io) ||
(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
(MI.getOpcode() == Hexagon::L2_loadrub_io) ||
(MI.getOpcode() == Hexagon::LDriw_f) ||
(MI.getOpcode() == Hexagon::LDrid_f)) {
- unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
+ unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
MI.getOperand(0).getReg();
OpenPOWER on IntegriCloud