diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 2 |
2 files changed, 9 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 2dbe5e6f397..30edf49f315 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7822,16 +7822,20 @@ def : Pat<(v4i64 (X86VPerm2x128 (loadv4i64 addr:$src2), // VZERO - Zero YMM registers // // Note, these instruction do not affect the YMM16-YMM31. +let SchedRW = [WriteSystem] in { let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in { // Zero All YMM registers def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", - [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>, VEX_WIG; + [(int_x86_avx_vzeroall)], IIC_AVX_ZERO>, PS, VEX, VEX_L, + Requires<[HasAVX]>, VEX_WIG; // Zero Upper bits of YMM registers def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", - [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>, VEX_WIG; -} + [(int_x86_avx_vzeroupper)], IIC_AVX_ZERO>, PS, VEX, + Requires<[HasAVX]>, VEX_WIG; +} // Defs +} // SchedRW //===----------------------------------------------------------------------===// // Half precision conversion instructions diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index bad3b7fc091..5709e1a0307 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -394,6 +394,8 @@ def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass; def IIC_SSE_CVT_SD2SI_RM : InstrItinClass; def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; +def IIC_AVX_ZERO : InstrItinClass; + // MMX def IIC_MMX_MOV_MM_RM : InstrItinClass; def IIC_MMX_MOV_REG_MM : InstrItinClass; |
