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-rw-r--r--llvm/lib/Target/SystemZ/SystemZCallingConv.td9
-rw-r--r--llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp39
-rw-r--r--llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp8
3 files changed, 44 insertions, 12 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZCallingConv.td b/llvm/lib/Target/SystemZ/SystemZCallingConv.td
index 2bf5ac29865..deba27fee7f 100644
--- a/llvm/lib/Target/SystemZ/SystemZCallingConv.td
+++ b/llvm/lib/Target/SystemZ/SystemZCallingConv.td
@@ -120,3 +120,12 @@ def CSR_SystemZ : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
// R9 is used to return SwiftError; remove it from CSR.
def CSR_SystemZ_SwiftError : CalleeSavedRegs<(sub CSR_SystemZ, R9D)>;
+
+// "All registers" as used by the AnyReg calling convention.
+// Note that registers 0 and 1 are still defined as intra-call scratch
+// registers that may be clobbered e.g. by PLT stubs.
+def CSR_SystemZ_AllRegs : CalleeSavedRegs<(add (sequence "R%dD", 2, 15),
+ (sequence "F%dD", 0, 15))>;
+def CSR_SystemZ_AllRegs_Vector : CalleeSavedRegs<(add (sequence "R%dD", 2, 15),
+ (sequence "V%d", 0, 31))>;
+
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index b2d59b1706d..565299c9013 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -204,7 +204,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
}
- // Save FPRs in the normal TargetInstrInfo way.
+ // Save FPRs/VRs in the normal TargetInstrInfo way.
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
unsigned Reg = CSI[I].getReg();
if (SystemZ::FP64BitRegClass.contains(Reg)) {
@@ -212,6 +212,11 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
&SystemZ::FP64BitRegClass, TRI);
}
+ if (SystemZ::VR128BitRegClass.contains(Reg)) {
+ MBB.addLiveIn(Reg);
+ TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
+ &SystemZ::VR128BitRegClass, TRI);
+ }
}
return true;
@@ -231,12 +236,15 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
bool HasFP = hasFP(MF);
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
- // Restore FPRs in the normal TargetInstrInfo way.
+ // Restore FPRs/VRs in the normal TargetInstrInfo way.
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
unsigned Reg = CSI[I].getReg();
if (SystemZ::FP64BitRegClass.contains(Reg))
TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
&SystemZ::FP64BitRegClass, TRI);
+ if (SystemZ::VR128BitRegClass.contains(Reg))
+ TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
+ &SystemZ::VR128BitRegClass, TRI);
}
// Restore call-saved GPRs (but not call-clobbered varargs, which at
@@ -425,7 +433,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
I->addLiveIn(SystemZ::R11D);
}
- // Skip over the FPR saves.
+ // Skip over the FPR/VR saves.
SmallVector<unsigned, 8> CFIIndexes;
for (auto &Save : CSI) {
unsigned Reg = Save.getReg();
@@ -436,19 +444,26 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
++MBBI;
else
llvm_unreachable("Couldn't skip over FPR save");
+ } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
+ if (MBBI != MBB.end() &&
+ MBBI->getOpcode() == SystemZ::VST)
+ ++MBBI;
+ else
+ llvm_unreachable("Couldn't skip over VR save");
+ } else
+ continue;
- // Add CFI for the this save.
- unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
- unsigned IgnoredFrameReg;
- int64_t Offset =
- getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
+ // Add CFI for the this save.
+ unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
+ unsigned IgnoredFrameReg;
+ int64_t Offset =
+ getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
+ unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, DwarfReg, SPOffsetFromCFA + Offset));
- CFIIndexes.push_back(CFIIndex);
- }
+ CFIIndexes.push_back(CFIIndex);
}
- // Complete the CFI for the FPR saves, modelling them as taking effect
+ // Complete the CFI for the FPR/VR saves, modelling them as taking effect
// after the last save.
for (auto CFIIndex : CFIIndexes) {
BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
index 856505e00a1..91c7d1f6e85 100644
--- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -108,6 +108,10 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
const MCPhysReg *
SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+ const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
+ if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
+ return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
+ : CSR_SystemZ_AllRegs_SaveList;
if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
MF->getFunction().getAttributes().hasAttrSomewhere(
Attribute::SwiftError))
@@ -118,6 +122,10 @@ SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const uint32_t *
SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const {
+ const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
+ if (CC == CallingConv::AnyReg)
+ return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
+ : CSR_SystemZ_AllRegs_RegMask;
if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
MF.getFunction().getAttributes().hasAttrSomewhere(
Attribute::SwiftError))
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