diff options
Diffstat (limited to 'llvm/lib/Target')
67 files changed, 127 insertions, 125 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index b0bda7c43c1..9ff2472dbec 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -392,7 +392,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, // Check all instructions, except the terminators. It is assumed that // terminators never have side effects or define any used register values. for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) { - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; if (++InstrCount > BlockInstrLimit && !Stress) { diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index d233827078a..2523cfdfb53 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -162,7 +162,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF) { // realistically that's not a big deal at this stage of the game. for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue() || MI.isPseudo() || + if (MI.isDebugInstr() || MI.isPseudo() || MI.getOpcode() == AArch64::ADDXri || MI.getOpcode() == AArch64::ADDSXri) continue; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 452bb13bf88..879d91d0d15 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -5044,7 +5044,7 @@ AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, return MachineOutlinerInstrType::Illegal; // Don't allow debug values to impact outlining type. - if (MI.isDebugValue() || MI.isIndirectDebugValue()) + if (MI.isDebugInstr() || MI.isIndirectDebugValue()) return MachineOutlinerInstrType::Invisible; // At this point, KILL instructions don't really tell us much so we can go diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 9cb9045ca76..2a05e3baa62 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -511,7 +511,7 @@ uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const // TODO: CodeSize should account for multiple functions. // TODO: Should we count size of debug info? - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; CodeSize += TII->getInstSizeInBytes(MI); @@ -652,7 +652,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( continue; case AMDGPU::NoRegister: - assert(MI.isDebugValue()); + assert(MI.isDebugInstr()); continue; case AMDGPU::VCC: diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index dd515b0bf2f..20f1321e79f 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -634,7 +634,7 @@ int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) { } int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) { - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return 0; const SIRegisterInfo *TRI = ST.getRegisterInfo(); diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index 9fecd8576f9..bf8413921d4 100644 --- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -69,14 +69,14 @@ static void printRegion(raw_ostream &OS, auto I = Begin; MaxInstNum = std::max(MaxInstNum, 1u); for (; I != End && MaxInstNum; ++I, --MaxInstNum) { - if (!I->isDebugValue() && LIS) + if (!I->isDebugInstr() && LIS) OS << LIS->getInstructionIndex(*I); OS << '\t' << *I; } if (I != End) { OS << "\t...\n"; I = std::prev(End); - if (!I->isDebugValue() && LIS) + if (!I->isDebugInstr() && LIS) OS << LIS->getInstructionIndex(*I); OS << '\t' << *I; } @@ -384,10 +384,10 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule, if (MI != &*Top) { BB->remove(MI); BB->insert(Top, MI); - if (!MI->isDebugValue()) + if (!MI->isDebugInstr()) LIS->handleMove(*MI, true); } - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { // Reset read - undef flags and update them later. for (auto &Op : MI->operands()) if (Op.isReg() && Op.isDef()) diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp index a294ae075a2..4e569a27e97 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -301,7 +301,7 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) { LastTrackedMI = &MI; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI); diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index cd7ccb4ac31..f92788ebaa7 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -388,13 +388,13 @@ void GCNScheduleDAGMILive::schedule() { DEBUG(dbgs() << "Attempting to revert scheduling.\n"); RegionEnd = RegionBegin; for (MachineInstr *MI : Unsched) { - if (MI->isDebugValue()) + if (MI->isDebugInstr()) continue; if (MI->getIterator() != RegionEnd) { BB->remove(MI); BB->insert(RegionEnd, MI); - if (!MI->isDebugValue()) + if (!MI->isDebugInstr()) LIS->handleMove(*MI, true); } // Reset read-undef flags and update them later. @@ -403,7 +403,7 @@ void GCNScheduleDAGMILive::schedule() { Op.setIsUndef(false); RegisterOperands RegOpers; RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { if (ShouldTrackLaneMasks) { // Adjust liveness and add missing dead+read-undef flags. SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); diff --git a/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp b/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp index 69ec3816772..c8ae8f71adc 100644 --- a/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp +++ b/llvm/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp @@ -78,8 +78,8 @@ bool SIDebuggerInsertNops::runOnMachineFunction(MachineFunction &MF) { for (auto &MBB : MF) { for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) { - // Skip DBG_VALUE instructions and instructions without location. - if (MI->isDebugValue() || !MI->getDebugLoc()) + // Skip debug instructions and instructions without location. + if (MI->isDebugInstr() || !MI->getDebugLoc()) continue; // Insert nop instruction if line number does not have nop inserted. diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 7dc3b68e01d..e6aaaf94751 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -897,7 +897,7 @@ void SIInsertWaitcnts::generateWaitcntInstBefore( setForceEmitWaitcnt(); bool IsForceEmitWaitcnt = isForceEmitWaitcnt(); - if (MI.isDebugValue() && + if (MI.isDebugInstr() && // TODO: any other opcode? !NeedLineMapping) { return; diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 04536cdfe72..0fd4c6bfed9 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -1280,7 +1280,7 @@ static MachineBasicBlock::iterator nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End) { for (; I != End; ++I) { - if (!I->isDebugValue()) + if (!I->isDebugInstr()) break; } return I; diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index 51ac8146f3a..b7bb80acb71 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -134,7 +134,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { } while (I != E) { - if (I->isDebugValue()) { + if (I->isDebugInstr()) { I = std::next(I); continue; } diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp index 4a95fced446..f8d14d243f4 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp +++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp @@ -173,7 +173,7 @@ bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, bool CantAnalyze = false; // Skip over DEBUG values and predicated nonterminators. - while (I->isDebugValue() || !I->isTerminator()) { + while (I->isDebugInstr() || !I->isTerminator()) { if (I == MBB.begin()) return false; --I; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 89e22369810..efe96f8d1b0 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -331,7 +331,7 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, bool CantAnalyze = false; // Skip over DEBUG values and predicated nonterminators. - while (I->isDebugValue() || !I->isTerminator()) { + while (I->isDebugInstr() || !I->isTerminator()) { if (I == MBB.begin()) return false; --I; @@ -1815,7 +1815,7 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // considered a scheduling hazard, which is wrong. It should be the actual // instruction preceding the dbg_value instruction(s), just like it is // when debug info is not present. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return false; // Terminators and labels can't be scheduled around. @@ -1829,8 +1829,8 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // to the t2IT instruction. The added compile time and complexity does not // seem worth it. MachineBasicBlock::const_iterator I = MI; - // Make sure to skip any dbg_value instructions - while (++I != MBB->end() && I->isDebugValue()) + // Make sure to skip any debug instructions + while (++I != MBB->end() && I->isDebugInstr()) ; if (I != MBB->end() && I->getOpcode() == ARM::t2IT) return true; diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index 7411caf4d12..1e3655aac89 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -701,7 +701,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) { WaterList.push_back(&MBB); for (MachineInstr &I : MBB) { - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; unsigned Opc = I.getOpcode(); diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp index f878bf9937a..d5dacbe0877 100644 --- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp +++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp @@ -37,7 +37,7 @@ ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { MachineInstr *MI = SU->getInstr(); - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following // a VMLA / VMLS will cause 4 cycle stall. const MCInstrDesc &MCID = MI->getDesc(); @@ -81,7 +81,7 @@ void ARMHazardRecognizer::Reset() { void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { MachineInstr *MI = SU->getInstr(); - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { LastMI = MI; FpMLxStalls = 0; } diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index bd478702c61..174ed3e5dd2 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1198,7 +1198,7 @@ findIncDecBefore(MachineBasicBlock::iterator MBBI, unsigned Reg, // Skip debug values. MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI); - while (PrevMBBI->isDebugValue() && PrevMBBI != BeginMBBI) + while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI) --PrevMBBI; Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg); @@ -1214,7 +1214,7 @@ findIncDecAfter(MachineBasicBlock::iterator MBBI, unsigned Reg, MachineBasicBlock::iterator EndMBBI = MBB.end(); MachineBasicBlock::iterator NextMBBI = std::next(MBBI); // Skip debug values. - while (NextMBBI != EndMBBI && NextMBBI->isDebugValue()) + while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr()) ++NextMBBI; if (NextMBBI == EndMBBI) return EndMBBI; @@ -1807,7 +1807,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) { MBBI = I; --Position; // Fallthrough to look into existing chain. - } else if (MBBI->isDebugValue()) { + } else if (MBBI->isDebugInstr()) { continue; } else if (MBBI->getOpcode() == ARM::t2LDRDi8 || MBBI->getOpcode() == ARM::t2STRDi8) { @@ -1891,8 +1891,8 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { MBBI->getOpcode() == ARM::tBX_RET || MBBI->getOpcode() == ARM::MOVPCLR)) { MachineBasicBlock::iterator PrevI = std::prev(MBBI); - // Ignore any DBG_VALUE instructions. - while (PrevI->isDebugValue() && PrevI != MBB.begin()) + // Ignore any debug instructions. + while (PrevI->isDebugInstr() && PrevI != MBB.begin()) --PrevI; MachineInstr &PrevMI = *PrevI; unsigned Opcode = PrevMI.getOpcode(); @@ -2063,7 +2063,7 @@ static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, // Are there stores / loads / calls between them? SmallSet<unsigned, 4> AddedRegPressure; while (++I != E) { - if (I->isDebugValue() || MemOps.count(&*I)) + if (I->isDebugInstr() || MemOps.count(&*I)) continue; if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects()) return false; @@ -2253,7 +2253,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, // This is the new location for the loads / stores. MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp; while (InsertPos != MBB->end() && - (MemOps.count(&*InsertPos) || InsertPos->isDebugValue())) + (MemOps.count(&*InsertPos) || InsertPos->isDebugInstr())) ++InsertPos; // If we are moving a pair of loads / stores, see if it makes sense @@ -2355,7 +2355,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) { break; } - if (!MI.isDebugValue()) + if (!MI.isDebugInstr()) MI2LocMap[&MI] = ++Loc; if (!isMemoryOp(MI)) diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index 04bdd91b53e..e0a5f7f04fa 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -183,7 +183,7 @@ Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI, // If not, then there is nothing to be gained by moving the copy. MachineBasicBlock::iterator I = MI; ++I; MachineBasicBlock::iterator E = MI->getParent()->end(); - while (I != E && I->isDebugValue()) + while (I != E && I->isDebugInstr()) ++I; if (I != E) { unsigned NPredReg = 0; @@ -237,7 +237,7 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) { // block so check the instruction we just put in the block. for (; MBBI != E && Pos && (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { - if (MBBI->isDebugValue()) + if (MBBI->isDebugInstr()) continue; MachineInstr *NMI = &*MBBI; diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index 179f1133d6e..d5f0ba9ee48 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -82,7 +82,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock::iterator E = MBB->begin(); unsigned Count = 4; // At most 4 instructions in an IT block. while (Count && MBBI != E) { - if (MBBI->isDebugValue()) { + if (MBBI->isDebugInstr()) { --MBBI; continue; } @@ -109,7 +109,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, bool Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const { - while (MBBI->isDebugValue()) { + while (MBBI->isDebugInstr()) { ++MBBI; if (MBBI == MBB.end()) return false; diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 5357e26856e..115ba65ff86 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -1033,7 +1033,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) { BundleMI = MI; continue; } - if (MI->isDebugValue()) + if (MI->isDebugInstr()) continue; LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR); diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp index 5e0818bea1c..e4bdd40fb74 100644 --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp @@ -475,7 +475,7 @@ bool ThumbRegisterInfo::saveScavengerRegister( // before that instead and adjust the UseMI. bool done = false; for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) { - if (II->isDebugValue()) + if (II->isDebugInstr()) continue; // If this instruction affects R12, adjust our restore point. for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp index 1a89a13693e..0c32334167f 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp +++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp @@ -273,7 +273,7 @@ bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) { + if (I->isDebugInstr()) { continue; } @@ -444,7 +444,7 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) { + if (I->isDebugInstr()) { continue; } //:TODO: add here the missing jmp instructions once they are implemented diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp index ffb7acd222b..ab6d7c84cd1 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp +++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp @@ -93,7 +93,7 @@ bool BPFInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator @@ -168,7 +168,7 @@ unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != BPF::JMP) break; diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index 378aafbc8dd..69529b0d116 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -843,7 +843,7 @@ void BT::visitPHI(const MachineInstr &PI) { void BT::visitNonBranch(const MachineInstr &MI) { if (Trace) dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI; - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; assert(!MI.isBranch() && "Unexpected branch instruction"); diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 6b836e29715..0ac83ea7c5f 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -760,7 +760,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { MachineBasicBlock::const_instr_iterator MII = MI->getIterator(); for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII) - if (!MII->isDebugValue() && !MII->isImplicitDef()) + if (!MII->isDebugInstr() && !MII->isImplicitDef()) HexagonLowerToMC(MCII, &*MII, MCB, *this); } else { HexagonLowerToMC(MCII, MI, MCB, *this); diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp index 8153c49447d..2fb30dfbc1c 100644 --- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -160,7 +160,7 @@ HexagonBlockRanges::InstrIndexMap::InstrIndexMap(MachineBasicBlock &B) IndexType Idx = IndexType::First; First = Idx; for (auto &In : B) { - if (In.isDebugValue()) + if (In.isDebugInstr()) continue; assert(getIndex(&In) == IndexType::None && "Instruction already in map"); Map.insert(std::make_pair(Idx, &In)); @@ -314,7 +314,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, RegisterSet Defs, Clobbers; for (auto &In : B) { - if (In.isDebugValue()) + if (In.isDebugInstr()) continue; IndexType Index = IndexMap.getIndex(&In); // Process uses first. diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 62b2e892b70..730cfafae42 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -799,7 +799,7 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB, SetVector<const MachineBasicBlock*> &Targets) { MachineBasicBlock::const_iterator FirstBr = MB->end(); for (const MachineInstr &MI : *MB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (MI.isBranch()) { FirstBr = MI.getIterator(); @@ -814,7 +814,7 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB, for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) { const MachineInstr &MI = *I; // Can there be debug instructions between branches? - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (!InstrExec.count(&MI)) continue; @@ -896,7 +896,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { // If the successor block just became executable, visit all instructions. // To see if this is the first time we're visiting it, check the first // non-debug instruction to see if it is executable. - while (It != End && It->isDebugValue()) + while (It != End && It->isDebugInstr()) ++It; assert(It == End || !It->isPHI()); // If this block has been visited, go on to the next one. @@ -905,7 +905,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { // For now, scan all non-branch instructions. Branches require different // processing. while (It != End && !It->isBranch()) { - if (!It->isDebugValue()) { + if (!It->isDebugInstr()) { InstrExec.insert(&*It); visitNonBranch(*It); } diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 087a77203fc..f3d24739da4 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -300,7 +300,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // * reads I2's def reg // * or has unmodelled side effects // we can't move I2 across it. - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) { @@ -358,7 +358,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // to remove the implicit killed %d4 operand. For now, we are // conservative and disallow the move. // we can't move I1 across it. - if (MI.isDebugValue()) { + if (MI.isDebugInstr()) { if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2. DbgMItoMove.push_back(&MI); continue; @@ -396,7 +396,7 @@ void HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) { DenseMap<unsigned, MachineInstr *> LastDef; for (MachineInstr &MI : BB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // Mark TFRs that feed a potential new value store as such. @@ -423,7 +423,7 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) { MachineBasicBlock::iterator It(DefInst); unsigned NumInstsToDef = 0; while (&*It != &MI) { - if (!It->isDebugValue()) + if (!It->isDebugInstr()) ++NumInstsToDef; ++It; } @@ -489,7 +489,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { MI != End;) { MachineInstr &I1 = *MI++; - if (I1.isDebugValue()) + if (I1.isDebugInstr()) continue; // Don't combine a TFR whose user could be newified (instructions that @@ -526,7 +526,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1, bool &DoInsertAtI1, bool AllowC64) { MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1)); - while (I2 != I1.getParent()->end() && I2->isDebugValue()) + while (I2 != I1.getParent()->end() && I2->isDebugInstr()) ++I2; unsigned I1DestReg = I1.getOperand(0).getReg(); diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 660466d0d6c..bbd06ff747e 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -367,7 +367,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) return false; for (auto &MI : *B) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (MI.isConditionalBranch()) return false; diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index 7c91412c250..e5af96468af 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -356,7 +356,7 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { return false; }; for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) { - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // This isn't 100% accurate, but it's safe. // It won't detect (as a kill) a case like this diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 78e82579c47..1ec1ce01336 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -134,7 +134,7 @@ static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE) { unsigned Count = 0; for (; MIB != MIE; ++MIB) { - if (!MIB->isDebugValue()) + if (!MIB->isDebugInstr()) ++Count; } return Count; @@ -419,7 +419,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, I = MBB.instr_end(); --I; - while (I->isDebugValue()) { + while (I->isDebugInstr()) { if (I == MBB.instr_begin()) return false; --I; @@ -562,7 +562,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, unsigned Count = 0; while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Only removing branches from end of MBB. if (!I->isBranch()) @@ -1626,7 +1626,7 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // considered a scheduling hazard, which is wrong. It should be the actual // instruction preceding the dbg_value instruction(s), just like it is // when debug info is not present. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return false; // Throwing call is a boundary. @@ -3164,7 +3164,7 @@ SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs( I = MBB.instr_end(); --I; - while (I->isDebugValue()) { + while (I->isDebugInstr()) { if (I == MBB.instr_begin()) return Jumpers; --I; @@ -4201,7 +4201,7 @@ short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const { // use a constant extender, which requires another 4 bytes. // For debug instructions and prolog labels, return 0. unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const { - if (MI.isDebugValue() || MI.isPosition()) + if (MI.isDebugInstr() || MI.isPosition()) return 0; unsigned Size = MI.getDesc().getSize(); diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index a3686c89d61..3dace168284 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -302,7 +302,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, // and satisfy the following conditions. ++II; for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) { - if (localII->isDebugValue()) + if (localII->isDebugInstr()) continue; // Check 1. @@ -494,7 +494,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); MII != E;) { MachineInstr &MI = *--MII; - if (MI.isDebugValue()) { + if (MI.isDebugInstr()) { continue; } diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index 4979ce1e7d6..386e6cbad1f 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -163,7 +163,7 @@ bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const { if (MI->mayLoad() || MI->mayStore()) if (MemRefsFixed || isVolatileInstr(MI)) return true; - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return false; unsigned Opc = MI->getOpcode(); diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 8c528b9ed22..2ae48e3d68f 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1037,7 +1037,7 @@ void HexagonPacketizerList::initPacketizerState() { // Ignore bundling of pseudo instructions. bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return true; if (MI.isCFIInstruction()) diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp index ceb4887a36d..3d1ec31dada 100644 --- a/llvm/lib/Target/Hexagon/RDFGraph.cpp +++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp @@ -893,7 +893,7 @@ void DataFlowGraph::build(unsigned Options) { NodeAddr<BlockNode*> BA = newBlock(Func, &B); BlockNodes.insert(std::make_pair(&B, BA)); for (MachineInstr &I : B) { - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; buildStmt(BA, I); } diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp index ef50a5319dc..c257d754ddf 100644 --- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp +++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp @@ -880,7 +880,7 @@ void Liveness::resetKills(MachineBasicBlock *B) { for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) { MachineInstr *MI = &*I; - if (MI->isDebugValue()) + if (MI->isDebugInstr()) continue; MI->clearKillInfo(); diff --git a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp index 6b4fa777178..ea76a112837 100644 --- a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -156,7 +156,7 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB, for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse(); I != MBB.instr_rend(); ++I) { // skip debug value - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Convert to forward iterator. diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index a7c9a7a7f28..493d02bef37 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -573,8 +573,8 @@ bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB, while (Instruction != MBB.begin()) { --Instruction; - // Skip over debug values. - if (Instruction->isDebugValue()) + // Skip over debug instructions. + if (Instruction->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator @@ -699,7 +699,7 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, while (Instruction != MBB.begin()) { --Instruction; - if (Instruction->isDebugValue()) + if (Instruction->isDebugInstr()) continue; if (Instruction->getOpcode() != Lanai::BT && Instruction->getOpcode() != Lanai::BRCC) { diff --git a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp index c29c933db74..35e2542dfb1 100644 --- a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -343,7 +343,7 @@ MbbIterator LanaiMemAluCombiner::findClosestSuitableAluInstr( break; // Skip over debug instructions - if (First->isDebugValue()) + if (First->isDebugInstr()) continue; if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) { diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index 6135ce08092..dd1b30a3e47 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -113,7 +113,7 @@ unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != MSP430::JMP && I->getOpcode() != MSP430::JCC && @@ -183,7 +183,7 @@ bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 97bb5fbdf95..8ffc0731abc 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -160,6 +160,8 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { PrintDebugValueComment(MI, OS); return; } + if (MI->isDebugLabel()) + return; // If we just ended a constant pool, mark it as such. if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 5e7a1afc66f..5ee816be373 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -661,7 +661,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) { if (!BBHasFallthrough(&MBB)) WaterList.push_back(&MBB); for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; int Opc = MI.getOpcode(); diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index 4f292e66ce0..dfebc343d84 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -679,7 +679,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, ++I; // skip debug value - if (CurrI->isDebugValue()) + if (CurrI->isDebugInstr()) continue; if (terminateSearch(*CurrI)) diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 947d7e45a9f..9254ae6a13b 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -163,7 +163,7 @@ unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, // Note that indirect branches are not removed. while (I != REnd && removed < 2) { // Skip past debug instructions. - if (I->isDebugValue()) { + if (I->isDebugInstr()) { ++I; continue; } @@ -195,7 +195,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch( MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); // Skip all the debug instructions. - while (I != REnd && I->isDebugValue()) + while (I != REnd && I->isDebugInstr()) ++I; if (I == REnd || !isUnpredicatedTerminator(*I)) { @@ -220,7 +220,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch( // Skip past any debug instruction to see if the second last actual // is a branch. ++I; - while (I != REnd && I->isDebugValue()) + while (I != REnd && I->isDebugInstr()) ++I; if (I != REnd) { diff --git a/llvm/lib/Target/Mips/MipsLongBranch.cpp b/llvm/lib/Target/Mips/MipsLongBranch.cpp index bc5f0df211e..7a7c8abfc6f 100644 --- a/llvm/lib/Target/Mips/MipsLongBranch.cpp +++ b/llvm/lib/Target/Mips/MipsLongBranch.cpp @@ -125,7 +125,7 @@ static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) { // found or it reaches E. static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) { for (; B != E; ++B) - if (!B->isDebugValue()) + if (!B->isDebugInstr()) return B; return E; diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp index 1699463c0a4..ed5e496b32f 100644 --- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp +++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -128,7 +128,7 @@ protected: if (J->getOperand(i).isMBB() && J->getOperand(i).getMBB() == &ReturnMBB) OtherReference = true; - } else if (!J->isTerminator() && !J->isDebugValue()) + } else if (!J->isTerminator() && !J->isDebugInstr()) break; if (J == (*PI)->begin()) diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp index f327396370f..4c718f8883e 100644 --- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -330,7 +330,7 @@ getHazardType(SUnit *SU, int Stalls) { MachineInstr *MI = SU->getInstr(); - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return NoHazard; unsigned Opcode = MI->getOpcode(); @@ -388,7 +388,7 @@ getHazardType(SUnit *SU, int Stalls) { void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { MachineInstr *MI = SU->getInstr(); - if (MI->isDebugValue()) + if (MI->isDebugInstr()) return; unsigned Opcode = MI->getOpcode(); diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 8151e433d6a..6f44e3adcfe 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -232,7 +232,7 @@ bool PPCMIPeephole::simplifyCode(void) { SomethingChanged = false; for (MachineBasicBlock &MBB : *MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; if (TII->convertToImmediateForm(MI)) { @@ -261,7 +261,7 @@ bool PPCMIPeephole::simplifyCode(void) { } // Ignore debug instructions. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; // Per-opcode peepholes. diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp index 635f8cd53ec..83c9dd67c33 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp @@ -249,7 +249,7 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() { for (MachineBasicBlock &MBB : *MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; bool RelevantInstr = false; diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp index 9b1d0f5bf3c..6290e5a15a8 100644 --- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp @@ -207,8 +207,8 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (!done) --I; - // skip debug value - if (I->isDebugValue()) + // skip debug instruction + if (I->isDebugInstr()) continue; if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() || diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index ea8ed830baf..6750763d8ee 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -280,7 +280,7 @@ unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != SP::BA diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index f094cf18dfd..f0f9211efd5 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -389,7 +389,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator instruction, we're @@ -479,7 +479,7 @@ unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (!I->isBranch()) break; diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp index ef8b9806f89..802962bd4db 100644 --- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -295,7 +295,7 @@ uint64_t SystemZLongBranch::initMBBInfo() { // Add the terminators. while (MI != End) { - if (!MI->isDebugValue()) { + if (!MI->isDebugInstr()) { assert(MI->isTerminator() && "Terminator followed by non-terminator"); Terminators.push_back(describeTerminator(*MI)); skipTerminator(Position, Terminators.back(), false); diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp index 51e8beb085a..1de11a1166d 100644 --- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp +++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp @@ -65,7 +65,7 @@ advanceTo(MachineBasicBlock::iterator NextBegin) { std::next(LastEmittedMI) : MBB->begin()); for (; I != NextBegin; ++I) { - if (I->isPosition() || I->isDebugValue()) + if (I->isPosition() || I->isDebugInstr()) continue; HazardRec->emitInstruction(&*I); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp index cf1bbfa5e18..3429c4fc6e2 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp @@ -265,7 +265,7 @@ static void FixEndsAtEndOfFunction( for (MachineBasicBlock &MBB : reverse(MF)) { for (MachineInstr &MI : reverse(MBB)) { - if (MI.isPosition() || MI.isDebugValue()) + if (MI.isPosition() || MI.isDebugInstr()) continue; if (MI.getOpcode() == WebAssembly::END_BLOCK) { BlockTops[&MI]->getOperand(0).setImm(int32_t(retType)); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp index cf14643627a..caf12a610be 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp @@ -231,7 +231,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { MachineInstr &MI = *I++; assert(!WebAssembly::isArgument(MI)); - if (MI.isDebugValue() || MI.isLabel()) + if (MI.isDebugInstr() || MI.isLabel()) continue; // Replace tee instructions with tee_local. The difference is that tee @@ -375,7 +375,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { // Assert that all registers have been stackified at this point. for (const MachineBasicBlock &MBB : MF) { for (const MachineInstr &MI : MBB) { - if (MI.isDebugValue() || MI.isLabel()) + if (MI.isDebugInstr() || MI.isLabel()) continue; for (const MachineOperand &MO : MI.explicit_operands()) { assert( diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index 739d6cf6253..fbdf4c011a9 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -151,7 +151,7 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.instr_begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (!I->isTerminator()) break; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 6780f252902..c326bdb8a7b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -163,7 +163,7 @@ static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read, assert(!MI.isPosition()); assert(!MI.isTerminator()); - if (MI.isDebugValue()) + if (MI.isDebugInstr()) return; // Check for loads. @@ -871,7 +871,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) { SmallVector<unsigned, 0> Stack; for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; for (MachineOperand &MO : reverse(MI.explicit_operands())) { if (!MO.isReg()) diff --git a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp index 522dc7926b9..c73fd6eb144 100644 --- a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp +++ b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp @@ -375,7 +375,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF, // Skip over DEBUG_VALUE. // For globals in PIC mode, we can have some LEAs here. Skip them as well. // TODO: Extend this to something that covers more cases. - while (I->getOpcode() == X86::LEA32r || I->isDebugValue()) + while (I->getOpcode() == X86::LEA32r || I->isDebugInstr()) ++I; unsigned StackPtr = RegInfo.getStackRegister(); diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp index 493d42c85b4..38baa90f479 100644 --- a/llvm/lib/Target/X86/X86CmovConversion.cpp +++ b/llvm/lib/Target/X86/X86CmovConversion.cpp @@ -295,7 +295,7 @@ bool X86CmovConverterPass::collectCmovCandidates( for (auto &I : *MBB) { // Skip debug instructions. - if (I.isDebugValue()) + if (I.isDebugInstr()) continue; X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode()); // Check if we found a X86::CMOVrr instruction. @@ -435,7 +435,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates( RegDefMaps[PhyRegType].clear(); for (MachineInstr &MI : *MBB) { // Skip debug instructions. - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; unsigned MIDepth = 0; unsigned MIDepthOpt = 0; @@ -605,7 +605,7 @@ static void packCmovGroup(MachineInstr *First, MachineInstr *Last) { SmallVector<MachineInstr *, 2> DBGInstructions; for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) { - if (I->isDebugValue()) + if (I->isDebugInstr()) DBGInstructions.push_back(&*I); } diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 248f9607c63..ffdb949918f 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -1675,7 +1675,7 @@ void FPS::setKillFlags(MachineBasicBlock &MBB) const { for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend(); I != E; ++I) { - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; std::bitset<8> Defs; diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index 42f9676fbe9..18f62e06afa 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -3025,7 +3025,7 @@ void X86FrameLowering::orderFrameObjects( // Count the number of uses for each object. for (auto &MBB : MF) { for (auto &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; for (const MachineOperand &MO : MI.operands()) { // Check to see if it's a local stack symbol. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 203c1318046..16ee56ecaa0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -27766,7 +27766,7 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, MCSymbol *Sym = nullptr; for (const auto &MI : MBB) { - if (MI.isDebugValue()) + if (MI.isDebugInstr()) continue; assert(MI.isEHLabel() && "expected EH_LABEL"); diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 5c85c7e5282..31ce4bdc767 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -4340,8 +4340,8 @@ bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, // This instruction defines EFLAGS, no need to look any further. return true; ++Iter; - // Skip over DBG_VALUE. - while (Iter != E && Iter->isDebugValue()) + // Skip over debug instructions. + while (Iter != E && Iter->isDebugInstr()) ++Iter; } @@ -4363,8 +4363,8 @@ bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, return !MBB.isLiveIn(X86::EFLAGS); --Iter; - // Skip over DBG_VALUE. - while (Iter != B && Iter->isDebugValue()) + // Skip over debug instructions. + while (Iter != B && Iter->isDebugInstr()) --Iter; bool SawKill = false; @@ -6254,7 +6254,7 @@ void X86InstrInfo::replaceBranchWithTailCall( MachineBasicBlock::iterator I = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (!I->isBranch()) assert(0 && "Can't find the branch to replace!"); @@ -6322,7 +6322,7 @@ bool X86InstrInfo::AnalyzeBranchImpl( MachineBasicBlock::iterator UnCondBrIter = MBB.end(); while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; // Working from the bottom, when we see a non-terminator instruction, we're @@ -6559,7 +6559,7 @@ unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, while (I != MBB.begin()) { --I; - if (I->isDebugValue()) + if (I->isDebugInstr()) continue; if (I->getOpcode() != X86::JMP_1 && X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) @@ -11172,7 +11172,7 @@ X86GenInstrInfo::MachineOutlinerInstrType X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const { MachineInstr &MI = *MIT; // Don't allow debug values to impact outlining type. - if (MI.isDebugValue() || MI.isIndirectDebugValue()) + if (MI.isDebugInstr() || MI.isIndirectDebugValue()) return MachineOutlinerInstrType::Invisible; // At this point, KILL instructions don't really tell us much so we can go diff --git a/llvm/lib/Target/X86/X86PadShortFunction.cpp b/llvm/lib/Target/X86/X86PadShortFunction.cpp index 2fe5cb973da..85b9aecc210 100644 --- a/llvm/lib/Target/X86/X86PadShortFunction.cpp +++ b/llvm/lib/Target/X86/X86PadShortFunction.cpp @@ -129,7 +129,7 @@ bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) { "Basic block should contain at least a RET but is empty"); MachineBasicBlock::iterator ReturnLoc = --MBB->end(); - while (ReturnLoc->isDebugValue()) + while (ReturnLoc->isDebugInstr()) --ReturnLoc; assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && "Basic block does not end with RET"); diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index a5fe63b2829..b87c149a36d 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -427,7 +427,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); DebugLoc DL; - if (MI != MBB.end() && !MI->isDebugValue()) + if (MI != MBB.end() && !MI->isDebugInstr()) DL = MI->getDebugLoc(); for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index c885332b07a..d5e276788f7 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -364,7 +364,7 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { DebugLoc DL; - if (I != MBB.end() && !I->isDebugValue()) + if (I != MBB.end() && !I->isDebugInstr()) DL = I->getDebugLoc(); MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -386,7 +386,7 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { DebugLoc DL; - if (I != MBB.end() && !I->isDebugValue()) + if (I != MBB.end() && !I->isDebugInstr()) DL = I->getDebugLoc(); MachineFunction *MF = MBB.getParent(); const MachineFrameInfo &MFI = MF->getFrameInfo(); @@ -429,7 +429,7 @@ MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate( MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const { DebugLoc dl; - if (MI != MBB.end() && !MI->isDebugValue()) + if (MI != MBB.end() && !MI->isDebugInstr()) dl = MI->getDebugLoc(); if (isImmMskBitp(Value)) { int N = Log2_32(Value) + 1; |
