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-rw-r--r--llvm/lib/Target/Alpha/AlphaISelLowering.cpp2
-rw-r--r--llvm/lib/Target/IA64/IA64ISelLowering.cpp4
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp49
-rw-r--r--llvm/lib/Target/PowerPC/README.txt42
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp2
5 files changed, 46 insertions, 53 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
index 2990146899b..c9cafd478e5 100644
--- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -56,6 +56,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
index 11b95c4e02e..1c835a8c98d 100644
--- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp
@@ -35,10 +35,14 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
// register class for predicate registers
addRegisterClass(MVT::i1, IA64::PRRegisterClass);
+ setOperationAction(ISD::BR_CC , MVT::Other, Expand);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
+ // ia64 uses SELECT not SELECT_CC
+ setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
+
// We need to handle ISD::RET for void functions ourselves,
// so we get a chance to restore ar.pfs before adding a
// br.ret insn
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 28beeafce16..ec35f37e96e 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13,6 +13,7 @@
#include "PPCISelLowering.h"
#include "PPCTargetMachine.h"
+#include "llvm/ADT/VectorExtras.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -20,7 +21,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
-#include "llvm/ADT/VectorExtras.h"
+#include "llvm/Support/MathExtras.h"
using namespace llvm;
PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
@@ -85,7 +86,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
- // PowerPC wants to optimize setcc i32, imm a bit.
+ // PowerPC wants to optimize integer setcc a bit
setOperationAction(ISD::SETCC, MVT::i32, Custom);
// PowerPC does not have BRCOND* which requires SetCC
@@ -452,15 +453,41 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
}
case ISD::SETCC: {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
- if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
- if (C->getValue() && !C->isAllOnesValue())
- if (CC == ISD::SETEQ || CC == ISD::SETNE ||
- CC == ISD::SETLT || CC == ISD::SETGT) {
- MVT::ValueType VT = Op.getValueType();
- SDOperand SUB = DAG.getNode(ISD::SUB, Op.getOperand(0).getValueType(),
- Op.getOperand(0), Op.getOperand(1));
- return DAG.getSetCC(VT, SUB, DAG.getConstant(0, VT), CC);
- }
+
+ // If we're comparing for equality to zero, expose the fact that this is
+ // implented as a ctlz/srl pair on ppc, so that the dag combiner can
+ // fold the new nodes.
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+ if (C->isNullValue() && CC == ISD::SETEQ) {
+ MVT::ValueType VT = Op.getOperand(0).getValueType();
+ SDOperand Zext = Op.getOperand(0);
+ if (VT < MVT::i32) {
+ VT = MVT::i32;
+ Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
+ }
+ unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
+ SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
+ SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
+ DAG.getConstant(Log2b, getShiftAmountTy()));
+ return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc);
+ }
+ // Leave comparisons against 0 and -1 alone for now, since they're usually
+ // optimized. FIXME: revisit this when we can custom lower all setcc
+ // optimizations.
+ if (C->isAllOnesValue() || C->isNullValue())
+ break;
+ }
+
+ // If we have an integer seteq/setne, turn it into a compare against zero
+ // by subtracting the rhs from the lhs, which is faster than setting a
+ // condition register, reading it back out, and masking the correct bit.
+ MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
+ if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
+ MVT::ValueType VT = Op.getValueType();
+ SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
+ Op.getOperand(1));
+ return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
+ }
break;
}
case ISD::VASTART: {
diff --git a/llvm/lib/Target/PowerPC/README.txt b/llvm/lib/Target/PowerPC/README.txt
index 1b05e7c4f0d..e23c6e77b5b 100644
--- a/llvm/lib/Target/PowerPC/README.txt
+++ b/llvm/lib/Target/PowerPC/README.txt
@@ -280,32 +280,6 @@ void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
===-------------------------------------------------------------------------===
-For this:
-
-int h(int i, int j, int k) {
- return (i==0||j==0||k == 0);
-}
-
-We currently emit this:
-
-_h:
- cntlzw r2, r3
- cntlzw r3, r4
- cntlzw r4, r5
- srwi r2, r2, 5
- srwi r3, r3, 5
- srwi r4, r4, 5
- or r2, r3, r2
- or r3, r2, r4
- blr
-
-The ctlz/shift instructions are created by the isel, so the dag combiner doesn't
-have a chance to pull the shifts through the or's (eliminating two
-instructions). SETCC nodes should be custom lowered in this case, not expanded
-by the isel.
-
-===-------------------------------------------------------------------------===
-
Darwin Stub LICM optimization:
Loops like this:
@@ -461,19 +435,3 @@ This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
same operands (but backwards) exists. In this case, this wouldn't save us
anything though, because the compares still wouldn't be shared.
-===-------------------------------------------------------------------------===
-
-A simple case we generate suboptimal code on:
-
-int test(int X) {
- return X == 0 ? 32 : 0;
-}
-
-_test:
- cntlzw r2, r3
- srwi r2, r2, 5
- slwi r3, r2, 5
- blr
-
-The shifts should be one 'andi'.
-
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d692780179c..0a63cfa1260 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -117,6 +117,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
}
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
+ setOperationAction(ISD::BR_CC , MVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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