diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelLowering.cpp | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/TargetSelectionDAG.td | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 |
7 files changed, 41 insertions, 43 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index cbbad532855..f94cfd1d421 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -48,19 +48,19 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); - // setOperationAction(ISD::BRIND, MVT::i64, Expand); - setOperationAction(ISD::BR_CC, MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); + setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); - setOperationAction(ISD::EXTLOAD, MVT::i1, Promote); - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand); - setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand); - setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote); - setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); - setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand); + // setOperationAction(ISD::BRIND, MVT::i64, Expand); + setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); diff --git a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 8367d245cf1..5add5d6ed5f 100644 --- a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -454,8 +454,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { */ case ISD::LOAD: - case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools? - case ISD::ZEXTLOAD: { + case ISD::LOADX: { // FIXME: load -1, not 1, for bools? SDOperand Chain = N->getOperand(0); SDOperand Address = N->getOperand(1); AddToISelQueue(Chain); diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp index 859530e409a..f832ea214f4 100644 --- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp +++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp @@ -35,6 +35,15 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) // register class for predicate registers addRegisterClass(MVT::i1, IA64::PRRegisterClass); + setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote); + + setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand); + + setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand); + setOperationAction(ISD::BRIND , MVT::i64, Expand); setOperationAction(ISD::BR_CC , MVT::Other, Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); @@ -50,15 +59,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) setSetCCResultType(MVT::i1); setShiftAmountType(MVT::i64); - setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote); - - setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand); - - setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); - setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand); - setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand); - setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand); - setOperationAction(ISD::FREM , MVT::f32 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ffb4617d3c5..e96982dcf0d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -43,6 +43,10 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); + // PowerPC has an i16 but no i8 (or i1) SEXTLOAD + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); + setOperationAction(ISD::ConstantFP, MVT::f64, Expand); setOperationAction(ISD::ConstantFP, MVT::f32, Expand); @@ -51,10 +55,6 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::MEMSET, MVT::Other, Expand); setOperationAction(ISD::MEMCPY, MVT::Other, Expand); - // PowerPC has an i16 but no i8 (or i1) SEXTLOAD - setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); - setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); - // PowerPC has no SREM/UREM instructions setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::UREM, MVT::i32, Expand); @@ -311,7 +311,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { static bool isFloatingPointZero(SDOperand Op) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); - else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { + else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) { // Maybe this has already been legalized into the constant pool? if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 1d1b595743c..801cf4ec9bf 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -137,6 +137,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); + // Turn FP extload into load/fextend + setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + // Custom legalize GlobalAddress nodes into LO/HI parts. setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::ConstantPool , MVT::i32, Custom); @@ -161,9 +164,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); - // Turn FP extload into load/fextend - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); - // Sparc has no select or setcc: expand to SELECT_CC. setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); @@ -332,7 +332,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { if (ObjectVT == MVT::i32) { Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); } else { - unsigned LoadOp = + ISD::LoadExtType LoadOp = I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. diff --git a/llvm/lib/Target/TargetSelectionDAG.td b/llvm/lib/Target/TargetSelectionDAG.td index f6d4cd5cdf2..2a2bd17bcf3 100644 --- a/llvm/lib/Target/TargetSelectionDAG.td +++ b/llvm/lib/Target/TargetSelectionDAG.td @@ -164,10 +164,10 @@ def SDTStore : SDTypeProfile<0, 2, [ // store SDTCisPtrTy<1> ]>; -def SDTExtLoad : SDTypeProfile<1, 3, [ // extload - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> +def SDTLoadX : SDTypeProfile<1, 4, [ // loadX + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisVT<4, i32> ]>; -def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload +def SDTIntExtLoad : SDTypeProfile<1, 3, [ // extload, sextload, zextload SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore @@ -308,11 +308,9 @@ def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>; def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>; def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>; -// Do not use sextld and zextld directly. Use sextload and zextload (see -// below) which pass in a dummy srcvalue node which tblgen will skip over. -def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; -def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>; -def extld : SDNode<"ISD::EXTLOAD" , SDTExtLoad, [SDNPHasChain]>; +// Do not use loadx directly. Use extload, sextload and zextload (see below) +// which pass in a dummy srcvalue node which tblgen will skip over. +def loadx : SDNode<"ISD::LOADX" , SDTLoadX, [SDNPHasChain]>; def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; @@ -415,12 +413,12 @@ def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; // extending load & truncstore fragments. +def extload : PatFrag<(ops node:$ptr, node:$vt), + (loadx node:$ptr, srcvalue:$dummy, node:$vt, 0)>; def sextload : PatFrag<(ops node:$ptr, node:$vt), - (sextld node:$ptr, srcvalue:$dummy, node:$vt)>; + (loadx node:$ptr, srcvalue:$dummy, node:$vt, 1)>; def zextload : PatFrag<(ops node:$ptr, node:$vt), - (zextld node:$ptr, srcvalue:$dummy, node:$vt)>; -def extload : PatFrag<(ops node:$ptr, node:$vt), - (extld node:$ptr, srcvalue:$dummy, node:$vt)>; + (loadx node:$ptr, srcvalue:$dummy, node:$vt, 2)>; def truncstore : PatFrag<(ops node:$val, node:$ptr, node:$vt), (truncst node:$val, node:$ptr, srcvalue:$dummy, node:$vt)>; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 24fe64d7988..6ab7c98b4a0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -75,6 +75,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) if (Subtarget->is64Bit()) addRegisterClass(MVT::i64, X86::GR64RegisterClass); + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); + // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this // operation. setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); @@ -155,7 +157,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); - setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand); setOperationAction(ISD::CTPOP , MVT::i8 , Expand); |
