diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SILowerI1Copies.cpp | 6 |
2 files changed, 11 insertions, 5 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 7663b2e0a20..4257f4e39bf 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1521,6 +1521,11 @@ def V_OR_I1 : InstSI < [(set i1:$dst, (or i1:$src0, i1:$src1))] >; +def V_XOR_I1 : InstSI < + (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "", + [(set i1:$dst, (xor i1:$src0, i1:$src1))] +>; + // SI pseudo instructions. These are used by the CFG structurizer pass // and should be lowered to ISA instructions prior to codegen. @@ -1786,11 +1791,6 @@ let Predicates = [isSI] in { // SOP2 Patterns //===----------------------------------------------------------------------===// -def : Pat < - (i1 (xor i1:$src0, i1:$src1)), - (S_XOR_B64 $src0, $src1) ->; - //===----------------------------------------------------------------------===// // SOPP Patterns //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/R600/SILowerI1Copies.cpp b/llvm/lib/Target/R600/SILowerI1Copies.cpp index 738c90b30e5..db19235995b 100644 --- a/llvm/lib/Target/R600/SILowerI1Copies.cpp +++ b/llvm/lib/Target/R600/SILowerI1Copies.cpp @@ -102,6 +102,12 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) { continue; } + if (MI.getOpcode() == AMDGPU::V_XOR_I1) { + I1Defs.push_back(MI.getOperand(0).getReg()); + MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32)); + continue; + } + if (MI.getOpcode() != AMDGPU::COPY || !TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()) || !TargetRegisterInfo::isVirtualRegister(MI.getOperand(1).getReg())) |
