diff options
Diffstat (limited to 'llvm/lib/Target')
17 files changed, 20 insertions, 13 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 8314b4a490f..05b714f924b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -351,7 +351,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_SHL: if (isSALUMapping(MI)) return getDefaultMappingSOP(MI); - // Fall-through + LLVM_FALLTHROUGH; case AMDGPU::G_FADD: case AMDGPU::G_FPTOSI: diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp index 478a473a51b..7769a35aadc 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp @@ -236,6 +236,7 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { // MI will become a KILL, don't considers it in scheduling return AluDiscarded; } + break; default: break; } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index e41cf6e771b..66eb9bbb84c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5049,12 +5049,11 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::r600_read_tgid_z: return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::WORKGROUP_ID_Z); - case Intrinsic::amdgcn_workitem_id_x: { + case Intrinsic::amdgcn_workitem_id_x: case Intrinsic::r600_read_tidig_x: return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32, SDLoc(DAG.getEntryNode()), MFI->getArgInfo().WorkItemIDX); - } case Intrinsic::amdgcn_workitem_id_y: case Intrinsic::r600_read_tidig_y: return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32, diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp index 496f2befde5..8890fb8adf4 100644 --- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp +++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp @@ -357,8 +357,8 @@ BPFAsmParser::parseOperandAsOperator(OperandVector &Operands) { case AsmToken::Plus: { if (getLexer().peekTok().is(AsmToken::Integer)) return MatchOperand_NoMatch; + LLVM_FALLTHROUGH; } - // Fall through. case AsmToken::Equal: case AsmToken::Greater: diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index 424be5e4476..ba9f638796e 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1208,6 +1208,7 @@ void HCE::recordExtender(MachineInstr &MI, unsigned OpNum) { case Hexagon::S4_subaddi: // (__: ## - Rs<<0) ED.Expr.Rs = MI.getOperand(OpNum+1); ED.Expr.Neg = true; + break; default: // (__: ## + __<<_) break; } diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 8f22a71dc1f..fa192391313 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -2463,6 +2463,7 @@ APInt HexagonConstEvaluator::getCmpImm(unsigned Opc, unsigned OpX, case Hexagon::A4_cmpheqi: // s8 case Hexagon::C4_cmpneqi: // s8 Signed = true; + break; case Hexagon::A4_cmpbeqi: // u8 break; case Hexagon::C2_cmpgtui: // u9 diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 9a66aece579..470b05bda4c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1547,6 +1547,7 @@ bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits, return true; } } + break; } default: break; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index ebfe21bd17d..908ce24136c 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -105,6 +105,7 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { default: if (!ResourcesModel->canReserveResources(*SU->getInstr())) return false; + break; case TargetOpcode::EXTRACT_SUBREG: case TargetOpcode::INSERT_SUBREG: case TargetOpcode::SUBREG_TO_REG: diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 93b5bedbb38..722699907ca 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1568,6 +1568,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { if (GlueAllocframeStore) continue; } + break; default: break; } diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 2e70d35fc4a..79e0c001a63 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -767,13 +767,13 @@ public: ~MipsOperand() override { switch (Kind) { - case k_Immediate: - break; case k_Memory: delete Mem.Base; break; case k_RegList: delete RegList.List; + break; + case k_Immediate: case k_RegisterIndex: case k_Token: break; diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 2e0c25de2bc..a19c97e2ef0 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -561,6 +561,7 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, O << '$' << MipsInstPrinter::getRegisterName(Reg); return false; } + break; } case 'w': // Print MSA registers for the 'f' constraint diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index cf2899dd375..f030f83295d 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -244,7 +244,7 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); break; } - // fallthrough + LLVM_FALLTHROUGH; case Mips::BuildPairF64: case Mips::ExtractElementF64: if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1()) diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp index f212894035d..668169839e7 100644 --- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -903,7 +903,7 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2, case MVT::i8: case MVT::i16: NeedsExt = true; - // Intentional fall-through. + LLVM_FALLTHROUGH; case MVT::i32: if (!UseImm) CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4ed110e6663..c6f0212ab40 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3970,7 +3970,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4( assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"); - /* fall through */ + LLVM_FALLTHROUGH; case MVT::v4f64: case MVT::v4i1: @@ -6113,7 +6113,7 @@ SDValue PPCTargetLowering::LowerCall_64SVR4( assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"); - /* fall through */ + LLVM_FALLTHROUGH; case MVT::v4f64: case MVT::v4i1: { bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32; diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index c8474b15b18..0d2c2389847 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -1308,7 +1308,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) { return false; case SystemZISD::SSUBO: NegateOperand = true; - /* fall through */ + LLVM_FALLTHROUGH; case SystemZISD::SADDO: if (MemVT == MVT::i32) NewOpc = SystemZ::ASI; @@ -1319,7 +1319,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) { break; case SystemZISD::USUBO: NegateOperand = true; - /* fall through */ + LLVM_FALLTHROUGH; case SystemZISD::UADDO: if (MemVT == MVT::i32) NewOpc = SystemZ::ALSI; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 5611a1b4588..00e37a4af29 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -447,6 +447,7 @@ unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V, (isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr())) return copyValue(Reg); } + break; case MVT::i8: case MVT::i16: break; diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp index b6320bd0612..54d550b6065 100644 --- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp @@ -1393,7 +1393,7 @@ static int readModRM(struct InternalInstruction* insn) { break; case 0x1: insn->displacementSize = 1; - /* FALLTHROUGH */ + LLVM_FALLTHROUGH; case 0x2: insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); switch (rm & 7) { |
