diff options
Diffstat (limited to 'llvm/lib/Target')
54 files changed, 114 insertions, 104 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 609b4c47daf..0d100977d2d 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -272,7 +272,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum, const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).Name; else assert(0 && "not implemented"); @@ -392,7 +392,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << TM.getRegisterInfo()->get(MO1.getReg()).Name; // Print the shift opc. @@ -401,7 +401,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { << " "; if (MO2.getReg()) { - assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); O << TM.getRegisterInfo()->get(MO2.getReg()).Name; assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); } else { @@ -468,7 +468,7 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name; if (MO2.getReg()) { @@ -532,7 +532,7 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, return; } - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); if (Modifier && strcmp(Modifier, "submode") == 0) { ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm()); @@ -569,7 +569,7 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, } const MachineOperand &MO1 = MI->getOperand(Op); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]"; } diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index 2105f14d3a3..62ea102ad5d 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -134,7 +134,7 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) { intptr_t rv = 0; const MachineOperand &MO = MI.getOperand(OpIndex); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())); rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); } else if (MO.isImmediate()) { rv = MO.getImm(); @@ -478,7 +478,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) if(IsShiftByRegister) { // set the value of bit[11:8] (register Rs). - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg()); assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); Value |= op << ARMII::RegRsShift; @@ -540,7 +540,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { // set bit I(25), because this is not in immediate enconding. Value |= 1 << ARMII::I_BitShift; - assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); // set bit[3:0] to the corresponding Rm register Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); @@ -640,7 +640,8 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MOR = MI.getOperand(i); unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg()); - assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16); + assert(TargetRegisterInfo::isPhysicalRegister(MOR.getReg()) && + RegNumber < 16); Value |= 0x1 << RegNumber; } diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index 4d1819de873..30c1742ff77 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -282,7 +282,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); if (MO.isDef()) { diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h index 31216e49eba..4ce90fc5664 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMInstrInfo.h @@ -134,7 +134,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 6c99c3af341..5eeeafbac1c 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -26,7 +26,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/Compiler.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -42,7 +42,7 @@ namespace { ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {} const TargetInstrInfo *TII; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; ARMFunctionInfo *AFI; RegScavenger *RS; @@ -755,7 +755,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { const TargetMachine &TM = Fn.getTarget(); AFI = Fn.getInfo<ARMFunctionInfo>(); TII = TM.getInstrInfo(); - MRI = TM.getRegisterInfo(); + TRI = TM.getRegisterInfo(); RS = new RegScavenger(); bool Modified = false; diff --git a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h index aa269e32a65..eeb61d76860 100644 --- a/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h +++ b/llvm/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -16,7 +16,7 @@ #include "ARMSubtarget.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/BitVector.h" diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp index b3f6d945a36..dccc77f7f61 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of the MRegisterInfo class. +// This file contains the ARM implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.h b/llvm/lib/Target/ARM/ARMRegisterInfo.h index cf18e86f33d..90def1f172d 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.h +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of the MRegisterInfo class. +// This file contains the ARM implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef ARMREGISTERINFO_H #define ARMREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "ARMGenRegisterInfo.h.inc" namespace llvm { diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td index 233cc245170..61c77e64acf 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.td +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td @@ -157,7 +157,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, GPRClass::iterator GPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); GPRClass::iterator I; if (Subtarget.isThumb()) diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h index 4bdfd48cec0..84416d6b0e2 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.h +++ b/llvm/lib/Target/ARM/ARMTargetMachine.h @@ -41,7 +41,7 @@ public: virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual TargetJITInfo *getJITInfo() { return &JITInfo; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } diff --git a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp index 03ed3d6b68f..067a8efb3ce 100644 --- a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp +++ b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp @@ -75,7 +75,8 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Register) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImm(); @@ -87,7 +88,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index d20e1f7fb12..cf646efcda5 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -261,7 +261,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, VarArgsOffset = (Op.Val->getNumValues()-1) * 8; std::vector<SDOperand> LS; for (int i = 0; i < 6; ++i) { - if (MRegisterInfo::isPhysicalRegister(args_int[i])) + if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); @@ -269,7 +269,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); - if (MRegisterInfo::isPhysicalRegister(args_float[i])) + if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.h b/llvm/lib/Target/Alpha/AlphaInstrInfo.h index 20d6388e737..0b51f2d3220 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.h +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.h @@ -28,7 +28,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index d749d35b4fc..c9a87dc0109 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h index 7a32bf58913..74037f59251 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef ALPHAREGISTERINFO_H #define ALPHAREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "AlphaGenRegisterInfo.h.inc" namespace llvm { diff --git a/llvm/lib/Target/Alpha/AlphaTargetMachine.h b/llvm/lib/Target/Alpha/AlphaTargetMachine.h index 0399d1a19a0..5c74181880a 100644 --- a/llvm/lib/Target/Alpha/AlphaTargetMachine.h +++ b/llvm/lib/Target/Alpha/AlphaTargetMachine.h @@ -43,7 +43,7 @@ public: virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual TargetLowering* getTargetLowering() const { diff --git a/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp b/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp index e5e7d04fda1..b62bf62d3df 100644 --- a/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp +++ b/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp @@ -31,7 +31,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" @@ -73,14 +73,15 @@ namespace { /// void printRegister(const MachineOperand &MO, bool R0AsZero) { unsigned RegNo = MO.getReg(); - assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && + "Not physreg??"); O << TM.getRegisterInfo()->get(RegNo).Name; } void printOperand(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImm(); diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.h b/llvm/lib/Target/CellSPU/SPUInstrInfo.h index 39237eef61b..c5fe811f6e5 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.h +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.h @@ -30,7 +30,7 @@ namespace llvm { /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp index 39edccb606e..4a607558141 100644 --- a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Cell implementation of the MRegisterInfo class. +// This file contains the Cell implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.h b/llvm/lib/Target/CellSPU/SPURegisterInfo.h index aa2f036e106..f54c11159cd 100644 --- a/llvm/lib/Target/CellSPU/SPURegisterInfo.h +++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.h @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Cell SPU implementation of the MRegisterInfo class. +// This file contains the Cell SPU implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.h b/llvm/lib/Target/CellSPU/SPUTargetMachine.h index 8d05ab9d74c..6f1cabbd815 100644 --- a/llvm/lib/Target/CellSPU/SPUTargetMachine.h +++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.h @@ -70,7 +70,7 @@ public: return const_cast<SPUTargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } diff --git a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp index c6d662678b4..4efc6727662 100644 --- a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp +++ b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp @@ -53,7 +53,8 @@ namespace { void printOperand(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); if (MO.getType() == MachineOperand::MO_Register) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physref??"); //XXX Bug Workaround: See note in Printer::doInitialization about %. O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { @@ -164,7 +165,7 @@ bool IA64AsmPrinter::runOnMachineFunction(MachineFunction &MF) { void IA64AsmPrinter::printOp(const MachineOperand &MO, bool isBRCALLinsn /* = false */) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: O << RI.get(MO.getReg()).Name; diff --git a/llvm/lib/Target/IA64/IA64InstrInfo.h b/llvm/lib/Target/IA64/IA64InstrInfo.h index 0508973f9b7..e5da6f1e25a 100644 --- a/llvm/lib/Target/IA64/IA64InstrInfo.h +++ b/llvm/lib/Target/IA64/IA64InstrInfo.h @@ -28,7 +28,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } // // Return true if the instruction is a register to register move and diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp index dae53d026d8..2204873befb 100644 --- a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the IA64 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on IA64. +// This file contains the IA64 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on IA64. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.h b/llvm/lib/Target/IA64/IA64RegisterInfo.h index 6e682e3eefd..510f7712328 100644 --- a/llvm/lib/Target/IA64/IA64RegisterInfo.h +++ b/llvm/lib/Target/IA64/IA64RegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the IA64 implementation of the MRegisterInfo class. +// This file contains the IA64 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef IA64REGISTERINFO_H #define IA64REGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "IA64GenRegisterInfo.h.inc" namespace llvm { class llvm::Type; } diff --git a/llvm/lib/Target/IA64/IA64TargetMachine.h b/llvm/lib/Target/IA64/IA64TargetMachine.h index 2831ea944ce..5b320c2e96c 100644 --- a/llvm/lib/Target/IA64/IA64TargetMachine.h +++ b/llvm/lib/Target/IA64/IA64TargetMachine.h @@ -40,7 +40,7 @@ public: virtual IA64TargetLowering *getTargetLowering() const { return const_cast<IA64TargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 28cbdea1526..872e51cc88d 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -162,7 +162,7 @@ emitFMaskDirective(MachineFunction &MF) void MipsAsmPrinter:: emitFrameDirective(MachineFunction &MF) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned stackReg = RI.getFrameRegister(MF); unsigned returnReg = RI.getRARegister(); @@ -195,7 +195,7 @@ emitSetDirective(SetDirectiveFlags Flag) unsigned int MipsAsmPrinter:: getSavedRegsBitmask(bool isFloat, MachineFunction &MF) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); // Float Point Registers, TODO if (isFloat) @@ -323,7 +323,7 @@ void MipsAsmPrinter:: printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); bool closeP = false; bool isPIC = (TM.getRelocationModel() == Reloc::PIC_); bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large); @@ -364,7 +364,7 @@ printOperand(const MachineInstr *MI, int opNum) switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << "$" << LowercaseString (RI.get(MO.getReg()).Name); else O << "$" << MO.getReg(); diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index d894b208a08..a186f2cd796 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -52,7 +52,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index e4dabc0b9cb..4ca5adea036 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the MIPS implementation of the MRegisterInfo class. +// This file contains the MIPS implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.h b/llvm/lib/Target/Mips/MipsRegisterInfo.h index 2181cdf3821..e491a953104 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.h +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Mips implementation of the MRegisterInfo class. +// This file contains the Mips implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef MIPSREGISTERINFO_H #define MIPSREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "MipsGenRegisterInfo.h.inc" namespace llvm { diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h index 859387e359c..d974d3c0cf6 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.h +++ b/llvm/lib/Target/Mips/MipsTargetMachine.h @@ -44,7 +44,7 @@ namespace llvm { virtual const TargetData *getTargetData() const { return &DataLayout;} - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 95825bb217e..71ce14708cc 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -37,7 +37,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" @@ -105,7 +105,7 @@ namespace { /// void printRegister(const MachineOperand &MO, bool R0AsZero) { unsigned RegNo = MO.getReg(); - assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); // If we should use 0 for R0. if (R0AsZero && RegNo == PPC::R0) { diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 09fef251964..f4aaaadd184 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -225,7 +225,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // by the scheduler. Detect them now. MachineFunction &Fn = MachineFunction::get(&F); bool HasVectorVReg = false; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = RegInfo->getLastVirtReg()+1; i != e; ++i) if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { HasVectorVReg = true; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index 9f289e4ff83..5836d1fa5ec 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -71,7 +71,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index efed0727860..a21abe5810c 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PowerPC implementation of the MRegisterInfo class. +// This file contains the PowerPC implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h index 2a84fc22efa..fc17b0209cc 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PowerPC implementation of the MRegisterInfo class. +// This file contains the PowerPC implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h index 769e137f1de..1d76d15f5a0 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -51,7 +51,7 @@ public: virtual PPCTargetLowering *getTargetLowering() const { return const_cast<PPCTargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index 12eae8ab955..b95acddc738 100644 --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -132,7 +132,7 @@ bool SparcAsmPrinter::runOnMachineFunction(MachineFunction &MF) { void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand (opNum); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); bool CloseParen = false; if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) { O << "%hi("; @@ -144,7 +144,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { } switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << "%" << LowercaseString (RI.get(MO.getReg()).Name); else O << "%reg" << MO.getReg(); diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index 14c3b4a254f..22b2dcd5916 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -41,7 +41,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index 6b93c686a99..cd50ad1dc1f 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the SPARC implementation of the MRegisterInfo class. +// This file contains the SPARC implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.h b/llvm/lib/Target/Sparc/SparcRegisterInfo.h index 2235de1a6e5..fe2c8eec0bb 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.h +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Sparc implementation of the MRegisterInfo class. +// This file contains the Sparc implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef SPARCREGISTERINFO_H #define SPARCREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "SparcGenRegisterInfo.h.inc" namespace llvm { diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h index 61588e8d5ee..0da92935c28 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.h +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -39,7 +39,7 @@ public: virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } diff --git a/llvm/lib/Target/MRegisterInfo.cpp b/llvm/lib/Target/TargetRegisterInfo.cpp index 8c022cfca09..11f1b3d070f 100644 --- a/llvm/lib/Target/MRegisterInfo.cpp +++ b/llvm/lib/Target/TargetRegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- MRegisterInfo.cpp - Target Register Information Implementation -----===// +//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// // // The LLVM Compiler Infrastructure // @@ -7,12 +7,12 @@ // //===----------------------------------------------------------------------===// // -// This file implements the MRegisterInfo interface. +// This file implements the TargetRegisterInfo interface. // //===----------------------------------------------------------------------===// #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -20,7 +20,7 @@ using namespace llvm; -MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, regclass_iterator RCB, regclass_iterator RCE, int CFSO, int CFDO) : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { @@ -31,12 +31,12 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, CallFrameDestroyOpcode = CFDO; } -MRegisterInfo::~MRegisterInfo() {} +TargetRegisterInfo::~TargetRegisterInfo() {} /// getPhysicalRegisterRegClass - Returns the Register Class of a physical /// register. const TargetRegisterClass * -MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, +TargetRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, unsigned reg) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the register class of the right type that contains this physreg. @@ -57,15 +57,15 @@ static void getAllocatableSetForRC(MachineFunction &MF, R.set(*I); } -BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, - const TargetRegisterClass *RC) const { +BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC) const { BitVector Allocatable(NumRegs); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); return Allocatable; } - for (MRegisterInfo::regclass_iterator I = regclass_begin(), + for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) getAllocatableSetForRC(MF, *I, Allocatable); return Allocatable; @@ -74,7 +74,7 @@ BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, /// getFrameIndexOffset - Returns the displacement from the frame register to /// the stack frame of the specified index. This is the default implementation /// which is likely incorrect for the target. -int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { +int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->getObjectOffset(FI) + MFI->getStackSize() - @@ -84,7 +84,7 @@ int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to a function. void -MRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const { +TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const { // Default is to do nothing. } diff --git a/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp b/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp index a5b1b796e1f..d315bb43b90 100644 --- a/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp +++ b/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp @@ -216,10 +216,10 @@ static inline bool printStub(TargetMachine &TM, const X86Subtarget* ST) { void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier, bool NotRIPRel) { const MachineOperand &MO = MI->getOperand(OpNo); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); O << '%'; unsigned Reg = MO.getReg(); @@ -553,7 +553,7 @@ void X86ATTAsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI, bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, const char Mode) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 0703563f011..53de9d86447 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -569,7 +569,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { const TargetRegisterClass *clas; for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() && - MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && + TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == X86::RFP32RegisterClass || clas == X86::RFP64RegisterClass || diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e4454709ae8..f131c57c971 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1051,7 +1051,7 @@ static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op) { if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || (Op.getOpcode()== ISD::CopyFromReg && (OpReg = cast<RegisterSDNode>(Op.getOperand(1))) && - OpReg->getReg() >= MRegisterInfo::FirstVirtualRegister)) + OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) return true; return false; } diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 6bf76afd642..b14e3dc24e5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -445,7 +445,7 @@ namespace llvm { /// Subtarget - Keep a pointer to the X86Subtarget around so that we can /// make the right decision when generating code for different targets. const X86Subtarget *Subtarget; - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; /// X86StackPtr - X86 physical register used as stack ptr. unsigned X86StackPtr; diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 4a62e9e2fcf..7a1ab51fc38 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -17,7 +17,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "X86RegisterInfo.h" #include "llvm/ADT/IndexedMap.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { class X86RegisterInfo; @@ -245,7 +245,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } // Return true if the instruction is a register to register move and // leave the source and dest operands in the passed parameters. diff --git a/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp b/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp index 029533e9a60..804790d45b8 100644 --- a/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp +++ b/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp @@ -114,10 +114,10 @@ void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) { void X86IntelAsmPrinter::printOp(const MachineOperand &MO, const char *Modifier) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: { - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ? @@ -252,7 +252,7 @@ void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) { bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO, const char Mode) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. diff --git a/llvm/lib/Target/X86/X86IntelAsmPrinter.h b/llvm/lib/Target/X86/X86IntelAsmPrinter.h index f8dd6bc6ab3..8e7a31c92e4 100644 --- a/llvm/lib/Target/X86/X86IntelAsmPrinter.h +++ b/llvm/lib/Target/X86/X86IntelAsmPrinter.h @@ -16,7 +16,7 @@ #include "X86AsmPrinter.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { @@ -41,7 +41,8 @@ struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public X86SharedAsmPrinter { const char *Modifier = 0) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { printOp(MO, Modifier); diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 931df4dcb50..10a0eec562e 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on X86. +// This file contains the X86 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on X86. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h index 02f237d06cb..8b010a92404 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.h +++ b/llvm/lib/Target/X86/X86RegisterInfo.h @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. +// This file contains the X86 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// @@ -16,7 +16,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "X86GenRegisterInfo.h.inc" namespace llvm { diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index 42c7ce7806d..9d70618f8fc 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -249,7 +249,7 @@ def GR8 : RegisterClass<"X86", [i8], 8, GR8Class::iterator GR8Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (!Subtarget.is64Bit()) return X86_GR8_AO_32; @@ -262,7 +262,7 @@ def GR8 : RegisterClass<"X86", [i8], 8, GR8Class::iterator GR8Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (!Subtarget.is64Bit()) return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned)); @@ -303,7 +303,7 @@ def GR16 : RegisterClass<"X86", [i16], 16, GR16Class::iterator GR16Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -321,7 +321,7 @@ def GR16 : RegisterClass<"X86", [i16], 16, GR16Class::iterator GR16Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -367,7 +367,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -385,7 +385,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, GR32Class::iterator GR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -414,7 +414,7 @@ def GR64 : RegisterClass<"X86", [i64], 64, GR64Class::iterator GR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? return end()-2; // If so, don't allocate RSP or RBP else diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 58c96979e44..e9148b5a52e 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -49,7 +49,7 @@ public: virtual X86TargetLowering *getTargetLowering() const { return const_cast<X86TargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } |
