diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 40 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 |
5 files changed, 38 insertions, 38 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index d84f260446c..52aa8bb3eb8 100644 --- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -199,7 +199,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { int FI = cast<FrameIndexSDNode>(N)->getIndex(); return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i32), - getI64Imm(0)).Val; + getI64Imm(0)); } case AlphaISD::GlobalBaseReg: { SDOperand Result = getGlobalBaseReg(); @@ -231,7 +231,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, SDOperand(CNode, 1)); - return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain).Val; + return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain); } case ISD::READCYCLECOUNTER: { @@ -268,7 +268,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, - CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()).Val; + CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()); } case ISD::TargetConstantFP: { ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N); @@ -277,11 +277,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) { if (CN->isExactlyValue(+0.0)) { return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, T, CurDAG->getRegister(Alpha::F31, T), - CurDAG->getRegister(Alpha::F31, T)).Val; + CurDAG->getRegister(Alpha::F31, T)); } else if ( CN->isExactlyValue(-0.0)) { return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, T, CurDAG->getRegister(Alpha::F31, T), - CurDAG->getRegister(Alpha::F31, T)).Val; + CurDAG->getRegister(Alpha::F31, T)); } else { abort(); } diff --git a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp index b384705e512..3948c535409 100644 --- a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -408,10 +408,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { int FI = cast<FrameIndexSDNode>(N)->getIndex(); if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i64)).Val; + CurDAG->getTargetFrameIndex(FI, MVT::i64)); else - return SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0).Val; + return CurDAG->getTargetNode(IA64::MOV, MVT::i64, + CurDAG->getTargetFrameIndex(FI, MVT::i64)); } case ISD::ConstantPool: { // TODO: nuke the constant pool @@ -464,7 +464,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), CurDAG->getRegister(IA64::r0, MVT::i64), - Chain).getValue(Op.ResNo).Val; + Chain); } /* otherwise, we want to load a bool into something bigger: LD1 will do that for us, so we just fall through */ @@ -480,7 +480,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { // TODO: comment this return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other, - Address, Chain).getValue(Op.ResNo).Val; + Address, Chain); } case ISD::TRUNCSTORE: @@ -505,7 +505,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, CurDAG->getConstant(1, MVT::i64), Tmp), 0); - return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain).Val; + return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain); } case MVT::i64: Opc = IA64::ST8; break; case MVT::f64: Opc = IA64::STF8; break; @@ -524,7 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { SDOperand N2 = N->getOperand(2); AddToISelQueue(N1); AddToISelQueue(N2); - return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val; + return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain); } case ISD::BRCOND: { @@ -536,7 +536,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock(); //FIXME - we do NOT need long branches all the time return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, - CurDAG->getBasicBlock(Dest), Chain).Val; + CurDAG->getBasicBlock(Dest), Chain); } case ISD::CALLSEQ_START: @@ -546,7 +546,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP; SDOperand N0 = N->getOperand(0); AddToISelQueue(N0); - return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0).Val; + return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0); } case ISD::BR: @@ -554,7 +554,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { SDOperand N0 = N->getOperand(0); AddToISelQueue(N0); return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, - N->getOperand(1), N0).Val; + N->getOperand(1), N0); } return SelectCode(Op); diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 22752abed09..507a2a3cc9d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -812,23 +812,23 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { case ISD::SETEQ: Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27), - getI32Imm(5), getI32Imm(31)).Val; + getI32Imm(5), getI32Imm(31)); case ISD::SETNE: { SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)), 0); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, - AD.getValue(1)).Val; + AD.getValue(1)); } case ISD::SETLT: return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1), - getI32Imm(31), getI32Imm(31)).Val; + getI32Imm(31), getI32Imm(31)); case ISD::SETGT: { SDOperand T = SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1), - getI32Imm(31), getI32Imm(31)).Val; + getI32Imm(31), getI32Imm(31)); } } } else if (Imm == ~0U) { // setcc op, -1 @@ -842,13 +842,13 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0)), 0), - Op.getValue(1)).Val; + Op.getValue(1)); case ISD::SETNE: { Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), - Op, SDOperand(AD, 1)).Val; + Op, SDOperand(AD, 1)); } case ISD::SETLT: { SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, @@ -856,14 +856,14 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op), 0); return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1), - getI32Imm(31), getI32Imm(31)).Val; + getI32Imm(31), getI32Imm(31)); } case ISD::SETGT: Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1), getI32Imm(31), getI32Imm(31)), 0); return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, - getI32Imm(1)).Val; + getI32Imm(1)); } } } @@ -889,13 +889,13 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { if (!Inv) { return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR, getI32Imm((32-(3-Idx)) & 31), - getI32Imm(31), getI32Imm(31)).Val; + getI32Imm(31), getI32Imm(31)); } else { SDOperand Tmp = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31),getI32Imm(31)), 0); - return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)).Val; + return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); } } @@ -921,7 +921,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, - getSmallIPtrImm(0)).Val; + getSmallIPtrImm(0)); return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI, getSmallIPtrImm(0)); } @@ -952,7 +952,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, N0, getI32Imm(Log2_32(Imm))); return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, - SDOperand(Op, 0), SDOperand(Op, 1)).Val; + SDOperand(Op, 0), SDOperand(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, @@ -961,7 +961,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, SDOperand(Op, 0), SDOperand(Op, 1)), 0); - return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT).Val; + return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); } } @@ -992,7 +992,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { } return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH), getI32Imm(MB), - getI32Imm(ME)).Val; + getI32Imm(ME)); } // ISD::OR doesn't get all the bitfield insertion fun. // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert @@ -1029,7 +1029,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), - getI32Imm(ME)).Val; + getI32Imm(ME)); } // Other cases are autogenerated. @@ -1043,7 +1043,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), - getI32Imm(ME)).Val; + getI32Imm(ME)); } // Other cases are autogenerated. @@ -1066,7 +1066,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { N->getOperand(0), getI32Imm(~0U)); return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(Tmp, 0), N->getOperand(0), - SDOperand(Tmp, 1)).Val; + SDOperand(Tmp, 1)); } SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); @@ -1089,7 +1089,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { AddToISelQueue(N->getOperand(3)); return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg, N->getOperand(2), N->getOperand(3), - getI32Imm(BROpc)).Val; + getI32Imm(BROpc)); } case ISD::BR_CC: { AddToISelQueue(N->getOperand(0)); @@ -1097,7 +1097,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode, getI32Imm(getBCCForSetCC(CC)), - N->getOperand(4), N->getOperand(0)).Val; + N->getOperand(4), N->getOperand(0)); } case ISD::BRIND: { // FIXME: Should custom lower this. @@ -1108,7 +1108,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target, Chain), 0); - return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain).Val; + return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); } // FIXME: These are manually selected because tblgen isn't handling varargs // nodes correctly. diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 7c298c78e5a..a30e7394207 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -1093,7 +1093,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { // FIXME: Handle div by immediate. unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, - TopPart).Val; + TopPart); } case ISD::MULHU: case ISD::MULHS: { @@ -1106,7 +1106,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. - return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)).Val; + return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); return NULL; } } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 6ec294c3f3a..572001151a5 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -658,7 +658,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { } if (C.Val) - return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val; + return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C); } // Other cases are handled by auto-generated code. |
