diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/TargetSubtargetInfo.cpp | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 904cb53cb8e..54f53dc14b2 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -723,7 +723,7 @@ namespace { class AArch64ConditionalCompares : public MachineFunctionPass { const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; - const MCSchedModel *SchedModel; + MCSchedModel SchedModel; // Does the proceeded function has Oz attribute. bool MinSize; MachineRegisterInfo *MRI; @@ -845,7 +845,7 @@ bool AArch64ConditionalCompares::shouldConvert() { // the cost of a misprediction. // // Set a limit on the delay we will accept. - unsigned DelayLimit = SchedModel->MispredictPenalty * 3 / 4; + unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4; // Instruction depths can be computed for all trace instructions above CmpBB. unsigned HeadDepth = diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp index 23778d4eeb1..0c36e8f2926 100644 --- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp +++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp @@ -123,7 +123,7 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) { MRI = &MF->getRegInfo(); const TargetSubtargetInfo &ST = MF->getTarget().getSubtarget<TargetSubtargetInfo>(); - SchedModel.init(*ST.getSchedModel(), &ST, TII); + SchedModel.init(ST.getSchedModel(), &ST, TII); Traces = &getAnalysis<MachineTraceMetrics>(); MinInstr = nullptr; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 25f2316a555..0a193ee2d1a 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -415,7 +415,7 @@ ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, } unsigned ARMSubtarget::getMispredictionPenalty() const { - return SchedModel->MispredictPenalty; + return SchedModel.MispredictPenalty; } bool ARMSubtarget::hasSinCos() const { diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 8b40f2f1932..05102b339d0 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -219,7 +219,7 @@ protected: Triple TargetTriple; /// SchedModel - Processor specific instruction costs. - const MCSchedModel *SchedModel; + MCSchedModel SchedModel; /// Selected instruction itineraries (one entry per itinerary class.) InstrItineraryData InstrItins; diff --git a/llvm/lib/Target/TargetSubtargetInfo.cpp b/llvm/lib/Target/TargetSubtargetInfo.cpp index 23c038fff66..10597a84bca 100644 --- a/llvm/lib/Target/TargetSubtargetInfo.cpp +++ b/llvm/lib/Target/TargetSubtargetInfo.cpp @@ -53,7 +53,7 @@ bool TargetSubtargetInfo::enableRALocalReassignment( } bool TargetSubtargetInfo::enablePostMachineScheduler() const { - return getSchedModel()->PostRAScheduler; + return getSchedModel().PostRAScheduler; } bool TargetSubtargetInfo::useAA() const { |
