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-rw-r--r--llvm/lib/Target/ARM/ARMInstrMVE.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index b4a7a139229..cd670819fad 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4928,6 +4928,13 @@ let Predicates = [HasMVEInt] in {
(v8i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
def : Pat<(v4i1 (load t2addrmode_imm7<2>:$addr)),
(v4i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
+
+ def : Pat<(store (v4i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
+ (VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
+ def : Pat<(store (v8i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
+ (VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
+ def : Pat<(store (v16i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
+ (VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
}
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