diff options
Diffstat (limited to 'llvm/lib/Target')
19 files changed, 61 insertions, 69 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index a95476b9118..452fbd3488b 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -377,11 +377,10 @@ bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) { // Now we have a set of sets, order them by start address so // we can iterate over them sequentially. - llvm::sort(V.begin(), V.end(), - [](const std::vector<Chain*> &A, - const std::vector<Chain*> &B) { - return A.front()->startsBefore(B.front()); - }); + llvm::sort(V, + [](const std::vector<Chain *> &A, const std::vector<Chain *> &B) { + return A.front()->startsBefore(B.front()); + }); // As we only have two colors, we can track the global (BB-level) balance of // odds versus evens. We aim to keep this near zero to keep both execution @@ -453,16 +452,16 @@ bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV, // change them to! // Final tie-break with instruction order so pass output is stable (i.e. not // dependent on malloc'd pointer values). - llvm::sort(GV.begin(), GV.end(), [](const Chain *G1, const Chain *G2) { - if (G1->size() != G2->size()) - return G1->size() > G2->size(); - if (G1->requiresFixup() != G2->requiresFixup()) - return G1->requiresFixup() > G2->requiresFixup(); - // Make sure startsBefore() produces a stable final order. - assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) && - "Starts before not total order!"); - return G1->startsBefore(G2); - }); + llvm::sort(GV, [](const Chain *G1, const Chain *G2) { + if (G1->size() != G2->size()) + return G1->size() > G2->size(); + if (G1->requiresFixup() != G2->requiresFixup()) + return G1->requiresFixup() > G2->requiresFixup(); + // Make sure startsBefore() produces a stable final order. + assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) && + "Starts before not total order!"); + return G1->startsBefore(G2); + }); Color PreferredColor = Parity < 0 ? Color::Even : Color::Odd; while (Chain *G = getAndEraseNext(PreferredColor, GV)) { diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index 15366d66bd8..8e4cc391dc2 100644 --- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -434,8 +434,7 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule, // Sort recorded regions by pressure - highest at the front void GCNIterativeScheduler::sortRegionsByPressure(unsigned TargetOcc) { const auto &ST = MF.getSubtarget<GCNSubtarget>(); - llvm::sort(Regions.begin(), Regions.end(), - [&ST, TargetOcc](const Region *R1, const Region *R2) { + llvm::sort(Regions, [&ST, TargetOcc](const Region *R1, const Region *R2) { return R2->MaxPressure.less(ST, R1->MaxPressure, TargetOcc); }); } diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp index cd14239de82..aa976d5141f 100644 --- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp +++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp @@ -168,16 +168,15 @@ void SIFormMemoryClauses::forAllLanes(unsigned Reg, LaneBitmask LaneMask, CoveringSubregs.push_back(Idx); } - llvm::sort(CoveringSubregs.begin(), CoveringSubregs.end(), - [this](unsigned A, unsigned B) { - LaneBitmask MaskA = TRI->getSubRegIndexLaneMask(A); - LaneBitmask MaskB = TRI->getSubRegIndexLaneMask(B); - unsigned NA = MaskA.getNumLanes(); - unsigned NB = MaskB.getNumLanes(); - if (NA != NB) - return NA > NB; - return MaskA.getHighestLane() > MaskB.getHighestLane(); - }); + llvm::sort(CoveringSubregs, [this](unsigned A, unsigned B) { + LaneBitmask MaskA = TRI->getSubRegIndexLaneMask(A); + LaneBitmask MaskB = TRI->getSubRegIndexLaneMask(B); + unsigned NA = MaskA.getNumLanes(); + unsigned NB = MaskB.getNumLanes(); + if (NA != NB) + return NA > NB; + return MaskA.getHighestLane() > MaskB.getHighestLane(); + }); for (unsigned Idx : CoveringSubregs) { LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(Idx); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 83de2c2c150..2ee8f9604e0 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1444,9 +1444,8 @@ void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const { SmallVector<unsigned, 6> ScratchRegs; for(unsigned I = 5; I < MI->getNumOperands(); ++I) ScratchRegs.push_back(MI->getOperand(I).getReg()); - llvm::sort(ScratchRegs.begin(), ScratchRegs.end(), - [&TRI](const unsigned &Reg1, - const unsigned &Reg2) -> bool { + llvm::sort(ScratchRegs, + [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool { return TRI.getEncodingValue(Reg1) < TRI.getEncodingValue(Reg2); }); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 742d5dd3d8c..3e057e953d8 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1008,8 +1008,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, if (Regs.empty()) continue; - llvm::sort(Regs.begin(), Regs.end(), [&](const RegAndKill &LHS, - const RegAndKill &RHS) { + llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) { return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first); }); @@ -1105,7 +1104,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, if (Regs.empty()) continue; - llvm::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) { + llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) { return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS); }); diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index e6b8f2fcf45..6da7430a8e5 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1848,7 +1848,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) { auto LessThan = [](const MergeCandidate* M0, const MergeCandidate *M1) { return M0->InsertPos < M1->InsertPos; }; - llvm::sort(Candidates.begin(), Candidates.end(), LessThan); + llvm::sort(Candidates, LessThan); // Go through list of candidates and merge. bool Changed = false; @@ -2186,13 +2186,12 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, bool RetVal = false; // Sort by offset (in reverse order). - llvm::sort(Ops.begin(), Ops.end(), - [](const MachineInstr *LHS, const MachineInstr *RHS) { - int LOffset = getMemoryOpOffset(*LHS); - int ROffset = getMemoryOpOffset(*RHS); - assert(LHS == RHS || LOffset != ROffset); - return LOffset > ROffset; - }); + llvm::sort(Ops, [](const MachineInstr *LHS, const MachineInstr *RHS) { + int LOffset = getMemoryOpOffset(*LHS); + int ROffset = getMemoryOpOffset(*RHS); + assert(LHS == RHS || LOffset != ROffset); + return LOffset > ROffset; + }); // The loads / stores of the same base are in order. Scan them from first to // last and check for the following: diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 3dc2ac39f9f..b481f8b9659 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -1072,7 +1072,7 @@ void ARMTargetELFStreamer::finishAttributeSection() { if (Contents.empty()) return; - llvm::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag); + llvm::sort(Contents, AttributeItem::LessTag); ARMELFStreamer &Streamer = getStreamer(); diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index b877ed7d5a9..6b48384c737 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1947,10 +1947,9 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) { AssignmentMap IMap; collect(MF); - llvm::sort(Extenders.begin(), Extenders.end(), - [](const ExtDesc &A, const ExtDesc &B) { - return ExtValue(A) < ExtValue(B); - }); + llvm::sort(Extenders, [](const ExtDesc &A, const ExtDesc &B) { + return ExtValue(A) < ExtValue(B); + }); bool Changed = false; LLVM_DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n"); diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index 2582a021e95..e3492e7374e 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -632,7 +632,7 @@ void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB, SortableVectorType VRs; for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I) VRs.push_back(I->first); - llvm::sort(VRs.begin(), VRs.end(), LexCmp); + llvm::sort(VRs, LexCmp); // Transfer the results to the outgoing register ordering. for (unsigned i = 0, n = VRs.size(); i < n; ++i) RO.insert(std::make_pair(VRs[i], i)); diff --git a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp index 991af047387..61c2121163b 100644 --- a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -578,7 +578,7 @@ bool HexagonStoreWidening::processBasicBlock(MachineBasicBlock &MBB) { }; for (auto &G : SGs) { assert(G.size() > 1 && "Store group with fewer than 2 elements"); - llvm::sort(G.begin(), G.end(), Less); + llvm::sort(G, Less); Changed |= processStoreGroup(G); } diff --git a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp index da339bfd3ff..8dcd485d65e 100644 --- a/llvm/lib/Target/Hexagon/RDFDeadCode.cpp +++ b/llvm/lib/Target/Hexagon/RDFDeadCode.cpp @@ -214,7 +214,7 @@ bool DeadCodeElimination::erase(const SetVector<NodeId> &Nodes) { return false; return A.Id < B.Id; }; - llvm::sort(DRNs.begin(), DRNs.end(), UsesFirst); + llvm::sort(DRNs, UsesFirst); if (trace()) dbgs() << "Removing dead ref nodes:\n"; diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp index 3d1ec31dada..d8ca08e7050 100644 --- a/llvm/lib/Target/Hexagon/RDFGraph.cpp +++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp @@ -1471,7 +1471,7 @@ void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs, // and add a def for each S in the closure. // Sort the refs so that the phis will be created in a deterministic order. - llvm::sort(MaxRefs.begin(), MaxRefs.end()); + llvm::sort(MaxRefs); // Remove duplicates. auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end()); MaxRefs.erase(NewEnd, MaxRefs.end()); diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp index c257d754ddf..9ff48d25a02 100644 --- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp +++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp @@ -207,7 +207,7 @@ NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, }; std::vector<NodeId> Tmp(Owners.begin(), Owners.end()); - llvm::sort(Tmp.begin(), Tmp.end(), Less); + llvm::sort(Tmp, Less); // The vector is a list of instructions, so that defs coming from // the same instruction don't need to be artificially ordered. @@ -813,7 +813,7 @@ void Liveness::computeLiveIns() { std::vector<RegisterRef> LV; for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I) LV.push_back(RegisterRef(I->PhysReg, I->LaneMask)); - llvm::sort(LV.begin(), LV.end()); + llvm::sort(LV); dbgs() << printMBBReference(B) << "\t rec = {"; for (auto I : LV) dbgs() << ' ' << Print<RegisterRef>(I, DFG); @@ -824,7 +824,7 @@ void Liveness::computeLiveIns() { const RegisterAggr &LG = LiveMap[&B]; for (auto I = LG.rr_begin(), E = LG.rr_end(); I != E; ++I) LV.push_back(*I); - llvm::sort(LV.begin(), LV.end()); + llvm::sort(LV); dbgs() << "\tcomp = {"; for (auto I : LV) dbgs() << ' ' << Print<RegisterRef>(I, DFG); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index 3dc753772e5..c600382446a 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -453,7 +453,7 @@ void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm, return; // Sort relocations by the address they are applied to. - llvm::sort(Relocs.begin(), Relocs.end(), + llvm::sort(Relocs, [](const ELFRelocationEntry &A, const ELFRelocationEntry &B) { return A.Offset < B.Offset; }); diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 54239c228d9..af17bb5f165 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -1401,7 +1401,7 @@ class BitPermutationSelector { for (auto &I : ValueRots) { ValueRotsVec.push_back(I.second); } - llvm::sort(ValueRotsVec.begin(), ValueRotsVec.end()); + llvm::sort(ValueRotsVec); } // In 64-bit mode, rlwinm and friends have a rotation operator that diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp index d69a2793710..d97b13a8d69 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp @@ -118,16 +118,15 @@ bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) { // registers), by weight next, and then by position. // TODO: Investigate more intelligent sorting heuristics. For starters, we // should try to coalesce adjacent live intervals before non-adjacent ones. - llvm::sort(SortedIntervals.begin(), SortedIntervals.end(), - [MRI](LiveInterval *LHS, LiveInterval *RHS) { - if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) - return MRI->isLiveIn(LHS->reg); - if (LHS->weight != RHS->weight) - return LHS->weight > RHS->weight; - if (LHS->empty() || RHS->empty()) - return !LHS->empty() && RHS->empty(); - return *LHS < *RHS; - }); + llvm::sort(SortedIntervals, [MRI](LiveInterval *LHS, LiveInterval *RHS) { + if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) + return MRI->isLiveIn(LHS->reg); + if (LHS->weight != RHS->weight) + return LHS->weight > RHS->weight; + if (LHS->empty() || RHS->empty()) + return !LHS->empty() && RHS->empty(); + return *LHS < *RHS; + }); LLVM_DEBUG(dbgs() << "Coloring register intervals:\n"); SmallVector<unsigned, 16> SlotMapping(SortedIntervals.size(), -1u); diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index 7979315a2ae..14e4c455a08 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -828,7 +828,7 @@ X86SpeculativeLoadHardeningPass::tracePredStateThroughCFG( "split above!"); // Sort and unique the codes to minimize them. - llvm::sort(UncondCodeSeq.begin(), UncondCodeSeq.end()); + llvm::sort(UncondCodeSeq); UncondCodeSeq.erase(std::unique(UncondCodeSeq.begin(), UncondCodeSeq.end()), UncondCodeSeq.end()); diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index b87c149a36d..fff8a66d0e7 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -151,7 +151,7 @@ static void GetSpillList(SmallVectorImpl<StackSlotInfo> &SpillList, Offset, FramePtr)); } - llvm::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset); + llvm::sort(SpillList, CompareSSIOffset); } /// Creates an ordered list of EH info register 'spills'. @@ -170,7 +170,7 @@ static void GetEHSpillList(SmallVectorImpl<StackSlotInfo> &SpillList, SpillList.push_back( StackSlotInfo(EHSlot[0], MFI.getObjectOffset(EHSlot[1]), TL->getExceptionSelectorRegister(PersonalityFn))); - llvm::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset); + llvm::sort(SpillList, CompareSSIOffset); } static MachineMemOperand *getFrameIndexMMO(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp b/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp index 1c93ba8fa14..7455cd997ad 100644 --- a/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp +++ b/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp @@ -129,7 +129,7 @@ createReplacementInstr(ConstantExpr *CE, Instruction *Instr) { static bool replaceConstantExprOp(ConstantExpr *CE, Pass *P) { do { SmallVector<WeakTrackingVH, 8> WUsers(CE->user_begin(), CE->user_end()); - llvm::sort(WUsers.begin(), WUsers.end()); + llvm::sort(WUsers); WUsers.erase(std::unique(WUsers.begin(), WUsers.end()), WUsers.end()); while (!WUsers.empty()) if (WeakTrackingVH WU = WUsers.pop_back_val()) { |