diff options
Diffstat (limited to 'llvm/lib/Target')
6 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 9e73766b6fd..0c4a727734f 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -622,7 +622,7 @@ bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits, // operand may be a subregister of a larger register, while Bits would // correspond to the larger register in its entirety. Because of that, // the parameter Begin can be used to indicate which bit of Bits should be -// considered the LSB of of the operand. +// considered the LSB of the operand. bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, BitVector &Bits, uint16_t Begin, const HexagonInstrInfo &HII) { using namespace Hexagon; diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index eb8fab13626..e618f64c00e 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1170,7 +1170,7 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R, } case HexagonISD::JT: case HexagonISD::CP: - // These are assumed to always be aligned at at least 8-byte boundary. + // These are assumed to always be aligned at least 8-byte boundary. if (LogAlign > 3) return false; R = N.getOperand(0); @@ -1182,7 +1182,7 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R, R = N; return true; case ISD::BlockAddress: - // Block address is always aligned at at least 4-byte boundary. + // Block address is always aligned at least 4-byte boundary. if (LogAlign > 2 || !IsAligned(cast<BlockAddressSDNode>(N)->getOffset())) return false; R = N; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index c026923645f..2e20f080b83 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -230,7 +230,7 @@ HexagonTargetLowering::createHvxPrefixPred(SDValue PredV, const SDLoc &dl, // Move the vector predicate SubV to a vector register, and scale it // down to match the representation (bytes per type element) that VecV // uses. The scaling down will pick every 2nd or 4th (every Scale-th - // in general) element and put them at at the front of the resulting + // in general) element and put them at the front of the resulting // vector. This subvector will then be inserted into the Q2V of VecV. // To avoid having an operation that generates an illegal type (short // vector), generate a full size vector. diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td index b91c9428858..d4ef2c7730e 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -1424,7 +1424,7 @@ def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), // setcc instead and earlier I had implemented setcc first so may have masked // the problem. The setcc variants are suboptimal for mips16 so I may wantto // figure out how to enable the brcond patterns or else possibly new -// combinations of of brcond and setcc. +// combinations of brcond and setcc. // // // bcond-seteq diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp index 88daea7e368..89018e2681c 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp @@ -136,7 +136,7 @@ bool WebAssemblyFixIrreducibleControlFlow::VisitLoop(MachineFunction &MF, MachineBasicBlock *Header = Loop ? Loop->getHeader() : &*MF.begin(); SetVector<MachineBasicBlock *> RewriteSuccs; - // DFS through Loop's body, looking for for irreducible control flow. Loop is + // DFS through Loop's body, looking for irreducible control flow. Loop is // natural, and we stay in its body, and we treat any nested loops // monolithically, so any cycles we encounter indicate irreducibility. SmallPtrSet<MachineBasicBlock *, 8> OnStack; diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 2f75e0dd07a..45e4f69da0d 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3066,7 +3066,7 @@ def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; -// Various unary fpstack operations default to operating on on ST1. +// Various unary fpstack operations default to operating on ST1. // For example, "fxch" -> "fxch %st(1)" def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; |
