diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/PIC16/PIC16ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
9 files changed, 35 insertions, 35 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e70bb0bd96a..14c4526d1a0 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -131,10 +131,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) computeRegisterProperties(); // ARM does not have f32 extending load. - setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); // ARM does not have i1 sign extending load. - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); // ARM supports all 4 flavors of integer indexed load / store. for (unsigned im = (unsigned)ISD::PRE_INC; diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 8ec3fb5d9bf..33445f0fa4c 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -52,15 +52,15 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); - setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); - setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand); - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); // setOperationAction(ISD::BRIND, MVT::Other, Expand); setOperationAction(ISD::BR_JT, MVT::Other, Expand); diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 33cb9e6d466..086a25f1d89 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -131,27 +131,27 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) addRegisterClass(MVT::i128, SPU::GPRCRegisterClass); // SPU has no sign or zero extended loads for i1, i8, i16: - setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); setTruncStoreAction(MVT::i8, MVT::i1, Custom); setTruncStoreAction(MVT::i16, MVT::i1, Custom); setTruncStoreAction(MVT::i32, MVT::i1, Custom); setTruncStoreAction(MVT::i64, MVT::i1, Custom); setTruncStoreAction(MVT::i128, MVT::i1, Custom); - setLoadXAction(ISD::EXTLOAD, MVT::i8, Custom); - setLoadXAction(ISD::SEXTLOAD, MVT::i8, Custom); - setLoadXAction(ISD::ZEXTLOAD, MVT::i8, Custom); + setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom); + setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom); setTruncStoreAction(MVT::i8 , MVT::i8, Custom); setTruncStoreAction(MVT::i16 , MVT::i8, Custom); setTruncStoreAction(MVT::i32 , MVT::i8, Custom); setTruncStoreAction(MVT::i64 , MVT::i8, Custom); setTruncStoreAction(MVT::i128, MVT::i8, Custom); - setLoadXAction(ISD::EXTLOAD, MVT::i16, Custom); - setLoadXAction(ISD::SEXTLOAD, MVT::i16, Custom); - setLoadXAction(ISD::ZEXTLOAD, MVT::i16, Custom); + setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom); + setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom); // SPU constant load actions are custom lowered: setOperationAction(ISD::Constant, MVT::i64, Custom); diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp index 3959dc6f744..11582719c80 100644 --- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp +++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp @@ -35,14 +35,14 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) // register class for predicate registers addRegisterClass(MVT::i1, IA64::PRRegisterClass); - setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote); + setLoadExtAction(ISD::EXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote); + setLoadExtAction(ISD::ZEXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand); - setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand); - setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand); + setLoadExtAction(ISD::SEXTLOAD , MVT::i1 , Promote); + setLoadExtAction(ISD::SEXTLOAD , MVT::i8 , Expand); + setLoadExtAction(ISD::SEXTLOAD , MVT::i16 , Expand); + setLoadExtAction(ISD::SEXTLOAD , MVT::i32 , Expand); setOperationAction(ISD::BRIND , MVT::Other, Expand); setOperationAction(ISD::BR_JT , MVT::Other, Expand); diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index dd6b432dca3..6dc237aad6d 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -82,9 +82,9 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) addLegalFPImmediate(APFloat(+0.0f)); // Load extented operations for i1 types must be promoted - setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); // Used by legalize types to correctly generate the setcc result. // Without this, every float setcc comes with a AND/OR with the result, diff --git a/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp b/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp index cdcc2527a28..ace3170dfa5 100644 --- a/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/llvm/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -60,9 +60,9 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM) addRegisterClass(MVT::i16, PIC16::PTRRegsRegisterClass); // Load extented operations for i1 types must be promoted . - setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); setOperationAction(ISD::ADD, MVT::i1, Promote); setOperationAction(ISD::ADD, MVT::i8, Legal); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 0cb77c014e8..553ca107ecf 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -53,8 +53,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); // PowerPC has an i16 but no i8 (or i1) SEXTLOAD - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand); diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index dc354248042..e81688e4e8e 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -515,9 +515,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); // Turn FP extload into load/fextend - setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); // Sparc doesn't have i1 sign extending load - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); // Turn FP truncstore into trunc + store. setTruncStoreAction(MVT::f64, MVT::f32, Expand); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6d3d0b0554e..19b94dfe095 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -84,7 +84,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) if (Subtarget->is64Bit()) addRegisterClass(MVT::i64, X86::GR64RegisterClass); - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); // We don't accept any truncstore of integer registers. setTruncStoreAction(MVT::i64, MVT::i32, Expand); |
