diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 8 |
2 files changed, 9 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 27c67500b26..ced12be388b 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3208,10 +3208,12 @@ def : InstAlias<"mov\t{$seg, $mem|$mem, $seg}", (MOV16ms i16mem:$mem, SEGMENT_RE // Match 'movq <largeimm>, <reg>' as an alias for movabsq. def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; -// Match 'movq GR64, MMX' as an alias for movd. -def : InstAlias<"movq\t{$src, $dst|$dst, $src}", +// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, +// which supports this due to an old AMD documentation bug when 64-bit mode was +// created. +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; -def : InstAlias<"movq\t{$src, $dst|$dst, $src}", +def : InstAlias<"movd\t{$src, $dst|$dst, $src}", (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; // movsx aliases diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index a481644efdd..18be0a54483 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -254,13 +254,13 @@ def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), let isBitcast = 1 in def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), - "movd\t{$src, $dst|$dst, $src}", + "movq\t{$src, $dst|$dst, $src}", [(set VR64:$dst, (bitconvert GR64:$src))], IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), - (ins i64mem:$src), "movd\t{$src, $dst|$dst, $src}", + (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOVQ_RM>, Sched<[WriteLoad]>; // These are 64 bit moves, but since the OS X assembler doesn't @@ -269,7 +269,7 @@ def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), let SchedRW = [WriteMove], isBitcast = 1 in { def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR64:$src), - "movd\t{$src, $dst|$dst, $src}", + "movq\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>; let hasSideEffects = 0 in @@ -286,7 +286,7 @@ def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src), let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), - "movd\t{$src, $dst|$dst, $src}", + "movq\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_REG_MM>, Sched<[WriteStore]>; let SchedRW = [WriteLoad] in { |
