summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/X86')
-rw-r--r--llvm/lib/Target/X86/X86InstrAVX512.td21
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td4
2 files changed, 15 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 5da5daf4063..d21aba283f8 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -656,17 +656,19 @@ multiclass vextract_for_size<int Opcode,
AVX512AIi8Base, EVEX;
let mayStore = 1 in {
def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
- (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
+ (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- []>, EVEX;
+ "\t{$idx, $src1, $dst|$dst, $src1, $idx}",
+ [(store (To.VT (vextract_extract:$idx
+ (From.VT From.RC:$src1), (iPTR imm))),
+ addr:$dst)]>, EVEX;
def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, To.KRCWM:$mask,
- From.RC:$src1, i32u8imm:$src2),
+ From.RC:$src1, i32u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts #
- "\t{$src2, $src1, $dst {${mask}}|"
- "$dst {${mask}}, $src1, $src2}",
+ "\t{$idx, $src1, $dst {${mask}}|"
+ "$dst {${mask}}, $src1, $idx}",
[]>, EVEX_K, EVEX;
}//mayStore = 1
}
@@ -705,11 +707,16 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
vextract_for_size_first_position_lowering<From, To> {
- let Predicates = p in
+ let Predicates = p in {
def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
(To.VT (!cast<Instruction>(InstrStr#"rr")
From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
+ def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
+ (iPTR imm))), addr:$dst),
+ (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
+ (EXTRACT_get_vextract_imm To.RC:$ext))>;
+ }
}
multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 4699b505ac3..fa8d50b4ab3 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -7946,7 +7946,7 @@ def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
}
// AVX1 patterns
-let Predicates = [HasAVX] in {
+let Predicates = [HasAVX, NoVLX] in {
def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
(v4f32 (VEXTRACTF128rr
(v8f32 VR256:$src1),
@@ -8634,9 +8634,7 @@ def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
(v16i8 (VEXTRACTI128rr
(v32i8 VR256:$src1),
(EXTRACT_get_vextract128_imm VR128:$ext)))>;
-}
-let Predicates = [HasAVX2] in {
def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
(iPTR imm))), addr:$dst),
(VEXTRACTI128mr addr:$dst, VR256:$src1,
OpenPOWER on IntegriCloud