diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSandyBridge.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 67f44125026..043bffec9fa 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -588,10 +588,8 @@ def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r1", - "ROL(8|16|32|64)ri", - "ROR(8|16|32|64)r1", - "ROR(8|16|32|64)ri", +def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r(1|i)", + "ROR(8|16|32|64)r(1|i)", "SET(A|BE)r")>; def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { @@ -939,12 +937,9 @@ def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8", "BTR(16|32|64)mi8", "BTS(16|32|64)mi8", - "SAR(8|16|32|64)m1", - "SAR(8|16|32|64)mi", - "SHL(8|16|32|64)m1", - "SHL(8|16|32|64)mi", - "SHR(8|16|32|64)m1", - "SHR(8|16|32|64)mi")>; + "SAR(8|16|32|64)m(1|i)", + "SHL(8|16|32|64)m(1|i)", + "SHR(8|16|32|64)m(1|i)")>; def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { let Latency = 8; @@ -982,10 +977,8 @@ def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { let NumMicroOps = 5; let ResourceCycles = [1,2,2]; } -def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m1", - "ROL(8|16|32|64)mi", - "ROR(8|16|32|64)m1", - "ROR(8|16|32|64)mi")>; +def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)", + "ROR(8|16|32|64)m(1|i)")>; def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { let Latency = 8; |
