diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSandyBridge.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index f805e82b7e1..da42577395b 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -1118,12 +1118,12 @@ def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { } def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; -def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
- let Latency = 11;
- let NumMicroOps = 11;
- let ResourceCycles = [7,4];
-}
-def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
+def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> { + let Latency = 11; + let NumMicroOps = 11; + let ResourceCycles = [7,4]; +} +def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m", "RCR(8|16|32|64)m")>; def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { |
