1 files changed, 11 insertions, 27 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 86cfce184fd..7797e23d397 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -1931,18 +1931,11 @@ def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup116], (instregex "SQRTSSr",
+def: InstRW<[SBWriteResGroup116], (instregex "(V?)SQRTSSr",
                                              "(V?)DIVPSrr",
                                              "(V?)DIVSSrr",
                                              "(V?)SQRTPSr")>;
 
-def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> {
-  let Latency = 14;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[SBWriteResGroup117], (instregex "VSQRTSSm")>;
-
 def SBWriteResGroup118 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
   let Latency = 14;
   let NumMicroOps = 4;
@@ -1971,7 +1964,7 @@ def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[SBWriteResGroup123], (instregex "SQRTSSm",
+def: InstRW<[SBWriteResGroup123], (instregex "(V?)SQRTSSm",
                                              "(V?)DIVPSrm",
                                              "(V?)DIVSSrm",
                                              "(V?)SQRTPSm")>;
@@ -1981,24 +1974,24 @@ def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup124], (instregex "VSQRTSDr")>;
+def: InstRW<[SBWriteResGroup124], (instregex "(V?)SQRTPDr",
+                                             "(V?)SQRTSDr")>;
 
 def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23]> {
-  let Latency = 21;
+  let Latency = 27;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[SBWriteResGroup125], (instregex "VSQRTSDm")>;
+def: InstRW<[SBWriteResGroup125], (instregex "(V?)SQRTPDm",
+                                             "(V?)SQRTSDm")>;
 
 def SBWriteResGroup126 : SchedWriteRes<[SBPort0]> {
   let Latency = 22;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup126], (instregex "SQRTSDr",
-                                             "(V?)DIVPDrr",
-                                             "(V?)DIVSDrr",
-                                             "(V?)SQRTPDr")>;
+def: InstRW<[SBWriteResGroup126], (instregex "(V?)DIVPDrr",
+                                             "(V?)DIVSDrr")>;
 
 def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
   let Latency = 24;
@@ -2017,10 +2010,8 @@ def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23]> {
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[SBWriteResGroup128], (instregex "SQRTSDm",
-                                             "(V?)DIVPDrm",
-                                             "(V?)DIVSDrm",
-                                             "(V?)SQRTPDm")>;
+def: InstRW<[SBWriteResGroup128], (instregex "(V?)DIVPDrm",
+                                             "(V?)DIVSDrm")>;
 
 def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort05]> {
   let Latency = 29;
@@ -2074,11 +2065,4 @@ def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort05]> {
 def: InstRW<[SBWriteResGroup134], (instregex "VDIVPDYrm",
                                              "VSQRTPDYm")>;
 
-def SBWriteResGroup135 : SchedWriteRes<[SBPort0]> {
-  let Latency = 114;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[SBWriteResGroup135], (instregex "VSQRTSSr")>;
-
 } // SchedModel