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-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td69
1 files changed, 35 insertions, 34 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 043bffec9fa..0030812e61e 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -578,10 +578,14 @@ def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABS(B|D|W)rr",
- "MMX_PADDQirr",
- "MMX_PALIGNRrri",
- "MMX_PSIGN(B|D|W)rr")>;
+def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
+ MMX_PABSDrr,
+ MMX_PABSWrr,
+ MMX_PADDQirr,
+ MMX_PALIGNRrri,
+ MMX_PSIGNBrr,
+ MMX_PSIGNDrr,
+ MMX_PSIGNWrr)>;
def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
let Latency = 2;
@@ -607,10 +611,7 @@ def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup12], (instregex "(V?)COMISDrr",
- "(V?)COMISSrr",
- "(V?)UCOMISDrr",
- "(V?)UCOMISSrr")>;
+def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>;
def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
let Latency = 2;
@@ -625,15 +626,15 @@ def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>;
-def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>;
+def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
+ MMX_MOVDQ2Qrr)>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>;
+def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>;
def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
let Latency = 4;
@@ -700,7 +701,7 @@ def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>;
+def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>;
def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 4;
@@ -743,8 +744,8 @@ def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m",
- "PUSHGS64")>;
+def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>;
+def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 5;
@@ -810,9 +811,9 @@ def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm",
- "POP(16|32|64)r",
- "VBROADCASTSSrm",
+def: InstRW<[SBWriteResGroup48], (instrs MMX_MOVD64from64rm,
+ VBROADCASTSSrm)>;
+def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
"(V?)MOV64toPQIrm",
"(V?)MOVDDUPrm",
"(V?)MOVDI2PDIrm",
@@ -827,7 +828,7 @@ def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup49], (instregex "MOV16sm")>;
+def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 6;
@@ -841,9 +842,13 @@ def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm",
- "MMX_PALIGNRrmi",
- "MMX_PSIGN(B|D|W)rm")>;
+def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
+ MMX_PABSDrm,
+ MMX_PABSWrm,
+ MMX_PALIGNRrmi,
+ MMX_PSIGNBrm,
+ MMX_PSIGNDrm,
+ MMX_PSIGNWrm)>;
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 6;
@@ -865,11 +870,11 @@ def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm",
- "VBROADCASTSSYrm",
- "VMOVDDUPYrm",
- "VMOVSHDUPYrm",
- "VMOVSLDUPYrm")>;
+def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
+ VBROADCASTSSYrm,
+ VMOVDDUPYrm,
+ VMOVSHDUPYrm,
+ VMOVSLDUPYrm)>;
def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 7;
@@ -883,14 +888,14 @@ def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>;
+def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQirm)>;
def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SBWriteResGroup62], (instregex "VER(R|W)m")>;
+def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>;
def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 7;
@@ -1000,8 +1005,7 @@ def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)SD2SI(64)?rm",
- "CVT(T?)SS2SI(64)?rm")>;
+def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)(SD|SS)2SI(64)?rm")>;
def SBWriteResGroup93_1 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 9;
@@ -1077,10 +1081,7 @@ def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort
let NumMicroOps = 6;
let ResourceCycles = [1,1,2,1,1];
}
-def: InstRW<[SBWriteResGroup100], (instregex "BT(16|32|64)mr",
- "BTC(16|32|64)mr",
- "BTR(16|32|64)mr",
- "BTS(16|32|64)mr")>;
+def: InstRW<[SBWriteResGroup100], (instregex "BT(C|R|S)?(16|32|64)mr")>;
def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 10;
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