diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSandyBridge.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index d4214b75bd1..bc9ec5765e8 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -328,11 +328,9 @@ def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { let NumMicroOps = 1; let ResourceCycles = [1]; } +def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FNOP)>; def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. -def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP", - "FFREE", - "FINCSTP", - "FNOP", +def: InstRW<[SBWriteResGroup2], (instregex "FFREE", "LD_Frr", "RETQ", "ST_FPrr", @@ -826,7 +824,7 @@ def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { let NumMicroOps = 4; let ResourceCycles = [1,3]; } -def: InstRW<[SBWriteResGroup41], (instregex "FNINIT")>; +def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> { let Latency = 5; |
