diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.h')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.h | 138 |
1 files changed, 66 insertions, 72 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 38caf04f7f8..00684f52cb3 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -24,13 +24,13 @@ #include "X86GenInstrInfo.inc" namespace llvm { - class MachineInstrBuilder; - class X86RegisterInfo; - class X86Subtarget; +class MachineInstrBuilder; +class X86RegisterInfo; +class X86Subtarget; namespace X86 { - // X86 specific condition code. These correspond to X86_*_COND in - // X86InstrInfo.td. They must be kept in synch. +// X86 specific condition code. These correspond to X86_*_COND in +// X86InstrInfo.td. They must be kept in synch. enum CondCode { COND_A = 0, COND_AE = 1, @@ -83,18 +83,17 @@ CondCode getCondFromCMovOpc(unsigned Opc); /// GetOppositeBranchCondition - Return the inverse of the specified cond, /// e.g. turning COND_E to COND_NE. CondCode GetOppositeBranchCondition(CondCode CC); -} // end namespace X86; - +} // namespace X86 /// isGlobalStubReference - Return true if the specified TargetFlag operand is /// a reference to a stub for a global, not the global itself. inline static bool isGlobalStubReference(unsigned char TargetFlag) { switch (TargetFlag) { - case X86II::MO_DLLIMPORT: // dllimport stub. - case X86II::MO_GOTPCREL: // rip-relative GOT reference. - case X86II::MO_GOT: // normal GOT reference. - case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. - case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. + case X86II::MO_DLLIMPORT: // dllimport stub. + case X86II::MO_GOTPCREL: // rip-relative GOT reference. + case X86II::MO_GOT: // normal GOT reference. + case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. + case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. return true; default: return false; @@ -106,11 +105,11 @@ inline static bool isGlobalStubReference(unsigned char TargetFlag) { /// is true, the addressing mode has the PIC base register added in (e.g. EBX). inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { switch (TargetFlag) { - case X86II::MO_GOTOFF: // isPICStyleGOT: local global. - case X86II::MO_GOT: // isPICStyleGOT: other global. - case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. - case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. - case X86II::MO_TLVP: // ??? Pretty sure.. + case X86II::MO_GOTOFF: // isPICStyleGOT: local global. + case X86II::MO_GOT: // isPICStyleGOT: other global. + case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. + case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. + case X86II::MO_TLVP: // ??? Pretty sure.. return true; default: return false; @@ -118,9 +117,8 @@ inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { } inline static bool isScale(const MachineOperand &MO) { - return MO.isImm() && - (MO.getImm() == 1 || MO.getImm() == 2 || - MO.getImm() == 4 || MO.getImm() == 8); + return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 || + MO.getImm() == 4 || MO.getImm() == 8); } inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { @@ -150,8 +148,8 @@ class X86InstrInfo final : public X86GenInstrInfo { /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps. /// - typedef DenseMap<unsigned, - std::pair<uint16_t, uint16_t> > RegOp2MemOpTableType; + typedef DenseMap<unsigned, std::pair<uint16_t, uint16_t>> + RegOp2MemOpTableType; RegOp2MemOpTableType RegOp2MemOpTable2Addr; RegOp2MemOpTableType RegOp2MemOpTable0; RegOp2MemOpTableType RegOp2MemOpTable1; @@ -161,13 +159,13 @@ class X86InstrInfo final : public X86GenInstrInfo { /// MemOp2RegOpTable - Load / store unfolding opcode map. /// - typedef DenseMap<unsigned, - std::pair<uint16_t, uint16_t> > MemOp2RegOpTableType; + typedef DenseMap<unsigned, std::pair<uint16_t, uint16_t>> + MemOp2RegOpTableType; MemOp2RegOpTableType MemOp2RegOpTable; static void AddTableEntry(RegOp2MemOpTableType &R2MTable, - MemOp2RegOpTableType &M2RTable, - uint16_t RegOp, uint16_t MemOp, uint16_t Flags); + MemOp2RegOpTableType &M2RTable, uint16_t RegOp, + uint16_t MemOp, uint16_t Flags); virtual void anchor(); @@ -216,9 +214,8 @@ public: /// true, then it's expected the pre-extension value is available as a subreg /// of the result register. This also returns the sub-register index in /// SubIdx. - bool isCoalescableExtInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SubIdx) const override; + bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, + unsigned &DstReg, unsigned &SubIdx) const override; unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; @@ -253,8 +250,8 @@ public: /// operand to the LEA instruction. bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, - bool &isKill, bool &isUndef, - MachineOperand &ImplicitOp, LiveVariables *LV) const; + bool &isKill, bool &isUndef, MachineOperand &ImplicitOp, + LiveVariables *LV) const; /// convertToThreeAddress - This method must be implemented by targets that /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target @@ -312,8 +309,7 @@ public: /// FMA213 #1, #2, #3 /// results into instruction with adjusted opcode: /// FMA231 #3, #2, #1 - bool findFMA3CommutedOpIndices(const MachineInstr &MI, - unsigned &SrcOpIdx1, + bool findFMA3CommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const; @@ -332,10 +328,10 @@ public: /// FMA213 #1, #2, #3 /// results into instruction with adjusted opcode: /// FMA231 #3, #2, #1 - unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, - unsigned SrcOpIdx1, - unsigned SrcOpIdx2, - const X86InstrFMA3Group &FMA3Group) const; + unsigned + getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, + unsigned SrcOpIdx2, + const X86InstrFMA3Group &FMA3Group) const; // Branch analysis. bool isUnpredicatedTerminator(const MachineInstr &MI) const override; @@ -364,8 +360,8 @@ public: MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded = nullptr) const override; - bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond, - unsigned, unsigned, int&, int&, int&) const override; + bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, + unsigned, unsigned, int &, int &, int &) const override; void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef<MachineOperand> Cond, unsigned TrueReg, @@ -374,8 +370,8 @@ public: const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIndex, + MachineBasicBlock::iterator MI, unsigned SrcReg, + bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; @@ -384,12 +380,11 @@ public: const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, - SmallVectorImpl<MachineInstr*> &NewMIs) const; + SmallVectorImpl<MachineInstr *> &NewMIs) const; void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIndex, - const TargetRegisterClass *RC, + MachineBasicBlock::iterator MI, unsigned DestReg, + int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -397,7 +392,7 @@ public: const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, - SmallVectorImpl<MachineInstr*> &NewMIs) const; + SmallVectorImpl<MachineInstr *> &NewMIs) const; bool expandPostRAPseudo(MachineInstr &MI) const override; @@ -434,7 +429,7 @@ public: SmallVectorImpl<MachineInstr *> &NewMIs) const override; bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, - SmallVectorImpl<SDNode*> &NewNodes) const override; + SmallVectorImpl<SDNode *> &NewNodes) const override; /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new /// instruction after load / store are unfolded from an instruction of the @@ -442,9 +437,9 @@ public: /// possible. If LoadRegIndex is non-null, it is filled in with the operand /// index of the operand which will hold the register holding the loaded /// value. - unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, - bool UnfoldLoad, bool UnfoldStore, - unsigned *LoadRegIndex = nullptr) const override; + unsigned + getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, + unsigned *LoadRegIndex = nullptr) const override; /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler /// to determine if two loads are loading from the same base address. It @@ -455,15 +450,15 @@ public: int64_t &Offset2) const override; /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to - /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should - /// be scheduled togther. On some targets if two loads are loading from + /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads + /// should be scheduled togther. On some targets if two loads are loading from /// addresses in the same cache line, it's better if they are scheduled /// together. This function takes two integers that represent the load offsets /// from the common base address. It returns true if it decides it's desirable /// to schedule the two loads together. "NumLoads" is the number of loads that /// have already been scheduled after Load1. - bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, - int64_t Offset1, int64_t Offset2, + bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, + int64_t Offset2, unsigned NumLoads) const override; void getNoop(MCInst &NopInst) const override; @@ -520,9 +515,7 @@ public: const MachineInstr &UseMI, unsigned UseIdx) const override; - bool useMachineCombiner() const override { - return true; - } + bool useMachineCombiner() const override { return true; } bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; @@ -566,30 +559,31 @@ public: ArrayRef<std::pair<unsigned, const char *>> getSerializableDirectMachineOperandTargetFlags() const override; - size_t getOutliningCallOverhead(MachineBasicBlock::iterator &StartIt, - MachineBasicBlock::iterator &EndIt) const override; - - size_t getOutliningFrameOverhead(MachineBasicBlock::iterator &StartIt, - MachineBasicBlock::iterator &EndIt) const override; + std::pair<size_t, unsigned> + getOutliningCallOverhead(MachineBasicBlock::iterator &StartIt, + MachineBasicBlock::iterator &EndIt) const override; + + std::pair<size_t, unsigned> getOutliningFrameOverhead( + std::vector< + std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>> + &CandidateClass) const override; bool isFunctionSafeToOutlineFrom(MachineFunction &MF) const override; llvm::X86GenInstrInfo::MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const override; - void insertOutlinerEpilogue(MachineBasicBlock &MBB, - MachineFunction &MF, - bool IsTailCall) const override; + void insertOutlinerEpilogue(MachineBasicBlock &MBB, MachineFunction &MF, + unsigned FrameClass) const override; - void insertOutlinerPrologue(MachineBasicBlock &MBB, - MachineFunction &MF, - bool isTailCall) const override; + void insertOutlinerPrologue(MachineBasicBlock &MBB, MachineFunction &MF, + unsigned FrameClass) const override; MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, - MachineBasicBlock::iterator &It, - MachineFunction &MF, - bool IsTailCall) const override; + MachineBasicBlock::iterator &It, MachineFunction &MF, + unsigned CallClass) const override; + protected: /// Commutes the operands in the given instruction by changing the operands /// order and/or changing the instruction's opcode and/or the immediate value @@ -645,6 +639,6 @@ private: unsigned &SrcOpIdx2) const; }; -} // End llvm namespace +} // namespace llvm #endif |
