diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrArithmetic.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrArithmetic.td | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 530154b17bf..16b6f9898f1 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1355,19 +1355,19 @@ let Predicates = [HasBMI2] in { //===----------------------------------------------------------------------===// // ADCX Instruction // -let hasSideEffects = 0, Defs = [EFLAGS], Uses = [EFLAGS], +let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS], Constraints = "$src0 = $dst", AddedComplexity = 10 in { let SchedRW = [WriteALU] in { def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src0, GR32:$src), "adcx{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, EFLAGS, (X86adc_flag GR32:$src0, GR32:$src, EFLAGS))], - IIC_BIN_CARRY_NONMEM>, T8PD, Requires<[HasADX]>; + IIC_BIN_CARRY_NONMEM>, T8PD; def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src0, GR64:$src), "adcx{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, EFLAGS, (X86adc_flag GR64:$src0, GR64:$src, EFLAGS))], - IIC_BIN_CARRY_NONMEM>, T8PD, Requires<[HasADX, In64BitMode]>; + IIC_BIN_CARRY_NONMEM>, T8PD; } // SchedRW let mayLoad = 1, SchedRW = [WriteALULd] in { @@ -1375,37 +1375,34 @@ let hasSideEffects = 0, Defs = [EFLAGS], Uses = [EFLAGS], (ins GR32:$src0, i32mem:$src), "adcx{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, EFLAGS, (X86adc_flag GR32:$src0, (loadi32 addr:$src), EFLAGS))], - IIC_BIN_CARRY_MEM>, T8PD, Requires<[HasADX]>; + IIC_BIN_CARRY_MEM>, T8PD; def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src0, i64mem:$src), "adcx{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, EFLAGS, (X86adc_flag GR64:$src0, (loadi64 addr:$src), EFLAGS))], - IIC_BIN_CARRY_MEM>, T8PD, Requires<[HasADX, In64BitMode]>; + IIC_BIN_CARRY_MEM>, T8PD; } } //===----------------------------------------------------------------------===// // ADOX Instruction // -let hasSideEffects = 0, Defs = [EFLAGS], Uses = [EFLAGS] in { +let Predicates = [HasADX], hasSideEffects = 0, Defs = [EFLAGS], + Uses = [EFLAGS] in { let SchedRW = [WriteALU] in { def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), - "adox{l}\t{$src, $dst|$dst, $src}", - [], IIC_BIN_NONMEM>, T8XS, Requires<[HasADX]>; + "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS; def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), - "adox{q}\t{$src, $dst|$dst, $src}", - [], IIC_BIN_NONMEM>, T8XS, Requires<[HasADX, In64BitMode]>; + "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS; } // SchedRW let mayLoad = 1, SchedRW = [WriteALULd] in { def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "adox{l}\t{$src, $dst|$dst, $src}", - [], IIC_BIN_MEM>, T8XS, Requires<[HasADX]>; + "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_MEM>, T8XS; def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "adox{q}\t{$src, $dst|$dst, $src}", - [], IIC_BIN_MEM>, T8XS, Requires<[HasADX, In64BitMode]>; + "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_MEM>, T8XS; } } |
