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-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f7fe3e8add4..80f1afe310f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35750,6 +35750,18 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
getZeroVector(OpVT, Subtarget, DAG, dl), SubVec2,
Vec.getOperand(2));
+
+ // If we are inserting into both halves of the vector, the starting
+ // vector should be undef. If it isn't, make it so. Only do this if the
+ // the early insert has no other uses.
+ // TODO: Should this be a generic DAG combine?
+ if (!Vec.getOperand(0).isUndef() && Vec.hasOneUse()) {
+ Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, DAG.getUNDEF(OpVT),
+ SubVec2, Vec.getOperand(2));
+ DCI.AddToWorklist(Vec.getNode());
+ return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Vec, SubVec, Idx);
+
+ }
}
}
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