summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp27
1 files changed, 4 insertions, 23 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bd378cfd232..c48158072e0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1404,12 +1404,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
} // Subtarget.hasCDI()
if (Subtarget.hasDQI()) {
- if (Subtarget.hasVLX()) {
- setOperationAction(ISD::MUL, MVT::v2i64, Legal);
- setOperationAction(ISD::MUL, MVT::v4i64, Legal);
- }
+ // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
+ setOperationAction(ISD::MUL, MVT::v2i64, Legal);
+ setOperationAction(ISD::MUL, MVT::v4i64, Legal);
setOperationAction(ISD::MUL, MVT::v8i64, Legal);
}
+
// Custom lower several nodes.
for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
@@ -19854,25 +19854,6 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget,
assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
"Only know how to lower V2I64/V4I64/V8I64 multiply");
- // AVX512DQ - extend to 512 bit vector.
- // FIXME: This can possibly be converted to a tablegen pattern.
- if (Subtarget.hasDQI()) {
- assert(!Subtarget.hasVLX() && "AVX512DQVL vXi64 multiply is legal");
- assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
- "AVX512DQ v8i64 multiply is legal");
-
- MVT NewVT = MVT::getVectorVT(MVT::i64, 512 / VT.getScalarSizeInBits());
- SDValue A512 =
- DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT, DAG.getUNDEF(NewVT), A,
- DAG.getIntPtrConstant(0, dl));
- SDValue B512 =
- DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT, DAG.getUNDEF(NewVT), B,
- DAG.getIntPtrConstant(0, dl));
- SDValue MulNode = DAG.getNode(ISD::MUL, dl, NewVT, A512, B512);
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, MulNode,
- DAG.getIntPtrConstant(0, dl));
- }
-
// Ahi = psrlqi(a, 32);
// Bhi = psrlqi(b, 32);
//
OpenPOWER on IntegriCloud