diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 61 |
1 files changed, 18 insertions, 43 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 99cf13262f3..b17d7276e0b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23035,6 +23035,22 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget, return MarkEHRegistrationNode(Op, DAG); case llvm::Intrinsic::x86_seh_ehguard: return MarkEHGuard(Op, DAG); + case llvm::Intrinsic::x86_rdpkru: { + SDLoc dl(Op); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + // Create a RDPKRU node and pass 0 to the ECX parameter. + return DAG.getNode(X86ISD::RDPKRU, dl, VTs, Op.getOperand(0), + DAG.getConstant(0, dl, MVT::i32)); + } + case llvm::Intrinsic::x86_wrpkru: { + SDLoc dl(Op); + // Create a WRPKRU node, pass the input to the EAX parameter, and pass 0 + // to the EDX and ECX parameters. + return DAG.getNode(X86ISD::WRPKRU, dl, MVT::Other, + Op.getOperand(0), Op.getOperand(2), + DAG.getConstant(0, dl, MVT::i32), + DAG.getConstant(0, dl, MVT::i32)); + } case llvm::Intrinsic::x86_flags_read_u32: case llvm::Intrinsic::x86_flags_read_u64: case llvm::Intrinsic::x86_flags_write_u32: @@ -27808,6 +27824,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::SAHF: return "X86ISD::SAHF"; case X86ISD::RDRAND: return "X86ISD::RDRAND"; case X86ISD::RDSEED: return "X86ISD::RDSEED"; + case X86ISD::RDPKRU: return "X86ISD::RDPKRU"; + case X86ISD::WRPKRU: return "X86ISD::WRPKRU"; case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW"; case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD"; case X86ISD::VPSHA: return "X86ISD::VPSHA"; @@ -28268,44 +28286,6 @@ static MachineBasicBlock *emitXBegin(MachineInstr &MI, MachineBasicBlock *MBB, return sinkMBB; } -static MachineBasicBlock *emitWRPKRU(MachineInstr &MI, MachineBasicBlock *BB, - const X86Subtarget &Subtarget) { - DebugLoc dl = MI.getDebugLoc(); - const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - - // insert input VAL into EAX - BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) - .addReg(MI.getOperand(0).getReg()); - // insert zero to ECX - BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::ECX); - - // insert zero to EDX - BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::EDX); - - // insert WRPKRU instruction - BuildMI(*BB, MI, dl, TII->get(X86::WRPKRUr)); - - MI.eraseFromParent(); // The pseudo is gone now. - return BB; -} - -static MachineBasicBlock *emitRDPKRU(MachineInstr &MI, MachineBasicBlock *BB, - const X86Subtarget &Subtarget) { - DebugLoc dl = MI.getDebugLoc(); - const TargetInstrInfo *TII = Subtarget.getInstrInfo(); - - // insert zero to ECX - BuildMI(*BB, MI, dl, TII->get(X86::MOV32r0), X86::ECX); - - // insert RDPKRU instruction - BuildMI(*BB, MI, dl, TII->get(X86::RDPKRUr)); - BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg()) - .addReg(X86::EAX); - - MI.eraseFromParent(); // The pseudo is gone now. - return BB; -} - MachineBasicBlock * @@ -30418,11 +30398,6 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return BB; } - // PKU feature - case X86::WRPKRU: - return emitWRPKRU(MI, BB, Subtarget); - case X86::RDPKRU: - return emitRDPKRU(MI, BB, Subtarget); // xbegin case X86::XBEGIN: return emitXBegin(MI, BB, Subtarget.getInstrInfo()); |
