diff options
Diffstat (limited to 'llvm/lib/Target/Sparc')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcFrameLowering.cpp | 9 | ||||
-rw-r--r-- | llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 9 |
2 files changed, 6 insertions, 12 deletions
diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index 16db38733c5..1b67b4b3403 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -46,8 +46,7 @@ void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF, DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (NumBytes >= -4096 && NumBytes < 4096) { BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) @@ -89,8 +88,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -155,8 +153,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); assert(MBBI->getOpcode() == SP::RETL && "Can only put epilog before 'retl' instruction!"); diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index dbf9ed66949..3cca98f0ca1 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -108,8 +108,7 @@ static void replaceFI(MachineFunction &MF, return; } - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // FIXME: it would be better to scavenge a register here instead of // reserving G1 all of the time. @@ -175,8 +174,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { if (MI.getOpcode() == SP::STQFri) { - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); @@ -188,8 +186,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(2).setReg(SrcOddReg); Offset += 8; } else if (MI.getOpcode() == SP::LDQFri) { - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned DestReg = MI.getOperand(0).getReg(); unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); |