diff options
136 files changed, 491 insertions, 739 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index 0a2c5733007..ef77b6069fc 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -39,6 +39,7 @@ class MachineModuleInfo; class MCContext; class Pass; class TargetMachine; +class TargetSubtargetInfo; class TargetRegisterClass; struct MachinePointerInfo; @@ -76,6 +77,7 @@ struct MachineFunctionInfo { class MachineFunction { const Function *Fn; const TargetMachine &Target; + const TargetSubtargetInfo *STI; MCContext &Ctx; MachineModuleInfo &MMI; GCModuleInfo *GMI; @@ -163,6 +165,11 @@ public: /// const TargetMachine &getTarget() const { return Target; } + /// getSubtarget - Return the subtarget for which this machine code is being + /// compiled. + const TargetSubtargetInfo &getSubtarget() const { return *STI; } + void setSubtarget(TargetSubtargetInfo *ST) { STI = ST; } + /// getRegInfo - Return information about the registers currently in use. /// MachineRegisterInfo &getRegInfo() { return *RegInfo; } diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index e8c695e5022..c45b4afdcfb 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -20,6 +20,7 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/ilist.h" #include "llvm/CodeGen/DAGCombine.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Support/RecyclingAllocator.h" #include "llvm/Target/TargetMachine.h" @@ -276,6 +277,7 @@ public: MachineFunction &getMachineFunction() const { return *MF; } const TargetMachine &getTarget() const { return TM; } + const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); } const TargetLowering &getTargetLoweringInfo() const { return *TLI; } const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; } LLVMContext *getContext() const {return Context; } diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index de0683bf916..b0c3906b02e 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -115,9 +115,9 @@ AggressiveAntiDepBreaker::AggressiveAntiDepBreaker( MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs) : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()), - TII(MF.getTarget().getSubtargetImpl()->getInstrInfo()), - TRI(MF.getTarget().getSubtargetImpl()->getRegisterInfo()), - RegClassInfo(RCI), State(nullptr) { + TII(MF.getSubtarget().getInstrInfo()), + TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), + State(nullptr) { /* Collect a bitset of all registers that are only broken if they are on the critical path. */ for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) { diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index b75cb4321d3..a030c5cc4fa 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1121,7 +1121,7 @@ void AsmPrinter::EmitConstantPool() { /// by the current function to the current output stream. /// void AsmPrinter::EmitJumpTableInfo() { - const DataLayout *DL = MF->getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *DL = MF->getSubtarget().getDataLayout(); const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); if (!MJTI) return; if (MJTI->getEntryKind() == MachineJumpTableInfo::EK_Inline) return; diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 604fad7fe51..1b90ba03d49 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -93,10 +93,9 @@ bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) { bool EnableTailMerge = !MF.getTarget().requiresStructuredCFG() && PassConfig->getEnableTailMerge(); BranchFolder Folder(EnableTailMerge, /*CommonHoist=*/true); - return Folder.OptimizeFunction( - MF, MF.getTarget().getSubtargetImpl()->getInstrInfo(), - MF.getTarget().getSubtargetImpl()->getRegisterInfo(), - getAnalysisIfAvailable<MachineModuleInfo>()); + return Folder.OptimizeFunction(MF, MF.getSubtarget().getInstrInfo(), + MF.getSubtarget().getRegisterInfo(), + getAnalysisIfAvailable<MachineModuleInfo>()); } diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp index 9e76995f5bf..1f6909028ea 100644 --- a/llvm/lib/CodeGen/CalcSpillWeights.cpp +++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp @@ -96,8 +96,7 @@ static bool isRematerializable(const LiveInterval &LI, void VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) { MachineRegisterInfo &mri = MF.getRegInfo(); - const TargetRegisterInfo &tri = - *MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo(); MachineBasicBlock *mbb = nullptr; MachineLoop *loop = nullptr; bool isExiting = false; @@ -188,8 +187,7 @@ VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) { // it is a preferred candidate for spilling. // FIXME: this gets much more complicated once we support non-trivial // re-materialization. - if (isRematerializable(li, LIS, - *MF.getTarget().getSubtargetImpl()->getInstrInfo())) + if (isRematerializable(li, LIS, *MF.getSubtarget().getInstrInfo())) totalWeight *= 0.5F; li.weight = normalize(totalWeight, li.getSize()); diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp index 737e6fa55f6..56d700e5e29 100644 --- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -31,11 +31,10 @@ using namespace llvm; CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI) : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()), - TII(MF.getTarget().getSubtargetImpl()->getInstrInfo()), - TRI(MF.getTarget().getSubtargetImpl()->getRegisterInfo()), - RegClassInfo(RCI), Classes(TRI->getNumRegs(), nullptr), - KillIndices(TRI->getNumRegs(), 0), DefIndices(TRI->getNumRegs(), 0), - KeepRegs(TRI->getNumRegs(), false) {} + TII(MF.getSubtarget().getInstrInfo()), + TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), + Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), + DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} CriticalAntiDepBreaker::~CriticalAntiDepBreaker() { } diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp index 09b5e931b6f..535477de788 100644 --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -92,8 +92,8 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { bool AnyChanges = false; MRI = &MF.getRegInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); // Loop over all instructions in all blocks, from bottom to top, so that it's // more likely that chains of dependent but ultimately dead instructions will diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp index 0810f947336..4a64d79d7e7 100644 --- a/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -153,8 +153,8 @@ private: public: /// runOnMachineFunction - Initialize per-function data structures. void runOnMachineFunction(MachineFunction &MF) { - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); LiveRegUnits.clear(); LiveRegUnits.setUniverse(TRI->getNumRegUnits()); @@ -782,8 +782,8 @@ bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) { .enableEarlyIfConversion()) return false; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); SchedModel = MF.getTarget().getSubtarget<TargetSubtargetInfo>().getSchedModel(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/CodeGen/ErlangGC.cpp b/llvm/lib/CodeGen/ErlangGC.cpp index ed2e3d8cf6e..85b089343ca 100644 --- a/llvm/lib/CodeGen/ErlangGC.cpp +++ b/llvm/lib/CodeGen/ErlangGC.cpp @@ -54,8 +54,7 @@ ErlangGC::ErlangGC() { MCSymbol *ErlangGC::InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const { - const TargetInstrInfo *TII = - MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo(); MCSymbol *Label = MBB.getParent()->getContext().CreateTempSymbol(); BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label); return Label; diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp index 9157d8a2abf..287cf55082c 100644 --- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp @@ -715,8 +715,8 @@ void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) { bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - TII = MF->getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF->getSubtarget().getInstrInfo(); + TRI = MF->getSubtarget().getRegisterInfo(); LiveRegs = nullptr; assert(NumRegs == RC->getNumRegs() && "Bad regclass"); diff --git a/llvm/lib/CodeGen/ExpandISelPseudos.cpp b/llvm/lib/CodeGen/ExpandISelPseudos.cpp index 23b543175a3..05b1e6a24e6 100644 --- a/llvm/lib/CodeGen/ExpandISelPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandISelPseudos.cpp @@ -47,8 +47,7 @@ INITIALIZE_PASS(ExpandISelPseudos, "expand-isel-pseudos", bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; - const TargetLowering *TLI = - MF.getTarget().getSubtargetImpl()->getTargetLowering(); + const TargetLowering *TLI = MF.getSubtarget().getTargetLowering(); // Iterate through each instruction in the function, looking for pseudos. for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp index 9b0995dff19..a8588c74560 100644 --- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -184,8 +184,8 @@ bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "Machine Function\n" << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n" << "********** Function: " << MF.getName() << '\n'); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); bool MadeChange = false; diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index 5b6702befab..79eb0fc6fe8 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -269,9 +269,9 @@ INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) INITIALIZE_PASS_END(IfConverter, "if-converter", "If Converter", false, false) bool IfConverter::runOnMachineFunction(MachineFunction &MF) { - TLI = MF.getTarget().getSubtargetImpl()->getTargetLowering(); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TLI = MF.getSubtarget().getTargetLowering(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); MRI = &MF.getRegInfo(); @@ -287,9 +287,8 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { if (!PreRegAlloc) { // Tail merge tend to expose more if-conversion opportunities. BranchFolder BF(true, false); - BFChange = BF.OptimizeFunction( - MF, TII, MF.getTarget().getSubtargetImpl()->getRegisterInfo(), - getAnalysisIfAvailable<MachineModuleInfo>()); + BFChange = BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(), + getAnalysisIfAvailable<MachineModuleInfo>()); } DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'" @@ -421,8 +420,7 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { if (MadeChange && IfCvtBranchFold) { BranchFolder BF(false, false); - BF.OptimizeFunction(MF, TII, - MF.getTarget().getSubtargetImpl()->getRegisterInfo(), + BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(), getAnalysisIfAvailable<MachineModuleInfo>()); } diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index cd1dfc31d12..28235b0f973 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -146,8 +146,8 @@ public: MDT(pass.getAnalysis<MachineDominatorTree>()), Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm), MFI(*mf.getFrameInfo()), MRI(mf.getRegInfo()), - TII(*mf.getTarget().getSubtargetImpl()->getInstrInfo()), - TRI(*mf.getTarget().getSubtargetImpl()->getRegisterInfo()), + TII(*mf.getSubtarget().getInstrInfo()), + TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()) {} void spill(LiveRangeEdit &) override; diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp index 5b21d32f537..f89879dd33b 100644 --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -699,7 +699,7 @@ bool LDVImpl::runOnMachineFunction(MachineFunction &mf) { MF = &mf; LIS = &pass.getAnalysis<LiveIntervals>(); MDT = &pass.getAnalysis<MachineDominatorTree>(); - TRI = mf.getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = mf.getSubtarget().getRegisterInfo(); LS.initialize(mf); DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: " << mf.getName() << " **********\n"); @@ -994,8 +994,7 @@ void LDVImpl::emitDebugValues(VirtRegMap *VRM) { DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n"); if (!MF) return; - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); for (unsigned i = 0, e = userValues.size(); i != e; ++i) { DEBUG(userValues[i]->print(dbgs(), &MF->getTarget())); userValues[i]->rewriteLocations(*VRM, *TRI); diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp index 0514ebbdbc9..dbe3e1ea789 100644 --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -48,7 +48,7 @@ void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const { } bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) { - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); LIS = &getAnalysis<LiveIntervals>(); VRM = &getAnalysis<VirtRegMap>(); diff --git a/llvm/lib/CodeGen/LiveStackAnalysis.cpp b/llvm/lib/CodeGen/LiveStackAnalysis.cpp index 4c01e19ae06..68636609584 100644 --- a/llvm/lib/CodeGen/LiveStackAnalysis.cpp +++ b/llvm/lib/CodeGen/LiveStackAnalysis.cpp @@ -50,7 +50,7 @@ void LiveStacks::releaseMemory() { } bool LiveStacks::runOnMachineFunction(MachineFunction &MF) { - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); // FIXME: No analysis is being done right now. We are relying on the // register allocators to provide the information. return false; diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp index 7b3efe40465..31558ef4415 100644 --- a/llvm/lib/CodeGen/LiveVariables.cpp +++ b/llvm/lib/CodeGen/LiveVariables.cpp @@ -500,7 +500,7 @@ void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI, bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { MF = &mf; MRI = &mf.getRegInfo(); - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF->getSubtarget().getRegisterInfo(); unsigned NumRegs = TRI->getNumRegs(); PhysRegDef = new MachineInstr*[NumRegs]; diff --git a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp index 69f1220a4c2..5c5712f37e1 100644 --- a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp +++ b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp @@ -103,8 +103,7 @@ INITIALIZE_PASS_END(LocalStackSlotPass, "localstackalloc", bool LocalStackSlotPass::runOnMachineFunction(MachineFunction &MF) { MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); unsigned LocalObjectCount = MFI->getObjectIndexEnd(); // If the target doesn't want/need this pass, or if there are no locals @@ -185,8 +184,7 @@ void LocalStackSlotPass::AssignProtectedObjSet(const StackObjSet &UnassignedObjs void LocalStackSlotPass::calculateFrameObjectOffsets(MachineFunction &Fn) { // Loop over all of the stack objects, assigning sequential addresses... MachineFrameInfo *MFI = Fn.getFrameInfo(); - const TargetFrameLowering &TFI = - *Fn.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering(); bool StackGrowsDown = TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; int64_t Offset = 0; @@ -275,10 +273,8 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) { bool UsedBaseReg = false; MachineFrameInfo *MFI = Fn.getFrameInfo(); - const TargetRegisterInfo *TRI = - Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); - const TargetFrameLowering &TFI = - *Fn.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo(); + const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering(); bool StackGrowsDown = TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 59e9b7e057f..ebf3be80257 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -292,8 +292,7 @@ void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const { OS << '\n'; - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); if (!livein_empty()) { if (Indexes) OS << '\t'; OS << " Live Ins:"; @@ -362,8 +361,7 @@ MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { bool LiveIn = isLiveIn(PhysReg); iterator I = SkipPHIsAndLabels(begin()), E = end(); MachineRegisterInfo &MRI = getParent()->getRegInfo(); - const TargetInstrInfo &TII = - *getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo(); // Look for an existing copy. if (LiveIn) @@ -394,8 +392,7 @@ void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) { } void MachineBasicBlock::updateTerminator() { - const TargetInstrInfo *TII = - getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); // A block with no successors has no concerns with fall-through edges. if (this->succ_empty()) return; @@ -650,8 +647,7 @@ bool MachineBasicBlock::canFallThrough() { // Analyze the branches, if any, at the end of the block. MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector<MachineOperand, 4> Cond; - const TargetInstrInfo *TII = - getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) { // If we couldn't analyze the branch, examine the last instruction. // If the block doesn't end in a known control barrier, assume fallthrough @@ -696,8 +692,7 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) { // We may need to update this's terminator, but we can't do that if // AnalyzeBranch fails. If this uses a jump table, we won't touch it. - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector<MachineOperand, 4> Cond; if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) @@ -802,8 +797,8 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) { NMBB->addSuccessor(Succ); if (!NMBB->isLayoutSuccessor(Succ)) { Cond.clear(); - MF->getTarget().getSubtargetImpl()->getInstrInfo()->InsertBranch( - *NMBB, Succ, nullptr, Cond, dl); + MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond, + dl); if (Indexes) { for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end(); @@ -831,8 +826,7 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) { NMBB->addLiveIn(*I); // Update LiveVariables. - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); if (LV) { // Restore kills of virtual registers that were killed by the terminators. while (!KilledRegs.empty()) { diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp index 491e2357935..661a4e321af 100644 --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -1112,8 +1112,8 @@ bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &F) { MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); MLI = &getAnalysis<MachineLoopInfo>(); - TII = F.getTarget().getSubtargetImpl()->getInstrInfo(); - TLI = F.getTarget().getSubtargetImpl()->getTargetLowering(); + TII = F.getSubtarget().getInstrInfo(); + TLI = F.getSubtarget().getTargetLowering(); assert(BlockToChain.empty()); buildCFGChains(F); diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index e63f76432ec..b032c7dee87 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -664,8 +664,8 @@ bool MachineCSE::runOnMachineFunction(MachineFunction &MF) { if (skipOptnoneFunction(*MF.getFunction())) return false; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); AA = &getAnalysis<AliasAnalysis>(); DT = &getAnalysis<MachineDominatorTree>(); diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 8ee97e90a74..cbd62728ace 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -336,8 +336,8 @@ bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); MRI = &MF.getRegInfo(); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 9f28ed35c35..212928815cb 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -54,8 +54,9 @@ void ilist_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) { MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM, unsigned FunctionNum, MachineModuleInfo &mmi, - GCModuleInfo* gmi) - : Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi), GMI(gmi) { + GCModuleInfo *gmi) + : Fn(F), Target(TM), STI(TM.getSubtargetImpl()), Ctx(mmi.getContext()), + MMI(mmi), GMI(gmi) { if (TM.getSubtargetImpl()->getRegisterInfo()) RegInfo = new (Allocator) MachineRegisterInfo(TM); else @@ -353,8 +354,7 @@ void MachineFunction::print(raw_ostream &OS, SlotIndexes *Indexes) const { // Print Constant Pool ConstantPool->print(OS); - const TargetRegisterInfo *TRI = - getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo(); if (RegInfo && !RegInfo->livein_empty()) { OS << "Function Live Ins: "; @@ -463,7 +463,7 @@ unsigned MachineFunction::addLiveIn(unsigned PReg, /// normal 'L' label is returned. MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate) const { - const DataLayout *DL = getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *DL = getSubtarget().getDataLayout(); assert(JumpTableInfo && "No jump tables"); assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!"); @@ -478,7 +478,7 @@ MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx, /// getPICBaseSymbol - Return a function-local symbol to represent the PIC /// base. MCSymbol *MachineFunction::getPICBaseSymbol() const { - const DataLayout *DL = getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *DL = getSubtarget().getDataLayout(); return Ctx.GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+ Twine(getFunctionNumber())+"$pb"); } @@ -629,10 +629,8 @@ MachineFrameInfo::getPristineRegs(const MachineBasicBlock *MBB) const { } unsigned MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); unsigned MaxAlign = getMaxAlignment(); int Offset = 0; @@ -682,8 +680,7 @@ unsigned MachineFrameInfo::estimateStackSize(const MachineFunction &MF) const { void MachineFrameInfo::print(const MachineFunction &MF, raw_ostream &OS) const{ if (Objects.empty()) return; - const TargetFrameLowering *FI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *FI = MF.getSubtarget().getFrameLowering(); int ValOffset = (FI ? FI->getOffsetOfLocalArea() : 0); OS << "Frame Objects:\n"; diff --git a/llvm/lib/CodeGen/MachineSSAUpdater.cpp b/llvm/lib/CodeGen/MachineSSAUpdater.cpp index 59881fd9744..180ece487a3 100644 --- a/llvm/lib/CodeGen/MachineSSAUpdater.cpp +++ b/llvm/lib/CodeGen/MachineSSAUpdater.cpp @@ -40,7 +40,7 @@ static AvailableValsTy &getAvailableVals(void *AV) { MachineSSAUpdater::MachineSSAUpdater(MachineFunction &MF, SmallVectorImpl<MachineInstr*> *NewPHI) : AV(nullptr), InsertedPHIs(NewPHI) { - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TII = MF.getSubtarget().getInstrInfo(); MRI = &MF.getRegInfo(); } diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index c9eefa15b23..5e87514e2f1 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -378,8 +378,7 @@ static bool isSchedBoundary(MachineBasicBlock::iterator MI, /// Main driver for both MachineScheduler and PostMachineScheduler. void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) { - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); bool IsPostRA = Scheduler.isPostRA(); // Visit all machine basic blocks. diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index b0e36639184..76f2aa7bdba 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -52,8 +52,8 @@ void MachineTraceMetrics::getAnalysisUsage(AnalysisUsage &AU) const { bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) { MF = &Func; - TII = MF->getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF->getSubtarget().getInstrInfo(); + TRI = MF->getSubtarget().getRegisterInfo(); MRI = &MF->getRegInfo(); Loops = &getAnalysis<MachineLoopInfo>(); const TargetSubtargetInfo &ST = diff --git a/llvm/lib/CodeGen/OptimizePHIs.cpp b/llvm/lib/CodeGen/OptimizePHIs.cpp index 7a5bec34a68..d28292d9fe5 100644 --- a/llvm/lib/CodeGen/OptimizePHIs.cpp +++ b/llvm/lib/CodeGen/OptimizePHIs.cpp @@ -67,7 +67,7 @@ bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) { return false; MRI = &Fn.getRegInfo(); - TII = Fn.getTarget().getSubtargetImpl()->getInstrInfo(); + TII = Fn.getSubtarget().getInstrInfo(); // Find dead PHI cycles and PHI cycles that can be replaced by a single // value. InstCombine does these optimizations, but DAG legalization may diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index 82a7d5d2ba2..da2bf7ac652 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -241,8 +241,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, // Insert a register to register copy at the top of the current block (but // after any remaining phi nodes) which copies the new incoming register // into the phi node destination. - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); if (isSourceDefinedByImplicitDef(MPhi, MRI)) // If all sources of a PHI node are implicit_def, just emit an // implicit_def instead of a copy. diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 506ee017884..a1f3e5b07ea 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -267,7 +267,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { if (skipOptnoneFunction(*Fn.getFunction())) return false; - TII = Fn.getTarget().getSubtargetImpl()->getInstrInfo(); + TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); AliasAnalysis *AA = &getAnalysis<AliasAnalysis>(); diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp index 38f22fcf9be..b1538006e72 100644 --- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp @@ -139,8 +139,8 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form."); assert(WorkList.empty() && "Inconsistent worklist state"); diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index 1f0110104bf..9d332cad9c5 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -111,10 +111,8 @@ typedef SmallSetVector<int, 8> StackObjSet; /// bool PEI::runOnMachineFunction(MachineFunction &Fn) { const Function* F = Fn.getFunction(); - const TargetRegisterInfo *TRI = - Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); - const TargetFrameLowering *TFI = - Fn.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo(); + const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering(); assert(!Fn.getRegInfo().getNumVirtRegs() && "Regalloc must assign all vregs"); @@ -188,10 +186,8 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) { /// variables for the function's frame information and eliminate call frame /// pseudo instructions. void PEI::calculateCallsInformation(MachineFunction &Fn) { - const TargetInstrInfo &TII = - *Fn.getTarget().getSubtargetImpl()->getInstrInfo(); - const TargetFrameLowering *TFI = - Fn.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo(); + const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering(); MachineFrameInfo *MFI = Fn.getFrameInfo(); unsigned MaxCallFrameSize = 0; @@ -244,10 +240,8 @@ void PEI::calculateCallsInformation(MachineFunction &Fn) { /// calculateCalleeSavedRegisters - Scan the function for modified callee saved /// registers. void PEI::calculateCalleeSavedRegisters(MachineFunction &F) { - const TargetRegisterInfo *RegInfo = - F.getTarget().getSubtargetImpl()->getRegisterInfo(); - const TargetFrameLowering *TFI = - F.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); + const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering(); MachineFrameInfo *MFI = F.getFrameInfo(); // Get the callee saved register list... @@ -344,12 +338,9 @@ void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) { if (CSI.empty()) return; - const TargetInstrInfo &TII = - *Fn.getTarget().getSubtargetImpl()->getInstrInfo(); - const TargetFrameLowering *TFI = - Fn.getTarget().getSubtargetImpl()->getFrameLowering(); - const TargetRegisterInfo *TRI = - Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo(); + const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering(); + const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo(); MachineBasicBlock::iterator I; // Spill using target interface. @@ -455,8 +446,7 @@ AssignProtectedObjSet(const StackObjSet &UnassignedObjs, /// abstract stack objects. /// void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { - const TargetFrameLowering &TFI = - *Fn.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering(); StackProtector *SP = &getAnalysis<StackProtector>(); bool StackGrowsDown = @@ -526,8 +516,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { // Make sure the special register scavenging spill slot is closest to the // incoming stack pointer if a frame pointer is required and is closer // to the incoming rather than the final stack pointer. - const TargetRegisterInfo *RegInfo = - Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); bool EarlyScavengingSlots = (TFI.hasFP(Fn) && TFI.isFPCloseToIncomingSP() && RegInfo->useFPForScavengingIndex(Fn) && @@ -682,8 +671,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { /// prolog and epilog code to the function. /// void PEI::insertPrologEpilogCode(MachineFunction &Fn) { - const TargetFrameLowering &TFI = - *Fn.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering(); // Add prologue to the function... TFI.emitPrologue(Fn); @@ -754,8 +742,7 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn, const TargetMachine &TM = Fn.getTarget(); assert(TM.getSubtargetImpl()->getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); - const TargetInstrInfo &TII = - *Fn.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo(); const TargetRegisterInfo &TRI = *TM.getSubtargetImpl()->getRegisterInfo(); const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering(); bool StackGrowsDown = diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index 643b7b1f848..3e6988e2149 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -189,8 +189,7 @@ PBQPRAProblem *PBQPBuilder::build(MachineFunction *mf, const LiveIntervals *lis, LiveIntervals *LIS = const_cast<LiveIntervals*>(lis); MachineRegisterInfo *mri = &mf->getRegInfo(); - const TargetRegisterInfo *tri = - mf->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *tri = mf->getSubtarget().getRegisterInfo(); std::unique_ptr<PBQPRAProblem> p(new PBQPRAProblem()); PBQPRAGraph &g = p->getGraph(); diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 795dee29f3a..9f4cd17ffdb 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -38,8 +38,8 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { MF = &mf; // Allocate new array the first time we see a new target. - if (MF->getTarget().getSubtargetImpl()->getRegisterInfo() != TRI) { - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + if (MF->getSubtarget().getRegisterInfo() != TRI) { + TRI = MF->getSubtarget().getRegisterInfo(); RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); unsigned NumPSets = TRI->getNumRegPressureSets(); PSetLimits.reset(new unsigned[NumPSets]); diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp index ca9a73be960..49c4cb0a824 100644 --- a/llvm/lib/CodeGen/RegisterPressure.cpp +++ b/llvm/lib/CodeGen/RegisterPressure.cpp @@ -185,7 +185,7 @@ void RegPressureTracker::init(const MachineFunction *mf, reset(); MF = mf; - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF->getSubtarget().getRegisterInfo(); RCI = rci; MRI = &MF->getRegInfo(); MBB = mbb; diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 34e44ccf0c7..1c85248eb84 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -210,8 +210,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { EVT VT = ValueVTs[vti]; unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); for (unsigned i = 0; i != NumRegisters; ++i) BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i); PHIReg += NumRegisters; diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index b62162c0bb0..83f8d308d71 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -48,7 +48,7 @@ static cl::opt<int> HighLatencyCycles( ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) : ScheduleDAG(mf), BB(nullptr), DAG(nullptr), - InstrItins(mf.getTarget().getSubtargetImpl()->getInstrItineraryData()) {} + InstrItins(mf.getSubtarget().getInstrItineraryData()) {} /// Run - perform scheduling. /// diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 193ab511612..1cfd8638097 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3947,8 +3947,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl, // Don't promote to an alignment that would require dynamic stack // realignment. - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (!TRI->needsStackRealignment(MF)) while (NewAlign > Align && TLI.getDataLayout()->exceedsNaturalStackAlignment(NewAlign)) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 8df2bb18fbf..cc6eac70ba7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -861,7 +861,7 @@ void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, AA = &aa; GFI = gfi; LibInfo = li; - DL = DAG.getTarget().getSubtargetImpl()->getDataLayout(); + DL = DAG.getSubtarget().getDataLayout(); Context = DAG.getContext(); LPadToCallSiteMap.clear(); } @@ -4601,8 +4601,7 @@ SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, return false; MachineFunction &MF = DAG.getMachineFunction(); - const TargetInstrInfo *TII = - DAG.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo(); // Ignore inlined function arguments here. DIVariable DV(Variable); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 4fdd2d6fef9..c10803f55b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -37,8 +37,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { return "<<Unknown DAG Node>>"; if (isMachineOpcode()) { if (G) - if (const TargetInstrInfo *TII = - G->getTarget().getSubtargetImpl()->getInstrInfo()) + if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo()) if (getMachineOpcode() < TII->getNumOpcodes()) return TII->getName(getMachineOpcode()); return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>"; @@ -435,10 +434,8 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { OS << LBB->getName() << " "; OS << (const void*)BBDN->getBasicBlock() << ">"; } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { - OS << ' ' - << PrintReg(R->getReg(), - G ? G->getTarget().getSubtargetImpl()->getRegisterInfo() - : nullptr); + OS << ' ' << PrintReg(R->getReg(), + G ? G->getSubtarget().getRegisterInfo() : nullptr); } else if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(this)) { OS << "'" << ES->getSymbol() << "'"; diff --git a/llvm/lib/CodeGen/Spiller.cpp b/llvm/lib/CodeGen/Spiller.cpp index 490af2d021f..af3da9e16b4 100644 --- a/llvm/lib/CodeGen/Spiller.cpp +++ b/llvm/lib/CodeGen/Spiller.cpp @@ -65,8 +65,8 @@ protected: lis = &pass.getAnalysis<LiveIntervals>(); mfi = mf.getFrameInfo(); mri = &mf.getRegInfo(); - tii = mf.getTarget().getSubtargetImpl()->getInstrInfo(); - tri = mf.getTarget().getSubtargetImpl()->getRegisterInfo(); + tii = mf.getSubtarget().getInstrInfo(); + tri = mf.getSubtarget().getRegisterInfo(); } /// Add spill ranges for every use/def of the live interval, inserting loads diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 1c1d377acd6..80c9a83cb69 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -43,7 +43,7 @@ STATISTIC(NumRepairs, "Number of invalid live ranges repaired"); SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis, const MachineLoopInfo &mli) : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli), - TII(*MF.getTarget().getSubtargetImpl()->getInstrInfo()), CurLI(nullptr), + TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr), LastSplitPoint(MF.getNumBlockIDs()) {} void SplitAnalysis::clear() { diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp index 00871c061d2..c2ee87a3de8 100644 --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -67,7 +67,7 @@ bool StackMapLiveness::runOnMachineFunction(MachineFunction &_MF) { DEBUG(dbgs() << "********** COMPUTING STACKMAP LIVENESS: " << _MF.getName() << " **********\n"); MF = &_MF; - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF->getSubtarget().getRegisterInfo(); ++NumStackMapFuncVisited; // Skip this function if there are no patchpoints to process. diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp index cca6cfcde70..adbb38e8b55 100644 --- a/llvm/lib/CodeGen/StackMaps.cpp +++ b/llvm/lib/CodeGen/StackMaps.cpp @@ -239,8 +239,7 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID, // Record the stack size of the current function. const MachineFrameInfo *MFI = AP.MF->getFrameInfo(); - const TargetRegisterInfo *RegInfo = - AP.MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo(); const bool DynamicFrameSize = MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(*(AP.MF)); FnStackSize[AP.CurrentFnSym] = diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp index 9dc46d9403b..5a9bc8be643 100644 --- a/llvm/lib/CodeGen/StackSlotColoring.cpp +++ b/llvm/lib/CodeGen/StackSlotColoring.cpp @@ -423,7 +423,7 @@ bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) { }); MFI = MF.getFrameInfo(); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TII = MF.getSubtarget().getInstrInfo(); LS = &getAnalysis<LiveStacks>(); MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); diff --git a/llvm/lib/CodeGen/TailDuplication.cpp b/llvm/lib/CodeGen/TailDuplication.cpp index 72c9cf4e4f0..4377236323a 100644 --- a/llvm/lib/CodeGen/TailDuplication.cpp +++ b/llvm/lib/CodeGen/TailDuplication.cpp @@ -136,8 +136,8 @@ bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) { if (skipOptnoneFunction(*MF.getFunction())) return false; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); MMI = getAnalysisIfAvailable<MachineModuleInfo>(); MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index 9a0190caca4..9afaebb864a 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -35,8 +35,7 @@ int TargetFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const { - const TargetRegisterInfo *RI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); // By default, assume all frame indices are referenced via whatever // getFrameRegister() says. The target can override this if it's doing diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 2d8b656bb12..42bba90f138 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -500,8 +500,7 @@ TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, const MachineOperand &MO = MI->getOperand(1-Ops[0]); MachineBasicBlock::iterator Pos = MI; - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (Flags == MachineMemOperand::MOStore) storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); @@ -656,10 +655,8 @@ bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI, // saves compile time, because it doesn't require every single // stack slot reference to depend on the instruction that does the // modification. - const TargetLowering &TLI = - *MF.getTarget().getSubtargetImpl()->getTargetLowering(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI)) return true; diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp index b176729027a..3d240a99733 100644 --- a/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/llvm/lib/CodeGen/TargetSchedule.cpp @@ -290,8 +290,7 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, // for predicated defs. unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); const MachineFunction &MF = *DefMI->getParent()->getParent(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI)) return computeInstrLatency(DefMI); diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 68e515b999a..7b41e21d701 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -55,8 +55,8 @@ INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false) bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) { MRI = &mf.getRegInfo(); - TII = mf.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = mf.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = mf.getSubtarget().getInstrInfo(); + TRI = mf.getSubtarget().getRegisterInfo(); MF = &mf; Virt2PhysMap.clear(); diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 17aae86e146..904cb53cb8e 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -191,8 +191,8 @@ public: /// runOnMachineFunction - Initialize per-function data structures. void runOnMachineFunction(MachineFunction &MF) { this->MF = &MF; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); } @@ -891,8 +891,8 @@ bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) { bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n" << "********** Function: " << MF.getName() << '\n'); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); SchedModel = MF.getTarget().getSubtarget<TargetSubtargetInfo>().getSchedModel(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 0c9b2ae0928..5174c62a916 100644 --- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -120,7 +120,7 @@ bool AArch64DeadRegisterDefinitions::processMachineBasicBlock( // Scan the function for instructions that have a dead definition of a // register. Replace that register with the zero register when possible. bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); bool Changed = false; DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index 9768de152f9..c850680d4c6 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -723,8 +723,7 @@ bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) { } bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const AArch64InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); bool Modified = false; for (auto &MBB : MF) diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 77b2551f0d2..44903fcb381 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -86,8 +86,7 @@ bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); #ifndef NDEBUG - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); assert(!RegInfo->needsStackRealignment(MF) && "No stack realignment on AArch64!"); #endif @@ -109,15 +108,14 @@ AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { void AArch64FrameLowering::eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const AArch64InstrInfo *TII = + static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc DL = I->getDebugLoc(); int Opc = I->getOpcode(); bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode(); uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0; - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { unsigned Align = getStackAlignment(); @@ -160,8 +158,7 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves( MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); DebugLoc DL = MBB.findDebugLoc(MBBI); // Add callee saved registers to move list. @@ -169,7 +166,7 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves( if (CSI.empty()) return; - const DataLayout *TD = MF.getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *TD = MF.getSubtarget().getDataLayout(); bool HasFP = hasFP(MF); // Calculate amount of bytes used for return address storing. @@ -208,9 +205,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *Fn = MF.getFunction(); const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + MF.getSubtarget().getRegisterInfo()); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); MachineModuleInfo &MMI = MF.getMMI(); AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry(); @@ -304,7 +300,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const { TII->copyPhysReg(MBB, MBBI, DL, AArch64::X19, AArch64::SP, false); if (needsFrameMoves) { - const DataLayout *TD = MF.getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *TD = MF.getSubtarget().getDataLayout(); const int StackGrowth = -TD->getPointerSize(0); unsigned FramePtr = RegInfo->getFrameRegister(MF); @@ -438,10 +434,10 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert(MBBI->isReturn() && "Can only insert epilog into returning blocks"); MachineFrameInfo *MFI = MF.getFrameInfo(); - const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const AArch64InstrInfo *TII = + static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); DebugLoc DL = MBBI->getDebugLoc(); unsigned RetOpcode = MBBI->getOpcode(); @@ -552,7 +548,7 @@ int AArch64FrameLowering::resolveFrameIndexReference(const MachineFunction &MF, bool PreferFP) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); int FPOffset = MFI->getObjectOffset(FI) + 16; int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); @@ -621,8 +617,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned Count = CSI.size(); DebugLoc DL; assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!"); @@ -698,8 +693,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned Count = CSI.size(); DebugLoc DL; assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!"); @@ -767,7 +761,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( void AArch64FrameLowering::processFunctionBeforeCalleeSavedScan( MachineFunction &MF, RegScavenger *RS) const { const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); MachineRegisterInfo *MRI = &MF.getRegInfo(); SmallVector<unsigned, 4> UnspilledCSGPRs; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 8c777640339..d734d436add 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -76,8 +76,7 @@ AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const { BitVector AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); // FIXME: avoid re-calculating this every time. BitVector Reserved(getNumRegs()); @@ -106,8 +105,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); switch (Reg) { default: @@ -171,8 +169,7 @@ bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { unsigned AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; } @@ -239,8 +236,7 @@ bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, // Note that the incoming offset is based on the SP value at function entry, // so it'll be negative. MachineFunction &MF = *MI->getParent()->getParent(); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); MachineFrameInfo *MFI = MF.getFrameInfo(); // Estimate an offset from the frame pointer. @@ -330,7 +326,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); const AArch64FrameLowering *TFI = static_cast<const AArch64FrameLowering *>( - MF.getTarget().getSubtargetImpl()->getFrameLowering()); + MF.getSubtarget().getFrameLowering()); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); unsigned FrameReg; @@ -368,8 +364,7 @@ namespace llvm { unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); switch (RC->getID()) { default: diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp index b09ecb74a71..61370a5387b 100644 --- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp +++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp @@ -118,9 +118,9 @@ bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) { bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - TII = static_cast<const AArch64InstrInfo *>( - MF->getTarget().getSubtargetImpl()->getInstrInfo()); - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = + static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo()); + TRI = MF->getSubtarget().getRegisterInfo(); MRI = &MF->getRegInfo(); const TargetSubtargetInfo &ST = MF->getTarget().getSubtarget<TargetSubtargetInfo>(); diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp index 6e769198855..8e086611c37 100644 --- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp +++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp @@ -677,9 +677,8 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) { } bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) { - TII = static_cast<const ARMBaseInstrInfo *>( - Fn.getTarget().getSubtargetImpl()->getInstrInfo()); - TRI = Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo()); + TRI = Fn.getSubtarget().getRegisterInfo(); MRI = &Fn.getRegInfo(); bool Modified = false; diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index b636d47df48..41f4d821134 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -137,8 +137,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, assert(!MO.getSubReg() && "Subregs should be eliminated!"); if(ARM::GPRPairRegClass.contains(Reg)) { const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); Reg = TRI->getSubReg(Reg, ARM::gsub_0); } O << ARMInstPrinter::getRegisterName(Reg); @@ -231,8 +230,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, case 'y': // Print a VFP single precision register as indexed double. if (MI->getOperand(OpNum).isReg()) { unsigned Reg = MI->getOperand(OpNum).getReg(); - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); // Find the 'd' register that has this 's' register as a sub-register, // and determine the lane number. for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { @@ -264,8 +262,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, // inline asm statement. O << "{"; if (ARM::GPRPairRegClass.contains(RegBegin)) { - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); O << ARMInstPrinter::getRegisterName(Reg0) << ", "; RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); @@ -321,8 +318,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const MachineOperand &MO = MI->getOperand(OpNum); if (!MO.isReg()) return true; - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? ARM::gsub_0 : ARM::gsub_1); O << ARMInstPrinter::getRegisterName(Reg); @@ -348,8 +344,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned Reg = MI->getOperand(OpNum).getReg(); if (!ARM::QPRRegClass.contains(Reg)) return true; - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1); O << ARMInstPrinter::getRegisterName(SubReg); @@ -364,8 +359,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, if (!MO.isReg()) return true; const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); unsigned Reg = MO.getReg(); if(!ARM::GPRPairRegClass.contains(Reg)) return false; @@ -1035,8 +1029,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { MCTargetStreamer &TS = *OutStreamer.getTargetStreamer(); ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS); const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>(); unsigned FramePtr = RegInfo->getFrameRegister(MF); diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 8af3f4934f6..6207fadcccb 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -123,8 +123,7 @@ ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { BitVector ARMBaseRegisterInfo:: getReservedRegs(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); // FIXME: avoid re-calculating this every time. BitVector Reserved(getNumRegs()); @@ -190,8 +189,7 @@ ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { unsigned ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); switch (RC->getID()) { default: @@ -313,8 +311,7 @@ ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); // When outgoing call frames are so large that we adjust the stack pointer // around the call, we can no longer use the stack pointer to reach the @@ -396,8 +393,7 @@ cannotEliminateFrame(const MachineFunction &MF) const { unsigned ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (TFI->hasFP(MF)) return FramePtr; @@ -414,8 +410,7 @@ emitLoadConstPool(MachineBasicBlock &MBB, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineConstantPool *ConstantPool = MF.getConstantPool(); const Constant *C = ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); @@ -542,8 +537,7 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { // Note that the incoming offset is based on the SP value at function entry, // so it'll be negative. MachineFunction &MF = *MI->getParent()->getParent(); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); @@ -605,8 +599,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB, const MachineFunction &MF = *MBB->getParent(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const MCInstrDesc &MCID = TII.get(ADDriOpc); MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); @@ -622,8 +615,7 @@ void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); int Off = Offset; // ARM doesn't need the general 64-bit offsets unsigned i = 0; @@ -722,10 +714,9 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>( - MF.getTarget().getSubtargetImpl()->getFrameLowering()); + MF.getSubtarget().getFrameLowering()); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); assert(!AFI->isThumb1OnlyFunction() && "This eliminateFrameIndex does not support Thumb1!"); diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index c3d4c442cea..12a8ed67eaa 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -531,7 +531,7 @@ ARMConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { // identity mapping of CPI's to CPE's. const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants(); - const DataLayout &TD = *MF->getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout &TD = *MF->getSubtarget().getDataLayout(); for (unsigned i = 0, e = CPs.size(); i != e; ++i) { unsigned Size = TD.getTypeAllocSize(CPs[i].getType()); assert(Size >= 4 && "Too small constant pool entry"); diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 0d062648f71..2d805185e6c 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -867,9 +867,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, if (RI.hasBasePointer(MF)) { int32_t NumBytes = AFI->getFramePtrSpillOffset(); unsigned FramePtr = RI.getFrameRegister(MF); - assert( - MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF) && - "base pointer without frame pointer?"); + assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && + "base pointer without frame pointer?"); if (AFI->isThumb2Function()) { emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 980229a011a..74f686507df 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -47,8 +47,7 @@ ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti) /// pointer register. This is true if the function has variable sized allocas /// or if frame pointer elimination is disabled. bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); // iOS requires FP not to be clobbered for backtracing purpose. if (STI.isTargetIOS()) @@ -576,11 +575,9 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF, DebugLoc dl = MBBI->getDebugLoc(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); assert(!AFI->isThumb1OnlyFunction() && "This emitEpilogue does not support Thumb1!"); bool isARM = !AFI->isThumbFunction(); @@ -725,7 +722,7 @@ ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, int SPAdj) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); int FPOffset = Offset - AFI->getFramePtrSpillOffset(); @@ -810,8 +807,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, unsigned NumAlignedDPRCS2Regs, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); @@ -884,8 +880,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); DebugLoc DL = MI->getDebugLoc(); unsigned RetOpcode = MI->getOpcode(); @@ -975,8 +970,7 @@ static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); DebugLoc DL = MI->getDebugLoc(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineFrameInfo &MFI = *MF.getFrameInfo(); // Mark the D-register spill slots as properly aligned. Since MFI computes @@ -1135,8 +1129,7 @@ static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); DebugLoc DL = MI->getDebugLoc(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // Find the frame index assigned to d8. int D8SpillFI = 0; @@ -1359,7 +1352,7 @@ static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) { // Aligned spills require stack realignment. const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); if (!RegInfo->canRealignStack(MF)) return; @@ -1399,10 +1392,9 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, SmallVector<unsigned, 4> UnspilledCS1GPRs; SmallVector<unsigned, 4> UnspilledCS2GPRs; const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); @@ -1643,8 +1635,7 @@ void ARMFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (!hasReservedCallFrame(MF)) { // If we have alloca, convert as follows: // ADJCALLSTACKDOWN -> sub, sp, sp, amount @@ -1762,8 +1753,7 @@ void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { MCContext &Context = MMI.getContext(); const MCRegisterInfo *MRI = Context.getRegisterInfo(); const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>(); DebugLoc DL; diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 39741e3dae0..e547600624a 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -425,7 +425,7 @@ bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const { return true; if (Use->isMachineOpcode()) { const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>( - CurDAG->getTarget().getSubtargetImpl()->getInstrInfo()); + CurDAG->getSubtarget().getInstrInfo()); const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode()); if (MCID.mayStore()) diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index b7adfeeb5a1..fe9a365e9b9 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1793,9 +1793,9 @@ namespace { } bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { - TD = Fn.getTarget().getSubtargetImpl()->getDataLayout(); - TII = Fn.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); + TD = Fn.getSubtarget().getDataLayout(); + TII = Fn.getSubtarget().getInstrInfo(); + TRI = Fn.getSubtarget().getRegisterInfo(); STI = &Fn.getTarget().getSubtarget<ARMSubtarget>(); MRI = &Fn.getRegInfo(); MF = &Fn; diff --git a/llvm/lib/Target/ARM/MLxExpansionPass.cpp b/llvm/lib/Target/ARM/MLxExpansionPass.cpp index 825217eb8db..35fe9b3342d 100644 --- a/llvm/lib/Target/ARM/MLxExpansionPass.cpp +++ b/llvm/lib/Target/ARM/MLxExpansionPass.cpp @@ -378,9 +378,8 @@ bool MLxExpansion::ExpandFPMLxInstructions(MachineBasicBlock &MBB) { } bool MLxExpansion::runOnMachineFunction(MachineFunction &Fn) { - TII = static_cast<const ARMBaseInstrInfo *>( - Fn.getTarget().getSubtargetImpl()->getInstrInfo()); - TRI = Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo()); + TRI = Fn.getSubtarget().getRegisterInfo(); MRI = &Fn.getRegInfo(); const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>(); isLikeA9 = STI->isLikeA9() || STI->isSwift(); diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp index 70dab9af8d0..05852d814aa 100644 --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -52,10 +52,9 @@ void Thumb1FrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const Thumb1InstrInfo &TII = - *static_cast<const Thumb1InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo()); const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); if (!hasReservedCallFrame(MF)) { // If we have alloca, convert as follows: // ADJCALLSTACKDOWN -> sub, sp, sp, amount @@ -91,10 +90,9 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); const Thumb1InstrInfo &TII = - *static_cast<const Thumb1InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo()); unsigned Align = MF.getTarget() .getSubtargetImpl() @@ -327,10 +325,9 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); const Thumb1InstrInfo &TII = - *static_cast<const Thumb1InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo()); unsigned Align = MF.getTarget() .getSubtargetImpl() @@ -426,8 +423,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, DebugLoc DL; MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); if (MI != MBB.end()) DL = MI->getDebugLoc(); @@ -466,8 +462,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); bool isVarArg = AFI->getArgRegsSaveSize() > 0; DebugLoc DL = MI->getDebugLoc(); diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp index 7811a22e589..fb8aaff9269 100644 --- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -67,8 +67,7 @@ Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineConstantPool *ConstantPool = MF.getConstantPool(); const Constant *C = ConstantInt::get( Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val); @@ -516,8 +515,7 @@ Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB, // off the frame pointer (if, for example, there are alloca() calls in // the function, the offset will be negative. Use R12 instead since that's // a call clobbered register that we know won't be used in Thumb1 mode. - const TargetInstrInfo &TII = - *MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); DebugLoc DL; AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr)) .addReg(ARM::R12, RegState::Define) @@ -564,8 +562,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); const ARMBaseInstrInfo &TII = - *static_cast<const ARMBaseInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); DebugLoc dl = MI.getDebugLoc(); MachineInstrBuilder MIB(*MBB.getParent(), &MI); @@ -576,8 +573,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MF.getFrameInfo()->getStackSize() + SPAdj; if (MF.getFrameInfo()->hasVarSizedObjects()) { - assert(SPAdj == 0 && - MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF) && + assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame // pointer or base pointer instead. diff --git a/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp index df72c811a3d..0d5d85a0061 100644 --- a/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -40,8 +40,7 @@ Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineConstantPool *ConstantPool = MF.getConstantPool(); const Constant *C = ConstantInt::get( Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val); diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 3fc7bb99a12..4e76698ba8f 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -417,9 +417,8 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { bool HasChanged = false; // Get target info. - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); - TII = static_cast<const HexagonInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TRI = MF.getSubtarget().getRegisterInfo(); + TII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); // Combine aggressively (for code size) ShouldCombineAggressively = diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index db699d4dc36..5f9b9273864 100644 --- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -160,8 +160,7 @@ bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) { void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF, MachineBasicBlock::iterator &MII, RegScavenger &RS) { - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); MachineBasicBlock *MBB = MII->getParent(); DebugLoc DL = MII->getDebugLoc(); unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 2999c2d5f30..28e2f5529fd 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -81,7 +81,7 @@ void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); determineFrameLayout(MF); @@ -118,8 +118,7 @@ void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const { // Check for overflow. // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used? const int ALLOCFRAME_MAX = 16384; - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); if (NumBytes >= ALLOCFRAME_MAX) { // Emit allocframe(#0). @@ -158,8 +157,7 @@ void HexagonFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = std::prev(MBB.end()); MachineBasicBlock::iterator MBBI_end = MBB.end(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // Handle EH_RETURN. if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) { assert(MBBI->getOperand(0).isReg() && "Offset should be in register!"); @@ -230,8 +228,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters( const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = - *MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); if (CSI.empty()) { return false; @@ -286,8 +283,7 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters( const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = - *MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); if (CSI.empty()) { return false; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 3356ff4f443..714d51f51eb 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -464,7 +464,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVector<SDValue, 8> MemOpChains; const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy()); @@ -723,7 +723,7 @@ SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, // Check it to be lr const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); if (Reg == QRI->getRARegister()) { FuncInfo->setHasClobberLR(true); break; @@ -817,7 +817,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, // The Sub result contains the new stack start address, so it // must be placed in the stack pointer register. const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub); SDValue Ops[2] = { ArgAdjust, CopyChain }; @@ -964,8 +964,7 @@ HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { SDValue HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { - const TargetRegisterInfo *TRI = - DAG.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MFI->setReturnAddressIsTaken(true); @@ -992,7 +991,7 @@ HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { SDValue HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { const HexagonRegisterInfo *TRI = static_cast<const HexagonRegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setFrameAddressIsTaken(true); diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 1b0bb13b808..782c979588f 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -362,10 +362,9 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { LiveVariables &LVs = getAnalysis<LiveVariables>(); #endif - QII = static_cast<const HexagonInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); QRI = static_cast<const HexagonRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); if (!QRI->Subtarget.hasV4TOps() || diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index 97d33bb9310..8912152c943 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -111,8 +111,7 @@ INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole", false, false) bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { - QII = static_cast<const HexagonInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); QRI = MF.getTarget().getSubtarget<HexagonSubtarget>().getRegisterInfo(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index ed1e08cd593..29613d37176 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -128,14 +128,12 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Addressable stack objects are accessed using neg. offsets from %fp. MachineFunction &MF = *MI.getParent()->getParent(); const HexagonInstrInfo &TII = - *static_cast<const HexagonInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); MachineFrameInfo &MFI = *MF.getFrameInfo(); unsigned FrameReg = getFrameRegister(MF); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (!TFI->hasFP(MF)) { // We will not reserve space on the stack for the lr and fp registers. Offset -= 2 * Hexagon_WordSize; @@ -280,8 +278,7 @@ unsigned HexagonRegisterInfo::getRARegister() const { unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (TFI->hasFP(MF)) { return Hexagon::R30; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 697a87adc2f..632be030102 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -191,8 +191,7 @@ HexagonPacketizerList::HexagonPacketizerList( } bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) { - const TargetInstrInfo *TII = - Fn.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); const MachineBranchProbabilityInfo *MBPI = diff --git a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp index 1c05b4bd6fb..ffcf22216d4 100644 --- a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp +++ b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -54,8 +54,8 @@ FunctionPass *llvm::createMSP430BranchSelectionPass() { } bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) { - const MSP430InstrInfo *TII = static_cast<const MSP430InstrInfo *>( - Fn.getTarget().getSubtargetImpl()->getInstrInfo()); + const MSP430InstrInfo *TII = + static_cast<const MSP430InstrInfo *>(Fn.getSubtarget().getInstrInfo()); // Give the blocks of the function a dense, in-order, numbering. Fn.RenumberBlocks(); BlockSizes.resize(Fn.getNumBlockIDs()); diff --git a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp index 8ab83d7cf30..2902acf2088 100644 --- a/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp @@ -44,8 +44,7 @@ void MSP430FrameLowering::emitPrologue(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>(); const MSP430InstrInfo &TII = - *static_cast<const MSP430InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -110,8 +109,7 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF, const MachineFrameInfo *MFI = MF.getFrameInfo(); MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>(); const MSP430InstrInfo &TII = - *static_cast<const MSP430InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); unsigned RetOpcode = MBBI->getOpcode(); @@ -191,8 +189,7 @@ MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>(); MFI->setCalleeSavedFrameSize(CSI.size() * 2); @@ -218,8 +215,7 @@ MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); for (unsigned i = 0, e = CSI.size(); i != e; ++i) BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); @@ -231,8 +227,7 @@ void MSP430FrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const MSP430InstrInfo &TII = - *static_cast<const MSP430InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); unsigned StackAlign = getStackAlignment(); if (!hasReservedCallFrame(MF)) { diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index 280a4e4fe28..27681aae606 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -307,8 +307,7 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 0; case TargetOpcode::INLINEASM: { const MachineFunction *MF = MI->getParent()->getParent(); - const TargetInstrInfo &TII = - *MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MF->getTarget().getMCAsmInfo()); } diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp index 41de23862c8..afd7e070b7f 100644 --- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -37,8 +37,7 @@ MSP430RegisterInfo::MSP430RegisterInfo() const MCPhysReg* MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - const TargetFrameLowering *TFI = - MF->getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); const Function* F = MF->getFunction(); static const MCPhysReg CalleeSavedRegs[] = { MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, @@ -74,8 +73,7 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); // Mark 4 special registers with subregisters as reserved. Reserved.set(MSP430::PCB); @@ -111,8 +109,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); DebugLoc dl = MI.getDebugLoc(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); @@ -134,8 +131,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // This is actually "load effective address" of the stack slot // instruction. We have only two-address instructions, thus we need to // expand it into mov + add - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MI.setDesc(TII.get(MSP430::MOV16rr)); MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); @@ -160,8 +156,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW; } diff --git a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp index dcf33636b9f..6070276529e 100644 --- a/llvm/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/llvm/lib/Target/Mips/Mips16FrameLowering.cpp @@ -36,8 +36,7 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); uint64_t StackSize = MFI->getStackSize(); @@ -85,8 +84,7 @@ void Mips16FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineFrameInfo *MFI = MF.getFrameInfo(); const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); uint64_t StackSize = MFI->getStackSize(); @@ -156,8 +154,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, Amount = -Amount; const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); TII.adjustStackPtr(Mips::SP, Amount, MBB, I); } @@ -177,8 +174,7 @@ void Mips16FrameLowering:: processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); const MipsRegisterInfo &RI = TII.getRegisterInfo(); const BitVector Reserved = RI.getReservedRegs(MF); bool SaveS2 = Reserved[Mips::S2]; diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 4b5bedb8bee..7732be4b92e 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -72,8 +72,7 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); const TargetRegisterClass *RC = @@ -104,8 +103,7 @@ void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg(); diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp index 13be5c60424..0bb452a3f7d 100644 --- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -65,8 +65,7 @@ bool Mips16RegisterInfo::saveScavengerRegister const TargetRegisterClass *RC, unsigned Reg) const { DebugLoc DL; - const TargetInstrInfo &TII = - *MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); return true; @@ -107,8 +106,7 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) FrameReg = Mips::SP; else { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (TFI->hasFP(MF)) { FrameReg = Mips::S0; } @@ -143,7 +141,7 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned NewImm; const Mips16InstrInfo &TII = *static_cast<const Mips16InstrInfo *>( - MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + MBB.getParent()->getSubtarget().getInstrInfo()); FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); Offset = SignExtend64<16>(NewImm); IsKill = true; diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index f349897ff27..57c20a6cf48 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -563,7 +563,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { // identity mapping of CPI's to CPE's. const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants(); - const DataLayout &TD = *MF->getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout &TD = *MF->getSubtarget().getDataLayout(); for (unsigned i = 0, e = CPs.size(); i != e; ++i) { unsigned Size = TD.getTypeAllocSize(CPs[i].getType()); assert(Size >= 4 && "Too small constant pool entry"); diff --git a/llvm/lib/Target/Mips/MipsFrameLowering.cpp b/llvm/lib/Target/Mips/MipsFrameLowering.cpp index 042204441ef..3014a0d9534 100644 --- a/llvm/lib/Target/Mips/MipsFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsFrameLowering.cpp @@ -100,8 +100,7 @@ bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetRegisterInfo &TRI = - *MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); int64_t Offset = 0; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 4bdf77721c2..c90b9a5674e 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2474,8 +2474,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameLowering *TFL = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp index 2217fa9fb3f..22c524ea437 100644 --- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp +++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp @@ -130,8 +130,7 @@ static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { static void setCallTargetReg(MachineBasicBlock *MBB, MachineBasicBlock::iterator I) { MachineFunction &MF = *MBB->getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned SrcReg = I->getOperand(0).getReg(); unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64; BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg) diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 3649eafe0b9..ab371da72ca 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -62,8 +62,7 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case Mips::GPR32RegClassID: case Mips::GPR64RegClassID: case Mips::DSPRRegClassID: { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return 28 - TFI->hasFP(MF); } case Mips::FGR32RegClassID: @@ -162,7 +161,7 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(*Reg); } // Reserve FP if this function should have a dedicated frame pointer register. - if (MF.getTarget().getSubtargetImpl()->getFrameLowering()->hasFP(MF)) { + if (MF.getSubtarget().getFrameLowering()->hasFP(MF)) { if (Subtarget.inMips16Mode()) Reserved.set(Mips::S0); else { @@ -251,8 +250,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned MipsRegisterInfo:: getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); bool IsN64 = Subtarget.isABI_N64(); if (Subtarget.inMips16Mode()) diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index ad1af80c074..67f96d16fd0 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -147,11 +147,9 @@ void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); @@ -169,11 +167,9 @@ void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); @@ -194,11 +190,9 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); @@ -226,11 +220,9 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); @@ -263,11 +255,9 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, // copy dst_hi, $vr1 const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; @@ -422,11 +412,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -559,11 +547,9 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); DebugLoc dl = MBBI->getDebugLoc(); unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; @@ -616,8 +602,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); MachineBasicBlock *EntryBlock = MF->begin(); - const TargetInstrInfo &TII = - *MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is @@ -658,8 +643,7 @@ void MipsSEFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (!hasReservedCallFrame(MF)) { int64_t Amount = I->getOperand(0).getImm(); diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 1b0c17cdc5e..f7599052da0 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -130,8 +130,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); const TargetRegisterClass *RC; diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp index 0643fe8a30f..55c6638b45d 100644 --- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -172,7 +172,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned Reg = RegInfo.createVirtualRegister(RC); const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>( - MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + MBB.getParent()->getSubtarget().getInstrInfo()); BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset); FrameReg = Reg; @@ -187,7 +187,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned NewImm = 0; const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>( - MBB.getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + MBB.getParent()->getSubtarget().getInstrInfo()); unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, OffsetBitSize == 16 ? &NewImm : nullptr); BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index d9856dc15e1..ccf420962cd 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -97,6 +97,7 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { Subtarget = &NoMips16Subtarget; else Subtarget = &DefaultSubtarget; + MF->setSubtarget(Subtarget); return; } diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index 711b6f89d32..1264b25b04b 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -1773,8 +1773,7 @@ void NVPTXAsmPrinter::setAndEmitFunctionVirtualRegisters( // Map the global virtual register number to a register class specific // virtual register number starting from 1 with that class. - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); //unsigned numRegClasses = TRI->getNumRegClasses(); // Emit the Fake Stack Object diff --git a/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp index 761715f5786..314df3828b8 100644 --- a/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXFrameLowering.cpp @@ -48,24 +48,20 @@ void NVPTXFrameLowering::emitPrologue(MachineFunction &MF) const { if (is64bit) { unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass); MachineInstr *MI = - BuildMI(MBB, MBBI, dl, - MF.getTarget().getSubtargetImpl()->getInstrInfo()->get( - NVPTX::cvta_local_yes_64), + BuildMI(MBB, MBBI, dl, MF.getSubtarget().getInstrInfo()->get( + NVPTX::cvta_local_yes_64), NVPTX::VRFrame).addReg(LocalReg); BuildMI(MBB, MI, dl, - MF.getTarget().getSubtargetImpl()->getInstrInfo()->get( - NVPTX::MOV_DEPOT_ADDR_64), + MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR_64), LocalReg).addImm(MF.getFunctionNumber()); } else { unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass); MachineInstr *MI = BuildMI(MBB, MBBI, dl, - MF.getTarget().getSubtargetImpl()->getInstrInfo()->get( - NVPTX::cvta_local_yes), + MF.getSubtarget().getInstrInfo()->get(NVPTX::cvta_local_yes), NVPTX::VRFrame).addReg(LocalReg); BuildMI(MBB, MI, dl, - MF.getTarget().getSubtargetImpl()->getInstrInfo()->get( - NVPTX::MOV_DEPOT_ADDR), + MF.getSubtarget().getInstrInfo()->get(NVPTX::MOV_DEPOT_ADDR), LocalReg).addImm(MF.getFunctionNumber()); } } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 1e2d8712162..55951e64a38 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -2028,8 +2028,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments( const Function *F = MF.getFunction(); const AttributeSet &PAL = F->getAttributes(); - const TargetLowering *TLI = - DAG.getTarget().getSubtargetImpl()->getTargetLowering(); + const TargetLowering *TLI = DAG.getSubtarget().getTargetLowering(); SDValue Root = DAG.getRoot(); std::vector<SDValue> OutChains; diff --git a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp index 4db819795f7..a1e1b9e7448 100644 --- a/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp @@ -109,10 +109,8 @@ AdjustStackOffset(MachineFrameInfo *MFI, int FrameIdx, void NVPTXPrologEpilogPass::calculateFrameObjectOffsets(MachineFunction &Fn) { - const TargetFrameLowering &TFI = - *Fn.getTarget().getSubtargetImpl()->getFrameLowering(); - const TargetRegisterInfo *RegInfo = - Fn.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetFrameLowering &TFI = *Fn.getSubtarget().getFrameLowering(); + const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); bool StackGrowsDown = TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp index 3dd19d03e8b..41594be42ec 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -64,8 +64,8 @@ FunctionPass *llvm::createPPCBranchSelectionPass() { } bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) { - const PPCInstrInfo *TII = static_cast<const PPCInstrInfo *>( - Fn.getTarget().getSubtargetImpl()->getInstrInfo()); + const PPCInstrInfo *TII = + static_cast<const PPCInstrInfo *>(Fn.getSubtarget().getInstrInfo()); // Give the blocks of the function a dense, in-order, numbering. Fn.RenumberBlocks(); BlockSizes.resize(Fn.getNumBlockIDs()); diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index 51d88628262..dc87a6ca366 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -254,8 +254,7 @@ static void RemoveVRSaveCode(MachineInstr *MI) { // transform this into the appropriate ORI instruction. static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { MachineFunction *MF = MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); DebugLoc dl = MI->getDebugLoc(); unsigned UsedRegMask = 0; @@ -372,8 +371,8 @@ unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; - const PPCRegisterInfo *RegInfo = static_cast<const PPCRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); // If we are a leaf function, and use up to 224 bytes of stack space, // don't have a frame pointer, calls, or dynamic alloca then we do not need @@ -460,8 +459,8 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { unsigned FPReg = is31 ? PPC::R31 : PPC::R1; unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; - const PPCRegisterInfo *RegInfo = static_cast<const PPCRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); bool HasBP = RegInfo->hasBasePointer(MF); unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; @@ -499,10 +498,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); const PPCInstrInfo &TII = - *static_cast<const PPCInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const PPCRegisterInfo *RegInfo = static_cast<const PPCRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); @@ -826,10 +824,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert(MBBI != MBB.end() && "Returning block has no terminator"); const PPCInstrInfo &TII = - *static_cast<const PPCInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const PPCRegisterInfo *RegInfo = static_cast<const PPCRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); unsigned RetOpcode = MBBI->getOpcode(); DebugLoc dl; @@ -1071,8 +1068,8 @@ static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { void PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *) const { - const PPCRegisterInfo *RegInfo = static_cast<const PPCRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); // Save and clear the LR state. PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); @@ -1204,8 +1201,7 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, } PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); int64_t LowerBound = 0; @@ -1239,8 +1235,8 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); } - const PPCRegisterInfo *RegInfo = static_cast<const PPCRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const PPCRegisterInfo *RegInfo = + static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); if (RegInfo->hasBasePointer(MF)) { HasGPSaveArea = true; @@ -1388,8 +1384,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineFunction *MF = MBB.getParent(); const PPCInstrInfo &TII = - *static_cast<const PPCInstrInfo *>( - MF->getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo()); DebugLoc DL; bool CRSpilled = false; MachineInstrBuilder CRMIB; @@ -1451,8 +1446,7 @@ restoreCRs(bool isPPC64, bool is31, MachineFunction *MF = MBB.getParent(); const PPCInstrInfo &TII = - *static_cast<const PPCInstrInfo *>( - MF->getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo()); DebugLoc DL; unsigned RestoreOp, MoveReg; @@ -1485,8 +1479,7 @@ void PPCFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const PPCInstrInfo &TII = - *static_cast<const PPCInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (MF.getTarget().Options.GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { // Add (actually subtract) back the amount the callee popped on return. @@ -1536,8 +1529,7 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineFunction *MF = MBB.getParent(); const PPCInstrInfo &TII = - *static_cast<const PPCInstrInfo *>( - MF->getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo()); bool CR2Spilled = false; bool CR3Spilled = false; bool CR4Spilled = false; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 8ddfd776726..3e907888fb1 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -858,8 +858,7 @@ static bool isConstantOrUndef(int Op, int Val) { /// For the latter, the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) { - bool IsLE = - DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian(); + bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian(); if (ShuffleKind == 0) { if (IsLE) return false; @@ -890,8 +889,7 @@ bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, /// For the latter, the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) { - bool IsLE = - DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian(); + bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian(); if (ShuffleKind == 0) { if (IsLE) return false; @@ -946,7 +944,7 @@ static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, /// the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) { - if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) { + if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) { if (ShuffleKind == 1) // unary return isVMerge(N, UnitSize, 0, 0); else if (ShuffleKind == 2) // swapped @@ -971,7 +969,7 @@ bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, /// the input operands are swapped (see PPCInstrAltivec.td). bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) { - if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) { + if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) { if (ShuffleKind == 1) // unary return isVMerge(N, UnitSize, 8, 8); else if (ShuffleKind == 2) // swapped @@ -1078,7 +1076,7 @@ unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG) { ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); assert(isSplatShuffleMask(SVOp, EltSize)); - if (DAG.getTarget().getSubtargetImpl()->getDataLayout()->isLittleEndian()) + if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize); else return SVOp->getMaskElt(0) / EltSize; diff --git a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp index 9613b864c6b..4aff95a8a65 100644 --- a/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp @@ -18,7 +18,7 @@ using namespace llvm; void PPCFunctionInfo::anchor() { } MCSymbol *PPCFunctionInfo::getPICOffsetSymbol() const { - const DataLayout *DL = MF.getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *DL = MF.getSubtarget().getDataLayout(); return MF.getContext().GetOrCreateSymbol(Twine(DL->getPrivateGlobalPrefix())+ Twine(MF.getFunctionNumber())+"$poff"); } diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 5180ab1bf18..9b9966f6465 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -141,7 +141,7 @@ PPCRegisterInfo::getNoPreservedMask() const { BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( - MF.getTarget().getSubtargetImpl()->getFrameLowering()); + MF.getSubtarget().getFrameLowering()); // The ZERO register is not really a register, but the representation of r0 // when used in instructions that treat r0 as the constant 0. @@ -223,8 +223,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); const unsigned DefaultSafety = 1; switch (RC->getID()) { @@ -288,8 +287,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { // Get the frame info. MachineFrameInfo *MFI = MF.getFrameInfo(); // Get the instruction info. - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // Determine whether 64-bit pointers are used. bool LP64 = Subtarget.isPPC64(); DebugLoc dl = MI.getDebugLoc(); @@ -408,8 +406,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); bool LP64 = Subtarget.isPPC64(); @@ -453,8 +450,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); bool LP64 = Subtarget.isPPC64(); @@ -527,8 +523,7 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); bool LP64 = Subtarget.isPPC64(); @@ -571,8 +566,7 @@ void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); bool LP64 = Subtarget.isPPC64(); @@ -619,8 +613,7 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; @@ -645,8 +638,7 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc dl = MI.getDebugLoc(); const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; @@ -726,8 +718,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Get the basic block's function. MachineFunction &MF = *MBB.getParent(); // Get the instruction info. - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // Get the frame info. MachineFrameInfo *MFI = MF.getFrameInfo(); DebugLoc dl = MI.getDebugLoc(); @@ -852,8 +843,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (!Subtarget.isPPC64()) return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; @@ -939,7 +929,7 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { MachineFunction &MF = *MBB.getParent(); const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( - MF.getTarget().getSubtargetImpl()->getFrameLowering()); + MF.getSubtarget().getFrameLowering()); unsigned StackEst = PPCFI->determineFrameLayout(MF, false, true); @@ -973,8 +963,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB, DL = Ins->getDebugLoc(); const MachineFunction &MF = *MBB->getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const MCInstrDesc &MCID = TII.get(ADDriOpc); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); @@ -999,8 +988,7 @@ void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const MCInstrDesc &MCID = MI.getDesc(); MachineRegisterInfo &MRI = MF.getRegInfo(); MRI.constrainRegClass(BaseReg, diff --git a/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index 30c6576f086..d4c0987ad94 100644 --- a/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -822,8 +822,8 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc, SDLoc DL(Addr); MachineFunction &MF = CurDAG->getMachineFunction(); - const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const SIRegisterInfo *TRI = + static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); diff --git a/llvm/lib/Target/R600/AMDILCFGStructurizer.cpp b/llvm/lib/Target/R600/AMDILCFGStructurizer.cpp index 6cca81a0430..647de66b633 100644 --- a/llvm/lib/Target/R600/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/R600/AMDILCFGStructurizer.cpp @@ -161,8 +161,7 @@ public: bool prepare(); bool runOnMachineFunction(MachineFunction &MF) override { - TII = static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); TRI = &TII->getRegisterInfo(); DEBUG(MF.dump();); OrderedBlks.clear(); diff --git a/llvm/lib/Target/R600/R600ClauseMergePass.cpp b/llvm/lib/Target/R600/R600ClauseMergePass.cpp index 5ea1f03fb0b..f07be0001fb 100644 --- a/llvm/lib/Target/R600/R600ClauseMergePass.cpp +++ b/llvm/lib/Target/R600/R600ClauseMergePass.cpp @@ -168,8 +168,7 @@ bool R600ClauseMergePass::mergeIfPossible(MachineInstr *RootCFAlu, } bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); BB != BB_E; ++BB) { MachineBasicBlock &MBB = *BB; diff --git a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp index 8e7bc1079b7..08e3c59d83a 100644 --- a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -477,10 +477,9 @@ public: } bool runOnMachineFunction(MachineFunction &MF) override { - TII = static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); TRI = static_cast<const R600RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>(); CFStack CFStack(ST, MFI->getShaderType()); diff --git a/llvm/lib/Target/R600/R600EmitClauseMarkers.cpp b/llvm/lib/Target/R600/R600EmitClauseMarkers.cpp index ae59468b96f..fdc20302f4a 100644 --- a/llvm/lib/Target/R600/R600EmitClauseMarkers.cpp +++ b/llvm/lib/Target/R600/R600EmitClauseMarkers.cpp @@ -298,8 +298,7 @@ public: } bool runOnMachineFunction(MachineFunction &MF) override { - TII = static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); BB != BB_E; ++BB) { diff --git a/llvm/lib/Target/R600/R600ExpandSpecialInstrs.cpp b/llvm/lib/Target/R600/R600ExpandSpecialInstrs.cpp index 04b03c24eaa..211d392e8fc 100644 --- a/llvm/lib/Target/R600/R600ExpandSpecialInstrs.cpp +++ b/llvm/lib/Target/R600/R600ExpandSpecialInstrs.cpp @@ -66,8 +66,7 @@ void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI, } bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); const R600RegisterInfo &TRI = TII->getRegisterInfo(); diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index f6da0623427..aa51ac8ae39 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -191,8 +191,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( MachineFunction * MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); MachineBasicBlock::iterator I = *MI; - const R600InstrInfo *TII = static_cast<const R600InstrInfo *>( - MF->getTarget().getSubtargetImpl()->getInstrInfo()); + const R600InstrInfo *TII = + static_cast<const R600InstrInfo *>(MF->getSubtarget().getInstrInfo()); switch (MI->getOpcode()) { default: @@ -646,7 +646,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const if (ijb < 0) { const MachineFunction &MF = DAG.getMachineFunction(); const R600InstrInfo *TII = static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + MF.getSubtarget().getInstrInfo()); interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32)); return DAG.getTargetExtractSubreg( @@ -2081,8 +2081,8 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, static bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) { - const R600InstrInfo *TII = static_cast<const R600InstrInfo *>( - DAG.getTarget().getSubtargetImpl()->getInstrInfo()); + const R600InstrInfo *TII = + static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo()); if (!Src.isMachineOpcode()) return false; switch (Src.getMachineOpcode()) { @@ -2206,8 +2206,8 @@ FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, /// \brief Fold the instructions after selecting them SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, SelectionDAG &DAG) const { - const R600InstrInfo *TII = static_cast<const R600InstrInfo *>( - DAG.getTarget().getSubtargetImpl()->getInstrInfo()); + const R600InstrInfo *TII = + static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo()); if (!Node->isMachineOpcode()) return Node; unsigned Opcode = Node->getMachineOpcode(); diff --git a/llvm/lib/Target/R600/R600InstrInfo.cpp b/llvm/lib/Target/R600/R600InstrInfo.cpp index 6b32ca4f11e..ff1cedbb288 100644 --- a/llvm/lib/Target/R600/R600InstrInfo.cpp +++ b/llvm/lib/Target/R600/R600InstrInfo.cpp @@ -1084,7 +1084,7 @@ bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const { const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>( - MF.getTarget().getSubtargetImpl()->getFrameLowering()); + MF.getSubtarget().getFrameLowering()); unsigned StackWidth = TFL->getStackWidth(MF); int End = getIndirectIndexEnd(MF); diff --git a/llvm/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/R600/R600OptimizeVectorRegisters.cpp index 0d312c6d688..3b131d17365 100644 --- a/llvm/lib/Target/R600/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/R600/R600OptimizeVectorRegisters.cpp @@ -315,8 +315,7 @@ void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) { } bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { - TII = static_cast<const R600InstrInfo *>( - Fn.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const R600InstrInfo *>(Fn.getSubtarget().getInstrInfo()); MRI = &(Fn.getRegInfo()); for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); MBB != MBBe; ++MBB) { diff --git a/llvm/lib/Target/R600/R600Packetizer.cpp b/llvm/lib/Target/R600/R600Packetizer.cpp index a6d8c95f3f4..cb2eeeaaf7d 100644 --- a/llvm/lib/Target/R600/R600Packetizer.cpp +++ b/llvm/lib/Target/R600/R600Packetizer.cpp @@ -152,7 +152,7 @@ public: MachineDominatorTree &MDT) : VLIWPacketizerList(MF, MLI, MDT, true), TII(static_cast<const R600InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo())), + MF.getSubtarget().getInstrInfo())), TRI(TII->getRegisterInfo()) { VLIW5 = !MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA(); } @@ -329,8 +329,7 @@ public: }; bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) { - const TargetInstrInfo *TII = - Fn.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index 6372cc4c335..c108571fcfb 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -196,10 +196,10 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy, bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); - const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); - const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SIRegisterInfo *TRI = + static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); + const SIInstrInfo *TII = + static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo()); for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE; ++BI) { diff --git a/llvm/lib/Target/R600/SIFixSGPRLiveRanges.cpp b/llvm/lib/Target/R600/SIFixSGPRLiveRanges.cpp index c6a24362a72..fbc9aed207e 100644 --- a/llvm/lib/Target/R600/SIFixSGPRLiveRanges.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRLiveRanges.cpp @@ -73,8 +73,8 @@ FunctionPass *llvm::createSIFixSGPRLiveRangesPass() { bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); - const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const SIRegisterInfo *TRI = + static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); LiveIntervals *LIS = &getAnalysis<LiveIntervals>(); for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); diff --git a/llvm/lib/Target/R600/SIInsertWaits.cpp b/llvm/lib/Target/R600/SIInsertWaits.cpp index 555f97c0214..23ade02927c 100644 --- a/llvm/lib/Target/R600/SIInsertWaits.cpp +++ b/llvm/lib/Target/R600/SIInsertWaits.cpp @@ -347,10 +347,9 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) { bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) { bool Changes = false; - TII = static_cast<const SIInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - TRI = static_cast<const SIRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo()); + TRI = + static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index 2739fff1388..97c706b0655 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -443,10 +443,9 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) { } bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const SIInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - TRI = static_cast<const SIRegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo()); + TRI = + static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); bool HaveKill = false; diff --git a/llvm/lib/Target/R600/SILowerI1Copies.cpp b/llvm/lib/Target/R600/SILowerI1Copies.cpp index 0e77e3d22ab..234ee4c0c25 100644 --- a/llvm/lib/Target/R600/SILowerI1Copies.cpp +++ b/llvm/lib/Target/R600/SILowerI1Copies.cpp @@ -71,10 +71,9 @@ FunctionPass *llvm::createSILowerI1CopiesPass() { bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); - const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const SIInstrInfo *TII = + static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); std::vector<unsigned> I1Defs; for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); diff --git a/llvm/lib/Target/R600/SIShrinkInstructions.cpp b/llvm/lib/Target/R600/SIShrinkInstructions.cpp index 9d951a762b5..df7d80126ae 100644 --- a/llvm/lib/Target/R600/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/R600/SIShrinkInstructions.cpp @@ -177,8 +177,8 @@ static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo &MRI = MF.getRegInfo(); - const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SIInstrInfo *TII = + static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo()); const SIRegisterInfo &TRI = TII->getRegisterInfo(); std::vector<unsigned> I1Defs; diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index 16db38733c5..1b67b4b3403 100644 --- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -46,8 +46,7 @@ void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF, DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (NumBytes >= -4096 && NumBytes < 4096) { BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) @@ -89,8 +88,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -155,8 +153,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); assert(MBBI->getOpcode() == SP::RETL && "Can only put epilog before 'retl' instruction!"); diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index dbf9ed66949..3cca98f0ca1 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -108,8 +108,7 @@ static void replaceFI(MachineFunction &MF, return; } - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // FIXME: it would be better to scavenge a register here instead of // reserving G1 all of the time. @@ -175,8 +174,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { if (MI.getOpcode() == SP::STQFri) { - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); @@ -188,8 +186,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(2).setReg(SrcOddReg); Offset += 8; } else if (MI.getOpcode() == SP::LDQFri) { - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned DestReg = MI.getOperand(0).getReg(); unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index 474eb9b56c3..1ea02984f3d 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -458,8 +458,7 @@ bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) { } bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) { - TII = static_cast<const SystemZInstrInfo *>( - F.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo()); TRI = &TII->getRegisterInfo(); bool Changed = false; diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp index df62d9c324a..db1a005353b 100644 --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -66,8 +66,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { MachineFrameInfo *MFFrame = MF.getFrameInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); bool HasFP = hasFP(MF); SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); bool IsVarArg = MF.getFunction()->isVarArg(); @@ -111,7 +110,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF, static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, unsigned GPR64, bool IsImplicit) { const TargetRegisterInfo *RI = - MBB.getParent()->getTarget().getSubtargetImpl()->getRegisterInfo(); + MBB.getParent()->getSubtarget().getRegisterInfo(); unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); if (!IsLive || !IsImplicit) { @@ -130,8 +129,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, return false; MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>(); bool IsVarArg = MF.getFunction()->isVarArg(); DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -220,8 +218,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, return false; MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>(); bool HasFP = hasFP(MF); DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -315,8 +312,8 @@ static void emitIncrement(MachineBasicBlock &MBB, void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFFrame = MF.getFrameInfo(); - auto *ZII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + auto *ZII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>(); MachineBasicBlock::iterator MBBI = MBB.begin(); MachineModuleInfo &MMI = MF.getMMI(); @@ -412,8 +409,8 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const { void SystemZFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); - auto *ZII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + auto *ZII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>(); // Skip the return instruction. diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index dc6cebf2ed9..721d3c2a36e 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -675,7 +675,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, SystemZMachineFunctionInfo *FuncInfo = MF.getInfo<SystemZMachineFunctionInfo>(); auto *TFL = static_cast<const SystemZFrameLowering *>( - DAG.getTarget().getSubtargetImpl()->getFrameLowering()); + DAG.getSubtarget().getFrameLowering()); // Assign locations to all of the incoming arguments. SmallVector<CCValAssign, 16> ArgLocs; @@ -2616,7 +2616,7 @@ MachineBasicBlock * SystemZTargetLowering::emitSelect(MachineInstr *MI, MachineBasicBlock *MBB) const { const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MBB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + MBB->getParent()->getSubtarget().getInstrInfo()); unsigned DestReg = MI->getOperand(0).getReg(); unsigned TrueReg = MI->getOperand(1).getReg(); @@ -2665,7 +2665,7 @@ SystemZTargetLowering::emitCondStore(MachineInstr *MI, unsigned StoreOpcode, unsigned STOCOpcode, bool Invert) const { const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MBB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + MBB->getParent()->getSubtarget().getInstrInfo()); unsigned SrcReg = MI->getOperand(0).getReg(); MachineOperand Base = MI->getOperand(1); @@ -2733,8 +2733,8 @@ SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI, unsigned BitSize, bool Invert) const { MachineFunction &MF = *MBB->getParent(); - const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SystemZInstrInfo *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); bool IsSubWord = (BitSize < 32); @@ -2857,8 +2857,8 @@ SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI, unsigned KeepOldMask, unsigned BitSize) const { MachineFunction &MF = *MBB->getParent(); - const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SystemZInstrInfo *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); bool IsSubWord = (BitSize < 32); @@ -2969,8 +2969,8 @@ MachineBasicBlock * SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI, MachineBasicBlock *MBB) const { MachineFunction &MF = *MBB->getParent(); - const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SystemZInstrInfo *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); // Extract the operands. Base can be a register or a frame index. @@ -3086,8 +3086,8 @@ SystemZTargetLowering::emitExt128(MachineInstr *MI, MachineBasicBlock *MBB, bool ClearEven, unsigned SubReg) const { MachineFunction &MF = *MBB->getParent(); - const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SystemZInstrInfo *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); DebugLoc DL = MI->getDebugLoc(); @@ -3118,8 +3118,8 @@ SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const { MachineFunction &MF = *MBB->getParent(); - const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SystemZInstrInfo *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); DebugLoc DL = MI->getDebugLoc(); @@ -3288,8 +3288,8 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const { MachineFunction &MF = *MBB->getParent(); - const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const SystemZInstrInfo *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); DebugLoc DL = MI->getDebugLoc(); diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp index 5274c1a2ce5..8dab44e7f8a 100644 --- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -448,8 +448,7 @@ void SystemZLongBranch::relaxBranches() { } bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) { - TII = static_cast<const SystemZInstrInfo *>( - F.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo()); MF = &F; uint64_t Size = initMBBInfo(); if (Size <= MaxForwardRange || !mustRelaxABranch()) diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp index ba318023c24..64f5eebf37c 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -35,8 +35,7 @@ SystemZRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (TFI->hasFP(MF)) { // R11D is the frame pointer. Reserve all aliases. @@ -62,10 +61,9 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, MachineBasicBlock &MBB = *MI->getParent(); MachineFunction &MF = *MBB.getParent(); - auto *TII = static_cast<const SystemZInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + auto *TII = + static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); DebugLoc DL = MI->getDebugLoc(); // Decompose the frame index into a base and offset. @@ -136,7 +134,6 @@ SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, unsigned SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D; } diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp index a717dad751f..ec7a8c40d18 100644 --- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -150,8 +150,7 @@ bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) { } bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) { - TII = static_cast<const SystemZInstrInfo *>( - F.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo()); bool Changed = false; for (auto &MBB : F) diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index dfbfefa3915..6883fc01493 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -311,7 +311,7 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) { if (!FPIsUsed) return false; Bundles = &getAnalysis<EdgeBundles>(); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TII = MF.getSubtarget().getInstrInfo(); // Prepare cross-MBB liveness. bundleCFG(MF); @@ -1647,7 +1647,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { void FPS::setKillFlags(MachineBasicBlock &MBB) const { const TargetRegisterInfo *TRI = - MBB.getParent()->getTarget().getSubtargetImpl()->getRegisterInfo(); + MBB.getParent()->getSubtarget().getRegisterInfo(); LivePhysRegs LPR(TRI); LPR.addLiveOuts(&MBB); diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index d078c4d18cd..f17e5a34e50 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -46,8 +46,7 @@ bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { bool X86FrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineModuleInfo &MMI = MF.getMMI(); - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); return (MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->needsStackRealignment(MF) || @@ -315,8 +314,7 @@ X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // Add callee saved registers to move list. const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); @@ -441,10 +439,9 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *Fn = MF.getFunction(); - const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const X86RegisterInfo *RegInfo = + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineModuleInfo &MMI = MF.getMMI(); X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. @@ -836,10 +833,9 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); - const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const X86RegisterInfo *RegInfo = + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert(MBBI != MBB.end() && "Returning block has no instructions"); unsigned RetOpcode = MBBI->getOpcode(); @@ -1049,8 +1045,8 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { - const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const X86RegisterInfo *RegInfo = + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()); const MachineFrameInfo *MFI = MF.getFrameInfo(); int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea(); uint64_t StackSize = MFI->getStackSize(); @@ -1092,8 +1088,8 @@ int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const { - const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const X86RegisterInfo *RegInfo = + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()); // We can't calculate offset from frame pointer if the stack is realigned, // so enforce usage of stack/base pointer. The base pointer is used when we // have dynamic allocas in addition to dynamic realignment. @@ -1110,8 +1106,8 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots( MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const { MachineFrameInfo *MFI = MF.getFrameInfo(); - const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const X86RegisterInfo *RegInfo = + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()); unsigned SlotSize = RegInfo->getSlotSize(); X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); @@ -1178,8 +1174,7 @@ bool X86FrameLowering::spillCalleeSavedRegisters( DebugLoc DL = MBB.findDebugLoc(MI); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>(); // Push GPRs. It increases frame size. @@ -1227,8 +1222,7 @@ bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, DebugLoc DL = MBB.findDebugLoc(MI); MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>(); // Reload XMMs from stack frame. @@ -1259,8 +1253,8 @@ void X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { MachineFrameInfo *MFI = MF.getFrameInfo(); - const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const X86RegisterInfo *RegInfo = + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()); unsigned SlotSize = RegInfo->getSlotSize(); X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); @@ -1337,8 +1331,7 @@ void X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { MachineBasicBlock &prologueMBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); uint64_t StackSize; const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>(); bool Is64Bit = STI.is64Bit(); @@ -1547,12 +1540,11 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { /// temp0 = sp - MaxStack /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const { - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); const unsigned SlotSize = - static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo())->getSlotSize(); + static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo()) + ->getSlotSize(); const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>(); const bool Is64Bit = STI.is64Bit(); DebugLoc DL; @@ -1682,11 +1674,9 @@ void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const { void X86FrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); - const X86RegisterInfo &RegInfo = - *static_cast<const X86RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); unsigned StackPtr = RegInfo.getStackRegister(); bool reseveCallFrame = hasReservedCallFrame(MF); int Opcode = I->getOpcode(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index be985fef602..88972a9a893 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2457,8 +2457,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, TotalNumXMMRegs = 0; if (IsWin64) { - const TargetFrameLowering &TFI = - *MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering(); // Get to the caller-allocated home save location. Add 8 to account // for the return address. int HomeOffset = TFI.getOffsetOfLocalArea() + 8; @@ -2723,7 +2722,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Walk the register/memloc assignments, inserting copies/loads. In the case // of tail call optimization arguments are handle later. const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { // Skip inalloca arguments, they have already been written. ISD::ArgFlagsTy Flags = Outs[i].Flags; @@ -3019,8 +3018,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second.getValueType())); // Add a register mask operand representing the call-preserved registers. - const TargetRegisterInfo *TRI = - DAG.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); @@ -3227,7 +3225,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to // emit a special epilogue. const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); if (RegInfo->needsStackRealignment(MF)) return false; @@ -3339,8 +3337,8 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, // the caller's fixed stack objects. MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineRegisterInfo *MRI = &MF.getRegInfo(); - const X86InstrInfo *TII = static_cast<const X86InstrInfo *>( - DAG.getTarget().getSubtargetImpl()->getInstrInfo()); + const X86InstrInfo *TII = + static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo()); for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; SDValue Arg = OutVals[i]; @@ -3493,7 +3491,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); int ReturnAddrIndex = FuncInfo->getRAIndex(); @@ -13608,8 +13606,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); Chain = SP.getValue(1); unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); - const TargetFrameLowering &TFI = - *DAG.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering(); unsigned StackAlign = TFI.getStackAlignment(); Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value if (Align > StackAlign) @@ -13668,7 +13665,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); unsigned SPReg = RegInfo->getStackRegister(); SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy); Chain = SP.getValue(1); @@ -15048,7 +15045,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, if (Depth > 0) { SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT); return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, PtrVT, @@ -15070,7 +15067,7 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); // FIXME probably not meaningful unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction()); assert(((FrameReg == X86::RBP && VT == MVT::i64) || (FrameReg == X86::EBP && VT == MVT::i32)) && @@ -15099,7 +15096,7 @@ unsigned X86TargetLowering::getRegisterByName(const char* RegName, SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const { const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize()); } @@ -15111,7 +15108,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { EVT PtrVT = getPointerTy(); const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction()); assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) || (FrameReg == X86::EBP && PtrVT == MVT::i32)) && @@ -15158,8 +15155,7 @@ SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, SDLoc dl (Op); const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); - const TargetRegisterInfo *TRI = - DAG.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo(); if (Subtarget->is64Bit()) { SDValue OutChains[6]; @@ -17562,8 +17558,7 @@ X86TargetLowering::EmitVAARG64WithCustomInserter( MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); // Machine Information - const TargetInstrInfo *TII = - MBB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); @@ -17819,8 +17814,7 @@ X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( XMMSaveMBB->addSuccessor(EndMBB); // Now add the instructions. - const TargetInstrInfo *TII = - MBB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned CountReg = MI->getOperand(0).getReg(); @@ -17903,8 +17897,7 @@ static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock * X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = - BB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the @@ -17931,7 +17924,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, // If the EFLAGS register isn't dead in the terminator, then claim that it's // live into the sink and copy blocks. const TargetRegisterInfo *TRI = - BB->getParent()->getTarget().getSubtargetImpl()->getRegisterInfo(); + BB->getParent()->getSubtarget().getRegisterInfo(); if (!MI->killsRegister(X86::EFLAGS) && !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { copy0MBB->addLiveIn(X86::EFLAGS); @@ -17973,8 +17966,7 @@ MachineBasicBlock * X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, bool Is64Bit) const { MachineFunction *MF = BB->getParent(); - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -18096,8 +18088,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, MachineBasicBlock * X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = - BB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); assert(!Subtarget->isTargetMacho()); @@ -18154,8 +18145,8 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, // or EAX and doing an indirect call. The return value will then // be in the normal return register. MachineFunction *F = BB->getParent(); - const X86InstrInfo *TII = static_cast<const X86InstrInfo *>( - F->getTarget().getSubtargetImpl()->getInstrInfo()); + const X86InstrInfo *TII = + static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo()); DebugLoc DL = MI->getDebugLoc(); assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); @@ -18212,8 +18203,7 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, MachineBasicBlock *MBB) const { DebugLoc DL = MI->getDebugLoc(); MachineFunction *MF = MBB->getParent(); - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF->getRegInfo(); const BasicBlock *BB = MBB->getBasicBlock(); @@ -18320,7 +18310,7 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, .addMBB(restoreMBB); const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF->getTarget().getSubtargetImpl()->getRegisterInfo()); + MF->getSubtarget().getRegisterInfo()); MIB.addRegMask(RegInfo->getNoPreservedMask()); thisMBB->addSuccessor(mainMBB); thisMBB->addSuccessor(restoreMBB); @@ -18350,8 +18340,7 @@ X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, MachineBasicBlock *MBB) const { DebugLoc DL = MI->getDebugLoc(); MachineFunction *MF = MBB->getParent(); - const TargetInstrInfo *TII = - MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF->getRegInfo(); // Memory Reference @@ -18367,7 +18356,7 @@ X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, unsigned Tmp = MRI.createVirtualRegister(RC); // Since FP is only updated here but NOT referenced, it's treated as GPR. const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( - MF->getTarget().getSubtargetImpl()->getRegisterInfo()); + MF->getSubtarget().getRegisterInfo()); unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; unsigned SP = RegInfo->getStackRegister(); @@ -18477,8 +18466,7 @@ X86TargetLowering::emitFMA3Instr(MachineInstr *MI, default: llvm_unreachable("Unrecognized FMA variant."); } - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc)) .addOperand(MI->getOperand(0)) @@ -18544,8 +18532,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, case X86::FP80_TO_INT32_IN_MEM: case X86::FP80_TO_INT64_IN_MEM: { MachineFunction *F = BB->getParent(); - const TargetInstrInfo *TII = - F->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // Change the floating point control register to use "round towards zero" @@ -18629,9 +18616,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, case X86::VPCMPESTRM128MEM: assert(Subtarget->hasSSE42() && "Target must have SSE4.2 or AVX features enabled"); - return EmitPCMPSTRM( - MI, BB, - BB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo()); // String/text processing lowering. case X86::PCMPISTRIREG: @@ -18644,21 +18629,16 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, case X86::VPCMPESTRIMEM: assert(Subtarget->hasSSE42() && "Target must have SSE4.2 or AVX features enabled"); - return EmitPCMPSTRI( - MI, BB, - BB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo()); // Thread synchronization. case X86::MONITOR: - return EmitMonitor( - MI, BB, BB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo(), - Subtarget); + return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(), + Subtarget); // xbegin case X86::XBEGIN: - return EmitXBegin( - MI, BB, - BB->getParent()->getTarget().getSubtargetImpl()->getInstrInfo()); + return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo()); case X86::VASTART_SAVE_XMM_REGS: return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index f273bb2800a..5b19b1237cc 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -196,8 +196,7 @@ X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { unsigned X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; switch (RC->getID()) { @@ -325,8 +324,7 @@ X86RegisterInfo::getNoPreservedMask() const { BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); // Set the stack-pointer register and its aliases as reserved. for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid(); @@ -461,8 +459,7 @@ bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (Reg == FramePtr && TFI->hasFP(MF)) { FrameIdx = MF.getFrameInfo()->getObjectIndexBegin(); @@ -479,8 +476,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); unsigned BasePtr; @@ -533,8 +529,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? FramePtr : StackPtr; } diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp index c6cb07537ae..edd9a429f8b 100644 --- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp +++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp @@ -204,7 +204,7 @@ X86SelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, // ESI might be used as a base pointer, in that case we can't simply overwrite // the register. Fall back to generic code. const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>( - DAG.getTarget().getSubtargetImpl()->getRegisterInfo()); + DAG.getSubtarget().getRegisterInfo()); if (TRI->hasBasePointer(DAG.getMachineFunction()) && TRI->getBaseRegister() == X86::ESI) return SDValue(); diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp index 33e14717455..d93baeb7002 100644 --- a/llvm/lib/Target/X86/X86VZeroUpper.cpp +++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp @@ -250,7 +250,7 @@ bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) { const X86Subtarget &ST = MF.getTarget().getSubtarget<X86Subtarget>(); if (!ST.hasAVX() || ST.hasAVX512()) return false; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); + TII = MF.getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); EverMadeChange = false; diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index 4bb7cd34a91..734ea6b2df3 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -227,8 +227,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { MachineModuleInfo *MMI = &MF.getMMI(); const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); // Debug location must be unknown since the first debug location is used // to determine the end of the prologue. @@ -264,8 +263,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { MBB.addLiveIn(XCore::LR); MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)); MIB.addImm(Adjusted); - MIB->addRegisterKilled( - XCore::LR, MF.getTarget().getSubtargetImpl()->getRegisterInfo(), true); + MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(), + true); if (emitFrameMoves) { EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4); unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true); @@ -327,7 +326,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { // We do not save/spill these registers. SmallVector<StackSlotInfo,2> SpillList; GetEHSpillList(SpillList, MFI, XFI, - MF.getTarget().getSubtargetImpl()->getTargetLowering()); + MF.getSubtarget().getTargetLowering()); assert(SpillList.size()==2 && "Unexpected SpillList size"); EmitCfiOffset(MBB, MBBI, dl, TII, MMI, MRI->getDwarfRegNum(SpillList[0].Reg, true), @@ -344,8 +343,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); DebugLoc dl = MBBI->getDebugLoc(); unsigned RetOpcode = MBBI->getOpcode(); @@ -360,8 +358,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, // 'Restore' the exception info the unwinder has placed into the stack // slots. SmallVector<StackSlotInfo,2> SpillList; - GetEHSpillList(SpillList, MFI, XFI, - MF.getTarget().getSubtargetImpl()->getTargetLowering()); + GetEHSpillList(SpillList, MFI, XFI, MF.getSubtarget().getTargetLowering()); RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList); // Return to the landing pad. @@ -419,8 +416,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, return true; MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = - *MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>(); bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); @@ -453,8 +449,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const{ MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = - *MF->getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); bool AtStart = MI == MBB.begin(); MachineBasicBlock::iterator BeforeI = MI; if (!AtStart) @@ -487,8 +482,7 @@ void XCoreFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (!hasReservedCallFrame(MF)) { // Turn the adjcallstackdown instruction into 'extsp <amt>' and the // adjcallstackup instruction into 'ldaw sp, sp[<amt>]' diff --git a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp index c758097c455..77292c4f8f5 100644 --- a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -44,8 +44,7 @@ FunctionPass *llvm::createXCoreFrameToArgsOffsetEliminationPass() { bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) { const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); unsigned StackSize = MF.getFrameInfo()->getStackSize(); for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp index 68e92435ef5..5c666ae59fb 100644 --- a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -222,8 +222,7 @@ const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF XCore::R8, XCore::R9, 0 }; - const TargetFrameLowering *TFI = - MF->getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); if (TFI->hasFP(*MF)) return CalleeSavedRegsFP; return CalleeSavedRegs; @@ -231,8 +230,7 @@ const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); Reserved.set(XCore::CP); Reserved.set(XCore::DP); @@ -270,11 +268,9 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineFunction &MF = *MI.getParent()->getParent(); const XCoreInstrInfo &TII = - *static_cast<const XCoreInstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo()); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int StackSize = MF.getFrameInfo()->getStackSize(); @@ -328,8 +324,7 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; } diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp index 213131acfd4..a34884480ce 100644 --- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp @@ -33,8 +33,7 @@ EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, // Call __memcpy_4 if the src, dst and size are all 4 byte aligned. if (!AlwaysInline && (Align & 3) == 0 && DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { - const TargetLowering &TLI = - *DAG.getTarget().getSubtargetImpl()->getTargetLowering(); + const TargetLowering &TLI = *DAG.getSubtarget().getTargetLowering(); TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; Entry.Ty = TLI.getDataLayout()->getIntPtrType(*DAG.getContext()); |
