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-rw-r--r--llvm/lib/Target/RISCV/RISCVInstrFormats.td100
1 files changed, 66 insertions, 34 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 383b73cf4e0..48f6cf8762d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -35,12 +35,40 @@ def InstFormatPseudo : InstFormat<0>;
def InstFormatR : InstFormat<1>;
def InstFormatI : InstFormat<2>;
def InstFormatS : InstFormat<3>;
-def InstFormatSB : InstFormat<4>;
+def InstFormatB : InstFormat<4>;
def InstFormatU : InstFormat<5>;
-def InstFormatOther : InstFormat<6>;
+def InstFormatJ : InstFormat<6>;
+def InstFormatOther : InstFormat<7>;
-class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstFormat format>
+// The following opcode names and match those given in Table 19.1 in the
+// RISC-V User-level ISA specification ("RISC-V base opcode map").
+class RISCVOpcode<bits<7> val> {
+ bits<7> Value = val;
+}
+def OPC_LOAD : RISCVOpcode<0b0000011>;
+def OPC_LOAD_FP : RISCVOpcode<0b0000111>;
+def OPC_MISC_MEM : RISCVOpcode<0b0001111>;
+def OPC_OP_IMM : RISCVOpcode<0b0010011>;
+def OPC_AUIPC : RISCVOpcode<0b0010111>;
+def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>;
+def OPC_STORE : RISCVOpcode<0b0100011>;
+def OPC_STORE_FP : RISCVOpcode<0b0100111>;
+def OPC_AMO : RISCVOpcode<0b0101111>;
+def OPC_OP : RISCVOpcode<0b0110011>;
+def OPC_LUI : RISCVOpcode<0b0110111>;
+def OPC_OP_32 : RISCVOpcode<0b0111011>;
+def OPC_MADD : RISCVOpcode<0b1000011>;
+def OPC_MSUB : RISCVOpcode<0b1000111>;
+def OPC_NMSUB : RISCVOpcode<0b1001011>;
+def OPC_NMADD : RISCVOpcode<0b1001111>;
+def OPC_OP_FP : RISCVOpcode<0b1010011>;
+def OPC_BRANCH : RISCVOpcode<0b1100011>;
+def OPC_JALR : RISCVOpcode<0b1100111>;
+def OPC_JAL : RISCVOpcode<0b1101111>;
+def OPC_SYSTEM : RISCVOpcode<0b1110011>;
+
+class RVInst<dag outs, dag ins, string opcodestr, string argstr,
+ list<dag> pattern, InstFormat format>
: Instruction {
field bits<32> Inst;
// SoftFail is a field the disassembler can use to provide a way for
@@ -58,7 +86,7 @@ class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern,
dag OutOperandList = outs;
dag InOperandList = ins;
- let AsmString = asmstr;
+ let AsmString = opcodestr # "\t" # argstr;
let Pattern = pattern;
let TSFlags{3-0} = format.Value;
@@ -66,14 +94,18 @@ class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern,
// Pseudo instructions
class Pseudo<dag outs, dag ins, list<dag> pattern>
- : RISCVInst<outs, ins, "", pattern, InstFormatPseudo> {
+ : RVInst<outs, ins, "", "", pattern, InstFormatPseudo> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
-class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
- string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern, InstFormatR>
-{
+// Instruction formats are listed in the order they appear in the RISC-V
+// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
+// RVInstRAtomic) sorted alphabetically.
+
+class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs2;
bits<5> rs1;
bits<5> rd;
@@ -83,12 +115,12 @@ class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
-class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : RISCVInst<outs, ins, asmstr, pattern, InstFormatI>
-{
+class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
bits<12> imm12;
bits<5> rs1;
bits<5> rd;
@@ -97,12 +129,12 @@ class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
-class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : RISCVInst<outs, ins, asmstr, pattern, InstFormatI>
-{
+class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
+ dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
bits<5> shamt;
bits<5> rs1;
bits<5> rd;
@@ -114,12 +146,12 @@ class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag in
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
-class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : RISCVInst<outs, ins, asmstr, pattern, InstFormatS>
-{
+class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {
bits<12> imm12;
bits<5> rs2;
bits<5> rs1;
@@ -129,12 +161,12 @@ class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = imm12{4-0};
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
-class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : RISCVInst<outs, ins, asmstr, pattern, InstFormatSB>
-{
+class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {
bits<12> imm12;
bits<5> rs2;
bits<5> rs1;
@@ -146,23 +178,23 @@ class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list
let Inst{14-12} = funct3;
let Inst{11-8} = imm12{3-0};
let Inst{7} = imm12{10};
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
-class FU<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : RISCVInst<outs, ins, asmstr, pattern, InstFormatU>
-{
+class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+ string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {
bits<20> imm20;
bits<5> rd;
let Inst{31-12} = imm20;
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
-class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
- : RISCVInst<outs, ins, asmstr, pattern, InstFormatU>
-{
+class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+ string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> {
bits<20> imm20;
bits<5> rd;
@@ -171,5 +203,5 @@ class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{20} = imm20{10};
let Inst{19-12} = imm20{18-11};
let Inst{11-7} = rd;
- let Opcode = opcode;
+ let Opcode = opcode.Value;
}
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