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Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
-rw-r--r--llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index f120800bdbe..cdc95daa806 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -305,6 +305,7 @@ static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
assert(decodeSImmOperand<6>(Inst, SImm6, Address, Decoder) ==
MCDisassembler::Success && "Invalid immediate");
+ (void)SImm6;
return MCDisassembler::Success;
}
@@ -316,6 +317,7 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
assert(decodeSImmOperand<6>(Inst, SImm6, Address, Decoder) ==
MCDisassembler::Success && "Invalid immediate");
+ (void)SImm6;
return MCDisassembler::Success;
}
@@ -328,6 +330,7 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
assert(decodeUImmOperand<6>(Inst, UImm6, Address, Decoder) ==
MCDisassembler::Success && "Invalid immediate");
+ (void)UImm6;
return MCDisassembler::Success;
}
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