1 files changed, 0 insertions, 89 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp
index 1d5b43f5954..09e319a3a5d 100644
--- a/llvm/lib/Target/R600/SIISelLowering.cpp
+++ b/llvm/lib/Target/R600/SIISelLowering.cpp
@@ -644,95 +644,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
     MI->eraseFromParent();
     break;
   }
-  case AMDGPU::FABS_SI: {
-    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
-    DebugLoc DL = MI->getDebugLoc();
-    unsigned DestReg = MI->getOperand(0).getReg();
-    unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
-      .addImm(0x7fffffff);
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), DestReg)
-      .addReg(MI->getOperand(1).getReg())
-      .addReg(Reg);
-    MI->eraseFromParent();
-    break;
-  }
-  case AMDGPU::FABS64_SI: {
-    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
-
-    DebugLoc DL = MI->getDebugLoc();
-    unsigned SuperReg = MI->getOperand(0).getReg();
-    unsigned SrcReg = MI->getOperand(1).getReg();
-
-    unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
-    // Copy the subregister to make sure it is the right register class.
-    unsigned VReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::COPY), VReg)
-      .addReg(SrcReg, 0, AMDGPU::sub1);
-
-    // We only need to mask the upper half of the register pair.
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_AND_B32_e32), TmpReg)
-      .addImm(0x7fffffff)
-      .addReg(VReg);
-
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
-      .addReg(SrcReg, 0, AMDGPU::sub0)
-      .addImm(AMDGPU::sub0)
-      .addReg(TmpReg)
-      .addImm(AMDGPU::sub1);
-    MI->eraseFromParent();
-    break;
-  }
-  case AMDGPU::FNEG_SI: {
-    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
-    DebugLoc DL = MI->getDebugLoc();
-    unsigned DestReg = MI->getOperand(0).getReg();
-    unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
-    // FIXME: Should use SALU instructions
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
-      .addImm(0x80000000);
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
-      .addReg(MI->getOperand(1).getReg())
-      .addReg(Reg);
-    MI->eraseFromParent();
-    break;
-  }
-  case AMDGPU::FNEG64_SI: {
-    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
-
-    DebugLoc DL = MI->getDebugLoc();
-    unsigned SrcReg = MI->getOperand(1).getReg();
-    unsigned DestReg = MI->getOperand(0).getReg();
-
-    unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-    unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
-
-    // FIXME: Should use SALU instructions
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), ImmReg)
-      .addImm(0x80000000);
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), TmpReg)
-      .addReg(SrcReg, 0, AMDGPU::sub1)
-      .addReg(ImmReg);
-
-    BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), DestReg)
-      .addReg(SrcReg, 0, AMDGPU::sub0)
-      .addImm(AMDGPU::sub0)
-      .addReg(TmpReg)
-      .addImm(AMDGPU::sub1);
-    MI->eraseFromParent();
-    break;
-  }
   case AMDGPU::FCLAMP_SI: {
     const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
         getTargetMachine().getSubtargetImpl()->getInstrInfo());