diff options
Diffstat (limited to 'llvm/lib/Target/R600/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 28881955156..dc9153d3e91 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -623,36 +623,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MI->eraseFromParent(); break; } - case AMDGPU::SI_BUFFER_RSRC: { - unsigned SuperReg = MI->getOperand(0).getReg(); - unsigned Args[4]; - for (unsigned i = 0, e = 4; i < e; ++i) { - MachineOperand &Arg = MI->getOperand(i + 1); - - if (Arg.isReg()) { - Args[i] = Arg.getReg(); - continue; - } - - assert(Arg.isImm()); - unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg) - .addImm(Arg.getImm()); - Args[i] = Reg; - } - BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), - SuperReg) - .addReg(Args[0]) - .addImm(AMDGPU::sub0) - .addReg(Args[1]) - .addImm(AMDGPU::sub1) - .addReg(Args[2]) - .addImm(AMDGPU::sub2) - .addReg(Args[3]) - .addImm(AMDGPU::sub3); - MI->eraseFromParent(); - break; - } case AMDGPU::V_SUB_F64: { unsigned DestReg = MI->getOperand(0).getReg(); BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg) |
