diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a82de6cab16..85731436c24 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14792,16 +14792,15 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -Register PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT, +Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { bool isPPC64 = Subtarget.isPPC64(); bool IsDarwinABI = Subtarget.isDarwinABI(); - if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) || - (!isPPC64 && VT != MVT::i32)) + bool is64Bit = isPPC64 && VT == LLT::scalar(64); + if (!is64Bit && VT != LLT::scalar(32)) report_fatal_error("Invalid register global variable type"); - bool is64Bit = isPPC64 && VT == MVT::i64; Register Reg = StringSwitch<Register>(RegName) .Case("r1", is64Bit ? PPC::X1 : PPC::R1) .Case("r2", (IsDarwinABI || isPPC64) ? Register() : PPC::R2) |
